NXP/FSL SoC driver updates for v5.1 take4
DPIO driver - Add support for cache stashing and enable it in dpaa2-eth driver GUTS driver - Make fsl_guts_get_svr() API internal in favor of more generic soc_device_match() -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEhb3UXAyxp6UQ0v6khtxQDvusFVQFAlx11WsACgkQhtxQDvus FVTxahAApjB6xxpMBkBlX4lZ+o3HdX/fyyjna6iZIdG5YPm2sGnlAQ7dZb/sLMCk 1U+s52hc+aowfL23/x6XDu6vk0Oa05Qc8qmqT5zAyzw8el5r0lFr6S6KI3QmlSBI 9m3CJTWMRMEJVPribWEIUb/DrrylKEHhZORRBeNqHBPV9J7yh/zvTc3zJiSRG4b5 Pl1l+iCykTvxazcoz/mXlM7qIe5jinFU5odhAnbbrK+2oPs0NjblLqPCQe96l3/3 NUVxO0pYqvHDDNc6SbIpylvLp8Yd3N3L+VmdfJiNDKIH1/19R47EBAXvNvWONcao DooHNVv3ltwJ3UB5aGcM9Pqr0qJyCtXzRcrfC5q5z7/kMJcTUxB1bbbfPlzsXqKi FvL2JpQwqAnF8IJh7Z81bdGIfHfl4YbbY3gp1x4keXo7zRyUtuS2+fkiE+Q/LaWL 3reJSDoXcPpozZ0ds5m4szbEB1vlm6zzCYpVXaXgZfr8uuV8OXG9CZ6Cl+OYyofc GkoyampBIWd8OLNfodOpa5GqcdPDgMZ4Ha8eafN3wNIT+PUYS0Eixy4tk+BNYjiw Yu4JHwZzbsGzLzpsT/BgYvznMXg3rpOTpak3WdeUb9VSlOE+vWngUSDMLiNRLdFE 1rJzCXBe43MOqYEfqc/FbffX+ddPpNWVUrRdMtKD5jYJm/luqKE= =tNfD -----END PGP SIGNATURE----- Merge tag 'soc-fsl-next-v5.1-4' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux into arm/drivers NXP/FSL SoC driver updates for v5.1 take4 DPIO driver - Add support for cache stashing and enable it in dpaa2-eth driver GUTS driver - Make fsl_guts_get_svr() API internal in favor of more generic soc_device_match() * tag 'soc-fsl-next-v5.1-4' of git://git.kernel.org/pub/scm/linux/kernel/git/leo/linux: dpaa2-eth: configure the cache stashing amount on a queue soc: fsl: dpio: configure cache stashing destination soc: fsl: dpio: enable frame data cache stashing per software portal soc: fsl: guts: make fsl_guts_get_svr() static Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
8ceb820b69
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@ -2303,9 +2303,14 @@ static int setup_rx_flow(struct dpaa2_eth_priv *priv,
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queue.destination.type = DPNI_DEST_DPCON;
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queue.destination.priority = 1;
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queue.user_context = (u64)(uintptr_t)fq;
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queue.flc.stash_control = 1;
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queue.flc.value &= 0xFFFFFFFFFFFFFFC0;
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/* 01 01 00 - data, annotation, flow context */
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queue.flc.value |= 0x14;
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err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
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DPNI_QUEUE_RX, 0, fq->flowid,
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DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST,
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DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST |
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DPNI_QUEUE_OPT_FLC,
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&queue);
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if (err) {
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dev_err(dev, "dpni_set_queue(RX) failed\n");
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@ -22,6 +22,7 @@ config FSL_GUTS
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config FSL_MC_DPIO
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tristate "QorIQ DPAA2 DPIO driver"
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depends on FSL_MC_BUS
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select SOC_BUS
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help
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Driver for the DPAA2 DPIO object. A DPIO provides queue and
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buffer management facilities for software to interact with
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@ -26,6 +26,7 @@
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#define DPIO_CMDID_DISABLE DPIO_CMD(0x003)
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#define DPIO_CMDID_GET_ATTR DPIO_CMD(0x004)
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#define DPIO_CMDID_RESET DPIO_CMD(0x005)
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#define DPIO_CMDID_SET_STASHING_DEST DPIO_CMD(0x120)
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struct dpio_cmd_open {
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__le32 dpio_id;
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@ -47,4 +48,8 @@ struct dpio_rsp_get_attr {
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__le32 qbman_version;
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};
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struct dpio_stashing_dest {
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u8 sdest;
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};
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#endif /* _FSL_DPIO_CMD_H */
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@ -14,6 +14,7 @@
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#include <linux/dma-mapping.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/sys_soc.h>
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#include <linux/fsl/mc.h>
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#include <soc/fsl/dpaa2-io.h>
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@ -32,6 +33,46 @@ struct dpio_priv {
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static cpumask_var_t cpus_unused_mask;
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static const struct soc_device_attribute ls1088a_soc[] = {
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{.family = "QorIQ LS1088A"},
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{ /* sentinel */ }
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};
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static const struct soc_device_attribute ls2080a_soc[] = {
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{.family = "QorIQ LS2080A"},
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{ /* sentinel */ }
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};
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static const struct soc_device_attribute ls2088a_soc[] = {
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{.family = "QorIQ LS2088A"},
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{ /* sentinel */ }
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};
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static const struct soc_device_attribute lx2160a_soc[] = {
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{.family = "QorIQ LX2160A"},
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{ /* sentinel */ }
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};
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static int dpaa2_dpio_get_cluster_sdest(struct fsl_mc_device *dpio_dev, int cpu)
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{
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int cluster_base, cluster_size;
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if (soc_device_match(ls1088a_soc)) {
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cluster_base = 2;
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cluster_size = 4;
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} else if (soc_device_match(ls2080a_soc) ||
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soc_device_match(ls2088a_soc) ||
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soc_device_match(lx2160a_soc)) {
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cluster_base = 0;
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cluster_size = 2;
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} else {
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dev_err(&dpio_dev->dev, "unknown SoC version\n");
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return -1;
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}
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return cluster_base + cpu / cluster_size;
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}
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static irqreturn_t dpio_irq_handler(int irq_num, void *arg)
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{
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struct device *dev = (struct device *)arg;
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@ -89,6 +130,7 @@ static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
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int err = -ENOMEM;
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struct device *dev = &dpio_dev->dev;
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int possible_next_cpu;
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int sdest;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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@ -145,6 +187,16 @@ static int dpaa2_dpio_probe(struct fsl_mc_device *dpio_dev)
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desc.cpu = possible_next_cpu;
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cpumask_clear_cpu(possible_next_cpu, cpus_unused_mask);
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sdest = dpaa2_dpio_get_cluster_sdest(dpio_dev, desc.cpu);
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if (sdest >= 0) {
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err = dpio_set_stashing_destination(dpio_dev->mc_io, 0,
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dpio_dev->mc_handle,
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sdest);
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if (err)
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dev_err(dev, "dpio_set_stashing_destination failed for cpu%d\n",
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desc.cpu);
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}
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/*
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* Set the CENA regs to be the cache inhibited area of the portal to
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* avoid coherency issues if a user migrates to another core.
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@ -166,6 +166,22 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io,
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return 0;
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}
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int dpio_set_stashing_destination(struct fsl_mc_io *mc_io,
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u32 cmd_flags,
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u16 token,
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u8 sdest)
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{
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struct fsl_mc_command cmd = { 0 };
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struct dpio_stashing_dest *dpio_cmd;
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cmd.header = mc_encode_cmd_header(DPIO_CMDID_SET_STASHING_DEST,
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cmd_flags, token);
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dpio_cmd = (struct dpio_stashing_dest *)cmd.params;
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dpio_cmd->sdest = sdest;
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return mc_send_command(mc_io, &cmd);
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}
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/**
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* dpio_get_api_version - Get Data Path I/O API version
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* @mc_io: Pointer to MC portal's DPIO object
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@ -75,6 +75,11 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io,
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u16 token,
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struct dpio_attr *attr);
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int dpio_set_stashing_destination(struct fsl_mc_io *mc_io,
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u32 cmd_flags,
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u16 token,
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u8 dest);
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int dpio_get_api_version(struct fsl_mc_io *mc_io,
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u32 cmd_flags,
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u16 *major_ver,
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@ -169,9 +169,9 @@ struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
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3, /* RPM: Valid bit mode, RCR in array mode */
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2, /* DCM: Discrete consumption ack mode */
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3, /* EPM: Valid bit mode, EQCR in array mode */
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0, /* mem stashing drop enable == FALSE */
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1, /* mem stashing drop enable == TRUE */
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1, /* mem stashing priority == TRUE */
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0, /* mem stashing enable == FALSE */
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1, /* mem stashing enable == TRUE */
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1, /* dequeue stashing priority == TRUE */
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0, /* dequeue stashing enable == FALSE */
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0); /* EQCR_CI stashing priority == FALSE */
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@ -115,7 +115,7 @@ static const struct fsl_soc_die_attr *fsl_soc_die_match(
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return NULL;
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}
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u32 fsl_guts_get_svr(void)
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static u32 fsl_guts_get_svr(void)
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{
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u32 svr = 0;
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@ -129,7 +129,6 @@ u32 fsl_guts_get_svr(void)
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return svr;
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}
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EXPORT_SYMBOL(fsl_guts_get_svr);
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static int fsl_guts_probe(struct platform_device *pdev)
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{
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@ -135,8 +135,6 @@ struct ccsr_guts {
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u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
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} __attribute__ ((packed));
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u32 fsl_guts_get_svr(void);
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/* Alternate function signal multiplex control */
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#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
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