drm/radeon: add vce dpm support for CI
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
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5ad6bf91ef
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8cd366823e
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@ -746,6 +746,14 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
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u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
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int i;
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if (rps->vce_active) {
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rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk;
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rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk;
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} else {
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rps->evclk = 0;
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rps->ecclk = 0;
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}
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if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
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ci_dpm_vblank_too_short(rdev))
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disable_mclk_switching = true;
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@ -804,6 +812,13 @@ static void ci_apply_state_adjust_rules(struct radeon_device *rdev,
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sclk = ps->performance_levels[0].sclk;
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}
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if (rps->vce_active) {
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if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk)
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sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk;
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if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk)
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mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk;
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}
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ps->performance_levels[0].sclk = sclk;
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ps->performance_levels[0].mclk = mclk;
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@ -3468,7 +3483,6 @@ static int ci_enable_uvd_dpm(struct radeon_device *rdev, bool enable)
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0 : -EINVAL;
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}
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#if 0
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static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
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{
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struct ci_power_info *pi = ci_get_pi(rdev);
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@ -3501,6 +3515,7 @@ static int ci_enable_vce_dpm(struct radeon_device *rdev, bool enable)
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0 : -EINVAL;
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}
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#if 0
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static int ci_enable_samu_dpm(struct radeon_device *rdev, bool enable)
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{
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struct ci_power_info *pi = ci_get_pi(rdev);
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@ -3587,7 +3602,6 @@ static int ci_update_uvd_dpm(struct radeon_device *rdev, bool gate)
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return ci_enable_uvd_dpm(rdev, !gate);
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}
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#if 0
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static u8 ci_get_vce_boot_level(struct radeon_device *rdev)
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{
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u8 i;
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@ -3608,13 +3622,11 @@ static int ci_update_vce_dpm(struct radeon_device *rdev,
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struct radeon_ps *radeon_current_state)
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{
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struct ci_power_info *pi = ci_get_pi(rdev);
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bool new_vce_clock_non_zero = (radeon_new_state->evclk != 0);
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bool old_vce_clock_non_zero = (radeon_current_state->evclk != 0);
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int ret = 0;
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u32 tmp;
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if (new_vce_clock_non_zero != old_vce_clock_non_zero) {
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if (new_vce_clock_non_zero) {
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if (radeon_current_state->evclk != radeon_new_state->evclk) {
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if (radeon_new_state->evclk) {
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pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev);
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tmp = RREG32_SMC(DPM_TABLE_475);
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@ -3630,6 +3642,7 @@ static int ci_update_vce_dpm(struct radeon_device *rdev,
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return ret;
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}
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#if 0
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static int ci_update_samu_dpm(struct radeon_device *rdev, bool gate)
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{
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return ci_enable_samu_dpm(rdev, gate);
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@ -4752,13 +4765,13 @@ int ci_dpm_set_power_state(struct radeon_device *rdev)
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DRM_ERROR("ci_generate_dpm_level_enable_mask failed\n");
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return ret;
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}
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#if 0
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ret = ci_update_vce_dpm(rdev, new_ps, old_ps);
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if (ret) {
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DRM_ERROR("ci_update_vce_dpm failed\n");
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return ret;
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}
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#endif
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ret = ci_update_sclk_t(rdev);
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if (ret) {
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DRM_ERROR("ci_update_sclk_t failed\n");
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@ -4995,6 +5008,21 @@ static int ci_parse_power_table(struct radeon_device *rdev)
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power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
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}
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rdev->pm.dpm.num_ps = state_array->ucNumEntries;
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/* fill in the vce power states */
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for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) {
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u32 sclk, mclk;
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clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx;
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clock_info = (union pplib_clock_info *)
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&clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
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sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
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sclk |= clock_info->ci.ucEngineClockHigh << 16;
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mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
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mclk |= clock_info->ci.ucMemoryClockHigh << 16;
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rdev->pm.dpm.vce_states[i].sclk = sclk;
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rdev->pm.dpm.vce_states[i].mclk = mclk;
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}
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return 0;
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}
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@ -5080,12 +5108,14 @@ int ci_dpm_init(struct radeon_device *rdev)
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ci_dpm_fini(rdev);
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return ret;
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}
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ret = ci_parse_power_table(rdev);
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ret = r600_parse_extended_power_table(rdev);
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if (ret) {
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ci_dpm_fini(rdev);
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return ret;
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}
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ret = r600_parse_extended_power_table(rdev);
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ret = ci_parse_power_table(rdev);
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if (ret) {
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ci_dpm_fini(rdev);
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return ret;
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