irqchip: Add LPC32xx interrupt controller driver
The change adds improved support of NXP LPC32xx MIC, SIC1 and SIC2 interrupt controllers. This is a list of new features in comparison to the legacy driver: * irq types are taken from device tree settings, no more need to hardcode them, * old driver is based on irq_domain_add_legacy, which causes problems with handling MIC hardware interrupt 0 produced by SIC1, * there is one driver for MIC, SIC1 and SIC2, no more need to handle them separately, e.g. have two separate handlers for SIC1 and SIC2, * the driver does not have any dependencies on hardcoded register offsets, * the driver is much simpler for maintenance, * SPARSE_IRQS option is supported. Legacy LPC32xx interrupt controller driver was broken since commit76ba59f836("genirq: Add irq_domain-aware core IRQ handler"), which requires a private interrupt handler, otherwise any SIC1 generated interrupt (mapped to MIC hwirq 0) breaks the kernel with the message "unexpected IRQ trap at vector 00". The change disables compilation of a legacy driver found at arch/arm/mach-lpc32xx/irq.c, the file will be removed in a separate commit. Fixes:76ba59f836("genirq: Add irq_domain-aware core IRQ handler") Tested-by: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This commit is contained in:
Vladimir Zapolskiy
Marc Zyngier
parent
f86c4fbd93
commit
8cb17b5ed0
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@ -531,6 +531,8 @@ config ARCH_LPC32XX
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select COMMON_CLK
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select CPU_ARM926T
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select GENERIC_CLOCKEVENTS
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select MULTI_IRQ_HANDLER
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select SPARSE_IRQ
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select USE_OF
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help
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Support for the NXP LPC32XX family of processors
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@ -206,7 +206,6 @@ static const char *const lpc32xx_dt_compat[] __initconst = {
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DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
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.atag_offset = 0x100,
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.map_io = lpc32xx_map_io,
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.init_irq = lpc32xx_init_irq,
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.init_machine = lpc3250_machine_init,
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.dt_compat = lpc32xx_dt_compat,
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MACHINE_END
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@ -7,6 +7,7 @@ obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2836.o
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obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
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obj-$(CONFIG_ARCH_LPC32XX) += irq-lpc32xx.o
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obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
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obj-$(CONFIG_IRQ_MXS) += irq-mxs.o
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obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
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@ -0,0 +1,238 @@
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/*
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* Copyright 2015-2016 Vladimir Zapolskiy <vz@mleia.com>
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/io.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/slab.h>
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#include <asm/exception.h>
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#define LPC32XX_INTC_MASK 0x00
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#define LPC32XX_INTC_RAW 0x04
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#define LPC32XX_INTC_STAT 0x08
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#define LPC32XX_INTC_POL 0x0C
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#define LPC32XX_INTC_TYPE 0x10
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#define LPC32XX_INTC_FIQ 0x14
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#define NR_LPC32XX_IC_IRQS 32
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struct lpc32xx_irq_chip {
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void __iomem *base;
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struct irq_domain *domain;
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struct irq_chip chip;
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};
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static struct lpc32xx_irq_chip *lpc32xx_mic_irqc;
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static inline u32 lpc32xx_ic_read(struct lpc32xx_irq_chip *ic, u32 reg)
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{
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return readl_relaxed(ic->base + reg);
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}
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static inline void lpc32xx_ic_write(struct lpc32xx_irq_chip *ic,
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u32 reg, u32 val)
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{
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writel_relaxed(val, ic->base + reg);
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}
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static void lpc32xx_irq_mask(struct irq_data *d)
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{
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struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
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u32 val, mask = BIT(d->hwirq);
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val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) & ~mask;
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lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
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}
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static void lpc32xx_irq_unmask(struct irq_data *d)
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{
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struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
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u32 val, mask = BIT(d->hwirq);
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val = lpc32xx_ic_read(ic, LPC32XX_INTC_MASK) | mask;
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lpc32xx_ic_write(ic, LPC32XX_INTC_MASK, val);
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}
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static void lpc32xx_irq_ack(struct irq_data *d)
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{
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struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
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u32 mask = BIT(d->hwirq);
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lpc32xx_ic_write(ic, LPC32XX_INTC_RAW, mask);
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}
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static int lpc32xx_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct lpc32xx_irq_chip *ic = irq_data_get_irq_chip_data(d);
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u32 val, mask = BIT(d->hwirq);
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bool high, edge;
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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edge = true;
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high = true;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge = true;
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high = false;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge = false;
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high = true;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge = false;
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high = false;
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break;
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default:
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pr_info("unsupported irq type %d\n", type);
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return -EINVAL;
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}
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irqd_set_trigger_type(d, type);
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val = lpc32xx_ic_read(ic, LPC32XX_INTC_POL);
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if (high)
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val |= mask;
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else
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val &= ~mask;
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lpc32xx_ic_write(ic, LPC32XX_INTC_POL, val);
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val = lpc32xx_ic_read(ic, LPC32XX_INTC_TYPE);
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if (edge) {
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val |= mask;
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irq_set_handler_locked(d, handle_edge_irq);
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} else {
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val &= ~mask;
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irq_set_handler_locked(d, handle_level_irq);
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}
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lpc32xx_ic_write(ic, LPC32XX_INTC_TYPE, val);
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return 0;
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}
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static void __exception_irq_entry lpc32xx_handle_irq(struct pt_regs *regs)
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{
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struct lpc32xx_irq_chip *ic = lpc32xx_mic_irqc;
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u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
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while (hwirq) {
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irq = __ffs(hwirq);
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hwirq &= ~BIT(irq);
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handle_domain_irq(lpc32xx_mic_irqc->domain, irq, regs);
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}
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}
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static void lpc32xx_sic_handler(struct irq_desc *desc)
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{
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struct lpc32xx_irq_chip *ic = irq_desc_get_handler_data(desc);
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struct irq_chip *chip = irq_desc_get_chip(desc);
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u32 hwirq = lpc32xx_ic_read(ic, LPC32XX_INTC_STAT), irq;
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chained_irq_enter(chip, desc);
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while (hwirq) {
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irq = __ffs(hwirq);
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hwirq &= ~BIT(irq);
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generic_handle_irq(irq_find_mapping(ic->domain, irq));
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}
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chained_irq_exit(chip, desc);
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}
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static int lpc32xx_irq_domain_map(struct irq_domain *id, unsigned int virq,
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irq_hw_number_t hw)
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{
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struct lpc32xx_irq_chip *ic = id->host_data;
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irq_set_chip_data(virq, ic);
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irq_set_chip_and_handler(virq, &ic->chip, handle_level_irq);
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_noprobe(virq);
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return 0;
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}
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static void lpc32xx_irq_domain_unmap(struct irq_domain *id, unsigned int virq)
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{
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irq_set_chip_and_handler(virq, NULL, NULL);
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}
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static const struct irq_domain_ops lpc32xx_irq_domain_ops = {
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.map = lpc32xx_irq_domain_map,
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.unmap = lpc32xx_irq_domain_unmap,
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.xlate = irq_domain_xlate_twocell,
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};
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static int __init lpc32xx_of_ic_init(struct device_node *node,
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struct device_node *parent)
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{
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struct lpc32xx_irq_chip *irqc;
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bool is_mic = of_device_is_compatible(node, "nxp,lpc3220-mic");
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const __be32 *reg = of_get_property(node, "reg", NULL);
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u32 parent_irq, i, addr = reg ? be32_to_cpu(*reg) : 0;
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irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);
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if (!irqc)
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return -ENOMEM;
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irqc->base = of_iomap(node, 0);
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if (!irqc->base) {
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pr_err("%s: unable to map registers\n", node->full_name);
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kfree(irqc);
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return -EINVAL;
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}
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irqc->chip.irq_ack = lpc32xx_irq_ack;
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irqc->chip.irq_mask = lpc32xx_irq_mask;
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irqc->chip.irq_unmask = lpc32xx_irq_unmask;
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irqc->chip.irq_set_type = lpc32xx_irq_set_type;
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if (is_mic)
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irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.mic", addr);
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else
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irqc->chip.name = kasprintf(GFP_KERNEL, "%08x.sic", addr);
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irqc->domain = irq_domain_add_linear(node, NR_LPC32XX_IC_IRQS,
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&lpc32xx_irq_domain_ops, irqc);
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if (!irqc->domain) {
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pr_err("unable to add irq domain\n");
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iounmap(irqc->base);
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kfree(irqc->chip.name);
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kfree(irqc);
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return -ENODEV;
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}
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if (is_mic) {
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lpc32xx_mic_irqc = irqc;
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set_handle_irq(lpc32xx_handle_irq);
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} else {
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for (i = 0; i < of_irq_count(node); i++) {
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parent_irq = irq_of_parse_and_map(node, i);
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if (parent_irq)
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irq_set_chained_handler_and_data(parent_irq,
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lpc32xx_sic_handler, irqc);
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}
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}
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lpc32xx_ic_write(irqc, LPC32XX_INTC_MASK, 0x00);
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lpc32xx_ic_write(irqc, LPC32XX_INTC_POL, 0x00);
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lpc32xx_ic_write(irqc, LPC32XX_INTC_TYPE, 0x00);
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return 0;
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}
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IRQCHIP_DECLARE(nxp_lpc32xx_mic, "nxp,lpc3220-mic", lpc32xx_of_ic_init);
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IRQCHIP_DECLARE(nxp_lpc32xx_sic, "nxp,lpc3220-sic", lpc32xx_of_ic_init);
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