ARM: SoC 64-bit changes for v4.6
Here's our branch of ARM64 contents for this merge window, now
containing all ARM64 changes other than device tree files.
- Various new platforms get added
- Allwinner A64 SoC
- Annapurna Labs Alpine SoCs
- Broadcom Vulcan
- Marvell Armada 3700 SoCs
- Amlogic S905
- Various defconfig changes to enable platform specific drivers
This branch includes the clk git tree to resolve a build-time
dependency.
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Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC 64-bit changes from Arnd Bergmann:
"Here's our branch of ARM64 contents for this merge window, now
containing all ARM64 changes other than device tree files.
- Various new platforms get added:
* Allwinner A64 SoC
* Annapurna Labs Alpine SoCs
* Broadcom Vulcan
* Marvell Armada 3700 SoCs
* Amlogic S905
- Various defconfig changes to enable platform specific drivers
This branch includes the clk git tree to resolve a build-time
dependency"
* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
arm64: defconfig: Increase MMC_BLOCK_MINORS to 16
arm64: defconfig: Add Qualcomm sdhci and restart functionality
ARM64: Enable Amlogic Meson GXBaby platform
arm64: defconfig: Enable Samsung MFD and related configs
arm64: alpine: select the Alpine MSI controller driver
arm64: defconfig: enable the Alpine family
arm64: add Alpine SoC family
arm64: defconfig: Enable exynos thermal config
arm64: add defconfig options for Allwinner SoCs
arm64: defconfig: Enable DesignWare APB GPIO controller
arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
clk: samsung: Don't build ARMv8 clock drivers on ARMv7
MAINTAINERS: Add entry for Broadcom Vulcan SoC
arm64: cputype info for Broadcom Vulcan
arm64: Broadcom Vulcan support
arm64: defconfig: Add Broadcom Vulcan to defconfig
arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
Documentation: arm: add Marvell Armada 7K and 8K families
Documentation: arm: add link to Armada 38x Functional Spec
...
This commit is contained in:
Linus Torvalds
commit
8c6d4082fc
|
|
@ -22,7 +22,7 @@ Orion family
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|||
88F5281
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Datasheet : http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sheet.pdf
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88F6183
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Core: Feroceon ARMv5 compatible
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Core: Feroceon 88fr331 (88f51xx) or 88fr531-vd (88f52xx) ARMv5 compatible
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Linux kernel mach directory: arch/arm/mach-orion5x
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Linux kernel plat directory: arch/arm/plat-orion
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@ -52,7 +52,7 @@ Kirkwood family
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Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf
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Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf
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Homepage: http://www.marvell.com/embedded-processors/kirkwood/
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Core: Feroceon ARMv5 compatible
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Core: Feroceon 88fr131 ARMv5 compatible
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Linux kernel mach directory: arch/arm/mach-mvebu
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Linux kernel plat directory: none
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@ -71,7 +71,7 @@ Discovery family
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MV76100
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Not supported by the Linux kernel.
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Core: Feroceon ARMv5 compatible
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Core: Feroceon 88fr571-vd ARMv5 compatible
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Linux kernel mach directory: arch/arm/mach-mv78xx0
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Linux kernel plat directory: arch/arm/plat-orion
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@ -86,20 +86,26 @@ EBU Armada family
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Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf
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Hardware Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-datasheet.pdf
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Functional Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-FunctionalSpec-datasheet.pdf
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Core: Sheeva ARMv7 compatible PJ4B
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Armada 375 Flavors:
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88F6720
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Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA_375_SoC-01_product_brief.pdf
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Core: ARM Cortex-A9
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Armada 380/385 Flavors:
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88F6810
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88F6820
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88F6828
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Armada 38x Flavors:
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88F6810 Armada 380
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88F6820 Armada 385
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88F6828 Armada 388
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Product infos: http://www.marvell.com/embedded-processors/armada-38x/
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Functional Spec: https://marvellcorp.wufoo.com/forms/marvell-armada-38x-functional-specifications/
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Core: ARM Cortex-A9
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|
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Armada 390/398 Flavors:
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88F6920
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88F6928
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Armada 39x Flavors:
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88F6920 Armada 390
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88F6928 Armada 398
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Product infos: http://www.marvell.com/embedded-processors/armada-39x/
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Core: ARM Cortex-A9
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||||
|
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Armada XP Flavors:
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MV78230
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@ -112,12 +118,43 @@ EBU Armada family
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|||
http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78230_OS.PDF
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http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78260_OS.PDF
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http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78460_OS.PDF
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|
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Core: Sheeva ARMv7 compatible
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Core: Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP
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|
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Linux kernel mach directory: arch/arm/mach-mvebu
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Linux kernel plat directory: none
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|
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EBU Armada family ARMv8
|
||||
-----------------------
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||||
|
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Armada 3710/3720 Flavors:
|
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88F3710
|
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88F3720
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Core: ARM Cortex A53 (ARMv8)
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|
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Homepage: http://www.marvell.com/embedded-processors/armada-3700/
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Product Brief: http://www.marvell.com/embedded-processors/assets/PB-88F3700-FNL.pdf
|
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Device tree files: arch/arm64/boot/dts/marvell/armada-37*
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|
||||
Armada 7K Flavors:
|
||||
88F7020 (AP806 Dual + one CP110)
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88F7040 (AP806 Quad + one CP110)
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Core: ARM Cortex A72
|
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|
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Homepage: http://www.marvell.com/embedded-processors/armada-70xx/
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Product Brief: http://www.marvell.com/embedded-processors/assets/Armada7020PB-Jan2016.pdf
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http://www.marvell.com/embedded-processors/assets/Armada7040PB-Jan2016.pdf
|
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Device tree files: arch/arm64/boot/dts/marvell/armada-70*
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|
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Armada 8K Flavors:
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||||
88F8020 (AP806 Dual + two CP110)
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88F8040 (AP806 Quad + two CP110)
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Core: ARM Cortex A72
|
||||
|
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Homepage: http://www.marvell.com/embedded-processors/armada-80xx/
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Product Brief: http://www.marvell.com/embedded-processors/assets/Armada8020PB-Jan2016.pdf
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http://www.marvell.com/embedded-processors/assets/Armada8040PB-Jan2016.pdf
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Device tree files: arch/arm64/boot/dts/marvell/armada-80*
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|
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Avanta family
|
||||
-------------
|
||||
|
||||
|
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@ -135,6 +172,15 @@ Avanta family
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|||
Linux kernel mach directory: no code in mainline yet, planned for the future
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Linux kernel plat directory: no code in mainline yet, planned for the future
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Storage family
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||||
--------------
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|
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Armada SP:
|
||||
88RC1580
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||||
Product infos: http://www.marvell.com/storage/armada-sp/
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Core: Sheeva ARMv7 comatible Quad-core PJ4C
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||||
(not supported in upstream Linux kernel)
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||||
|
||||
Dove family (application processor)
|
||||
-----------------------------------
|
||||
|
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|
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@ -155,7 +201,7 @@ PXA 2xx/3xx/93x/95x family
|
|||
Flavors:
|
||||
PXA21x, PXA25x, PXA26x
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||||
Application processor only
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||||
Core: ARMv5 XScale core
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||||
Core: ARMv5 XScale1 core
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||||
PXA270, PXA271, PXA272
|
||||
Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_pb.pdf
|
||||
Design guide : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_design_guide.pdf
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||||
|
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@ -163,7 +209,7 @@ PXA 2xx/3xx/93x/95x family
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|||
Specification : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_emts.pdf
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||||
Specification update : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf
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||||
Application processor only
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||||
Core: ARMv5 XScale core
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||||
Core: ARMv5 XScale2 core
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||||
PXA300, PXA310, PXA320
|
||||
PXA 300 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA300_PB_R4.pdf
|
||||
PXA 310 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA310_PB_R4.pdf
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||||
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@ -174,10 +220,10 @@ PXA 2xx/3xx/93x/95x family
|
|||
Specification Update : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Spec_Update.zip
|
||||
Reference Manual : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_TavorP_BootROM_Ref_Manual.pdf
|
||||
Application processor only
|
||||
Core: ARMv5 XScale core
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||||
Core: ARMv5 XScale3 core
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||||
PXA930, PXA935
|
||||
Application processor with Communication processor
|
||||
Core: ARMv5 XScale core
|
||||
Core: ARMv5 XScale3 core
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||||
PXA955
|
||||
Application processor with Communication processor
|
||||
Core: ARMv7 compatible Sheeva PJ4 core
|
||||
|
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@ -196,7 +242,7 @@ PXA 2xx/3xx/93x/95x family
|
|||
Linux kernel mach directory: arch/arm/mach-pxa
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||||
Linux kernel plat directory: arch/arm/plat-pxa
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||||
|
||||
MMP/MMP2 family (communication processor)
|
||||
MMP/MMP2/MMP3 family (communication processor)
|
||||
-----------------------------------------
|
||||
|
||||
Flavors:
|
||||
|
|
@ -209,16 +255,32 @@ MMP/MMP2 family (communication processor)
|
|||
Boot ROM manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_ref_manual.pdf
|
||||
App node package : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_app_note_package.pdf
|
||||
Application processor only
|
||||
Core: ARMv5 compatible Marvell PJ1 (Mohawk)
|
||||
PXA910
|
||||
Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk)
|
||||
PXA910/PXA920
|
||||
Homepage : http://www.marvell.com/communication-processors/pxa910/
|
||||
Product Brief : http://www.marvell.com/communication-processors/pxa910/assets/Marvell_PXA910_Platform-001_PB_final.pdf
|
||||
Application processor with Communication processor
|
||||
Core: ARMv5 compatible Marvell PJ1 (Mohawk)
|
||||
MMP2, a.k.a Armada 610
|
||||
Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk)
|
||||
PXA688, a.k.a. MMP2, a.k.a Armada 610
|
||||
Product Brief : http://www.marvell.com/application-processors/armada-600/assets/armada610_pb.pdf
|
||||
Application processor only
|
||||
Core: ARMv7 compatible Sheeva PJ4 88sv581x core
|
||||
PXA2128, a.k.a. MMP3 (OLPC XO4, Linux support not upstream)
|
||||
Product Brief : http://www.marvell.com/application-processors/armada/pxa2128/assets/Marvell-ARMADA-PXA2128-SoC-PB.pdf
|
||||
Application processor only
|
||||
Core: Dual-core ARMv7 compatible Sheeva PJ4C core
|
||||
PXA960/PXA968/PXA978 (Linux support not upstream)
|
||||
Application processor with Communication Processor
|
||||
Core: ARMv7 compatible Sheeva PJ4 core
|
||||
PXA986/PXA988 (Linux support not upstream)
|
||||
Application processor with Communication Processor
|
||||
Core: Dual-core ARMv7 compatible Sheeva PJ4B-MP core
|
||||
PXA1088/PXA1920 (Linux support not upstream)
|
||||
Application processor with Communication Processor
|
||||
Core: quad-core ARMv7 Cortex-A7
|
||||
PXA1908/PXA1928/PXA1936
|
||||
Application processor with Communication Processor
|
||||
Core: multi-core ARMv8 Cortex-A53
|
||||
|
||||
Comments:
|
||||
|
||||
|
|
@ -237,6 +299,10 @@ Berlin family (Multimedia Solutions)
|
|||
-------------------------------------
|
||||
|
||||
Flavors:
|
||||
88DE3010, Armada 1000 (no Linux support)
|
||||
Core: Marvell PJ1 (ARMv5TE), Dual-core
|
||||
Product Brief: http://www.marvell.com.cn/digital-entertainment/assets/armada_1000_pb.pdf
|
||||
88DE3005, Armada 1500-mini
|
||||
88DE3005, Armada 1500 Mini
|
||||
Design name: BG2CD
|
||||
Core: ARM Cortex-A9, PL310 L2CC
|
||||
|
|
@ -247,14 +313,16 @@ Berlin family (Multimedia Solutions)
|
|||
Homepage: http://www.marvell.com/multimedia-solutions/armada-1500-mini-plus/
|
||||
88DE3100, Armada 1500
|
||||
Design name: BG2
|
||||
Core: Marvell PJ4B (ARMv7), Tauros3 L2CC
|
||||
Product Brief: http://www.marvell.com/multimedia-solutions/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
|
||||
Core: Marvell PJ4B-MP (ARMv7), Tauros3 L2CC
|
||||
Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf
|
||||
88DE3114, Armada 1500 Pro
|
||||
Design name: BG2Q
|
||||
Core: Quad Core ARM Cortex-A9, PL310 L2CC
|
||||
88DE????
|
||||
88DE3214, Armada 1500 Pro 4K
|
||||
Design name: BG3
|
||||
Core: ARM Cortex-A15, CA15 integrated L2CC
|
||||
88DE3218, ARMADA 1500 Ultra
|
||||
Core: ARM Cortex-A53
|
||||
|
||||
Homepage: http://www.marvell.com/multimedia-solutions/
|
||||
Directory: arch/arm/mach-berlin
|
||||
|
|
@ -263,6 +331,49 @@ Berlin family (Multimedia Solutions)
|
|||
* This line of SoCs is based on Marvell Sheeva or ARM Cortex CPUs
|
||||
with Synopsys DesignWare (IRQ, GPIO, Timers, ...) and PXA IP (SDHCI, USB, ETH, ...).
|
||||
|
||||
CPU Cores
|
||||
---------
|
||||
|
||||
The XScale cores were designed by Intel, and shipped by Marvell in the older
|
||||
PXA processors. Feroceon is a Marvell designed core that developed in-house,
|
||||
and that evolved into Sheeva. The XScale and Feroceon cores were phased out
|
||||
over time and replaced with Sheeva cores in later products, which subsequently
|
||||
got replaced with licensed ARM Cortex-A cores.
|
||||
|
||||
XScale 1
|
||||
CPUID 0x69052xxx
|
||||
ARMv5, iWMMXt
|
||||
XScale 2
|
||||
CPUID 0x69054xxx
|
||||
ARMv5, iWMMXt
|
||||
XScale 3
|
||||
CPUID 0x69056xxx or 0x69056xxx
|
||||
ARMv5, iWMMXt
|
||||
Feroceon-1850 88fr331 "Mohawk"
|
||||
CPUID 0x5615331x or 0x41xx926x
|
||||
ARMv5TE, single issue
|
||||
Feroceon-2850 88fr531-vd "Jolteon"
|
||||
CPUID 0x5605531x or 0x41xx926x
|
||||
ARMv5TE, VFP, dual-issue
|
||||
Feroceon 88fr571-vd "Jolteon"
|
||||
CPUID 0x5615571x
|
||||
ARMv5TE, VFP, dual-issue
|
||||
Feroceon 88fr131 "Mohawk-D"
|
||||
CPUID 0x5625131x
|
||||
ARMv5TE, single-issue in-order
|
||||
Sheeva PJ1 88sv331 "Mohawk"
|
||||
CPUID 0x561584xx
|
||||
ARMv5, single-issue iWMMXt v2
|
||||
Sheeva PJ4 88sv581x "Flareon"
|
||||
CPUID 0x560f581x
|
||||
ARMv7, idivt, optional iWMMXt v2
|
||||
Sheeva PJ4B 88sv581x
|
||||
CPUID 0x561f581x
|
||||
ARMv7, idivt, optional iWMMXt v2
|
||||
Sheeva PJ4B-MP / PJ4C
|
||||
CPUID 0x562f584x
|
||||
ARMv7, idivt/idiva, LPAE, optional iWMMXt v2 and/or NEON
|
||||
|
||||
Long-term plans
|
||||
---------------
|
||||
|
||||
|
|
|
|||
|
|
@ -9,6 +9,8 @@ Required properties:
|
|||
"apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock
|
||||
"apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock
|
||||
"apm,xgene-device-clock" - for a X-Gene device clock
|
||||
"apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock
|
||||
"apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock
|
||||
|
||||
Required properties for SoC or PCP PLL clocks:
|
||||
- reg : shall be the physical PLL register address for the pll clock.
|
||||
|
|
|
|||
|
|
@ -1307,6 +1307,7 @@ F: arch/arm/mach-mvebu/
|
|||
F: drivers/rtc/rtc-armada38x.c
|
||||
F: arch/arm/boot/dts/armada*
|
||||
F: arch/arm/boot/dts/kirkwood*
|
||||
F: arch/arm64/boot/dts/marvell/armada*
|
||||
|
||||
|
||||
ARM/Marvell Berlin SoC support
|
||||
|
|
@ -2552,6 +2553,13 @@ L: netdev@vger.kernel.org
|
|||
S: Supported
|
||||
F: drivers/net/ethernet/broadcom/bcmsysport.*
|
||||
|
||||
BROADCOM VULCAN ARM64 SOC
|
||||
M: Jayachandran C. <jchandra@broadcom.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
L: bcm-kernel-feedback-list@broadcom.com
|
||||
S: Maintained
|
||||
F: arch/arm64/boot/dts/broadcom/vulcan*
|
||||
|
||||
BROCADE BFA FC SCSI DRIVER
|
||||
M: Anil Gurumurthy <anil.gurumurthy@qlogic.com>
|
||||
M: Sudarsana Kalluru <sudarsana.kalluru@qlogic.com>
|
||||
|
|
|
|||
|
|
@ -26,12 +26,14 @@ CONFIG_ARM_APPENDED_DTB=y
|
|||
CONFIG_ARM_ATAG_DTB_COMPAT=y
|
||||
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_STAT_DETAILS=y
|
||||
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
|
||||
CONFIG_CPUFREQ_DT=y
|
||||
CONFIG_CPU_IDLE=y
|
||||
CONFIG_ARM_EXYNOS_CPUIDLE=y
|
||||
CONFIG_VFP=y
|
||||
CONFIG_NEON=y
|
||||
CONFIG_KERNEL_MODE_NEON=y
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
|
|
@ -193,7 +195,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
|||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_MAX8997=y
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
CONFIG_RTC_DRV_MAX77802=y
|
||||
CONFIG_RTC_DRV_S5M=y
|
||||
CONFIG_RTC_DRV_S3C=y
|
||||
CONFIG_DMADEVICES=y
|
||||
|
|
@ -238,7 +239,12 @@ CONFIG_DEBUG_RT_MUTEXES=y
|
|||
CONFIG_DEBUG_SPINLOCK=y
|
||||
CONFIG_DEBUG_MUTEXES=y
|
||||
CONFIG_DEBUG_USER=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_DEV_S5P=y
|
||||
CONFIG_ARM_CRYPTO=y
|
||||
CONFIG_CRYPTO_SHA1_ARM_NEON=m
|
||||
CONFIG_CRYPTO_SHA256_ARM=m
|
||||
CONFIG_CRYPTO_SHA512_ARM=m
|
||||
CONFIG_CRYPTO_AES_ARM_BS=m
|
||||
CONFIG_CRC_CCITT=y
|
||||
CONFIG_FONTS=y
|
||||
CONFIG_FONT_7x14=y
|
||||
|
|
|
|||
|
|
@ -665,7 +665,6 @@ CONFIG_RTC_DRV_MAX8907=y
|
|||
CONFIG_RTC_DRV_MAX8997=m
|
||||
CONFIG_RTC_DRV_MAX77686=y
|
||||
CONFIG_RTC_DRV_RK808=m
|
||||
CONFIG_RTC_DRV_MAX77802=m
|
||||
CONFIG_RTC_DRV_RS5C372=m
|
||||
CONFIG_RTC_DRV_PALMAS=y
|
||||
CONFIG_RTC_DRV_ST_LPC=y
|
||||
|
|
|
|||
|
|
@ -15,6 +15,7 @@ config PLAT_S3C24XX
|
|||
select NO_IOPORT_MAP
|
||||
select S3C_DEV_NAND
|
||||
select IRQ_DOMAIN
|
||||
select COMMON_CLK
|
||||
help
|
||||
Base platform code for any Samsung S3C24XX device
|
||||
|
||||
|
|
|
|||
|
|
@ -1,7 +1,22 @@
|
|||
menu "Platform selection"
|
||||
|
||||
config ARCH_SUNXI
|
||||
bool "Allwinner sunxi 64-bit SoC Family"
|
||||
help
|
||||
This enables support for Allwinner sunxi based SoCs like the A64.
|
||||
|
||||
config ARCH_ALPINE
|
||||
bool "Annapurna Labs Alpine platform"
|
||||
select ALPINE_MSI
|
||||
help
|
||||
This enables support for the Annapurna Labs Alpine
|
||||
Soc family.
|
||||
|
||||
config ARCH_BCM_IPROC
|
||||
bool "Broadcom iProc SoC Family"
|
||||
select COMMON_CLK_IPROC
|
||||
select PINCTRL
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
help
|
||||
This enables support for Broadcom iProc based SoCs
|
||||
|
||||
|
|
@ -14,21 +29,14 @@ config ARCH_BERLIN
|
|||
This enables support for Marvell Berlin SoC Family
|
||||
|
||||
config ARCH_EXYNOS
|
||||
bool
|
||||
help
|
||||
This enables support for Samsung Exynos SoC family
|
||||
|
||||
config ARCH_EXYNOS7
|
||||
bool "ARMv8 based Samsung Exynos7"
|
||||
select ARCH_EXYNOS
|
||||
bool "ARMv8 based Samsung Exynos SoC family"
|
||||
select COMMON_CLK_SAMSUNG
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select HAVE_S3C_RTC if RTC_CLASS
|
||||
select PINCTRL
|
||||
select PINCTRL_EXYNOS
|
||||
|
||||
help
|
||||
This enables support for Samsung Exynos7 SoC family
|
||||
This enables support for ARMv8 based Samsung Exynos SoC family.
|
||||
|
||||
config ARCH_LAYERSCAPE
|
||||
bool "ARMv8 based Freescale Layerscape SoC family"
|
||||
|
|
@ -48,6 +56,22 @@ config ARCH_MEDIATEK
|
|||
help
|
||||
Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
|
||||
|
||||
config ARCH_MESON
|
||||
bool "Amlogic Platforms"
|
||||
help
|
||||
This enables support for the Amlogic S905 SoCs.
|
||||
|
||||
config ARCH_MVEBU
|
||||
bool "Marvell EBU SoC Family"
|
||||
select ARMADA_AP806_CORE_CLK
|
||||
select ARMADA_AP806_RING_CLK
|
||||
select MVEBU_ODMI
|
||||
help
|
||||
This enables support for Marvell EBU familly, including:
|
||||
- Armada 3700 SoC Family
|
||||
- Armada 7K SoC Family
|
||||
- Armada 8K SoC Family
|
||||
|
||||
config ARCH_QCOM
|
||||
bool "Qualcomm Platforms"
|
||||
select PINCTRL
|
||||
|
|
@ -60,6 +84,7 @@ config ARCH_ROCKCHIP
|
|||
select ARCH_REQUIRE_GPIOLIB
|
||||
select PINCTRL
|
||||
select PINCTRL_ROCKCHIP
|
||||
select ROCKCHIP_TIMER
|
||||
help
|
||||
This enables support for the ARMv8 based Rockchip chipsets,
|
||||
like the RK3368.
|
||||
|
|
@ -76,7 +101,9 @@ config ARCH_RENESAS
|
|||
bool "Renesas SoC Platforms"
|
||||
select ARCH_SHMOBILE
|
||||
select PINCTRL
|
||||
select PM_GENERIC_DOMAINS if PM
|
||||
select PM
|
||||
select PM_GENERIC_DOMAINS
|
||||
select RENESAS_IRQC
|
||||
help
|
||||
This enables support for the ARMv8 based Renesas SoCs.
|
||||
|
||||
|
|
@ -131,6 +158,11 @@ config ARCH_VEXPRESS
|
|||
This enables support for the ARMv8 software model (Versatile
|
||||
Express).
|
||||
|
||||
config ARCH_VULCAN
|
||||
bool "Broadcom Vulcan SOC Family"
|
||||
help
|
||||
This enables support for Broadcom Vulcan SoC Family
|
||||
|
||||
config ARCH_XGENE
|
||||
bool "AppliedMicro X-Gene SOC Family"
|
||||
help
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb
|
||||
dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,33 @@
|
|||
/*
|
||||
* dts file for Broadcom (BRCM) Vulcan Evaluation Platform
|
||||
*
|
||||
* Copyright (c) 2013-2016 Broadcom
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "vulcan.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Broadcom Vulcan Eval Platform";
|
||||
compatible = "brcm,vulcan-eval", "brcm,vulcan-soc";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */
|
||||
<0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,144 @@
|
|||
/*
|
||||
* dtsi file for Broadcom (BRCM) Vulcan processor
|
||||
*
|
||||
* Copyright (c) 2013-2016 Broadcom
|
||||
* Author: Zi Shen Lim <zlim@broadcom.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
model = "Broadcom Vulcan";
|
||||
compatible = "brcm,vulcan-soc";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
/* just 4 cpus now, 128 needed in full config */
|
||||
cpus {
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "brcm,vulcan", "arm,armv8";
|
||||
reg = <0x0 0x0>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "brcm,vulcan", "arm,armv8";
|
||||
reg = <0x0 0x1>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "brcm,vulcan", "arm,armv8";
|
||||
reg = <0x0 0x2>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "brcm,vulcan", "arm,armv8";
|
||||
reg = <0x0 0x3>;
|
||||
enable-method = "psci";
|
||||
};
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@400080000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
#redistributor-regions = <1>;
|
||||
reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
|
||||
<0x04 0x01000000 0x0 0x1000000>; /* GICR */
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
gicits: gic-its@40010000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; /* PMU overflow */
|
||||
};
|
||||
|
||||
clk125mhz: uart_clk125mhz {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "clk125mhz";
|
||||
};
|
||||
|
||||
pci {
|
||||
compatible = "pci-host-ecam-generic";
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
/* ECAM at 0x3000_0000 - 0x4000_0000 */
|
||||
reg = <0x0 0x30000000 0x0 0x10000000>;
|
||||
reg-names = "PCI ECAM";
|
||||
|
||||
/* IO 0x4000_0000 - 0x4001_0000 */
|
||||
ranges = <0x01000000 0 0x40000000 0 0x40000000 0 0x00010000
|
||||
/* MEM 0x4800_0000 - 0x5000_0000 */
|
||||
0x02000000 0 0x48000000 0 0x48000000 0 0x08000000
|
||||
/* MEM64 pref 0x6_0000_0000 - 0x7_0000_0000 */
|
||||
0x43000000 6 0x00000000 6 0x00000000 1 0x00000000>;
|
||||
interrupt-map-mask = <0 0 0 7>;
|
||||
interrupt-map =
|
||||
/* addr pin ic icaddr icintr */
|
||||
<0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
|
||||
0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
msi-parent = <&gicits>;
|
||||
dma-coherent;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
uart0: serial@402020000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x04 0x02020000 0x0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clk125mhz>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
|
@ -1,4 +1,4 @@
|
|||
dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb
|
||||
dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
|
|
|
|||
|
|
@ -30,12 +30,15 @@ CONFIG_MODULES=y
|
|||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
# CONFIG_IOSCHED_DEADLINE is not set
|
||||
CONFIG_ARCH_SUNXI=y
|
||||
CONFIG_ARCH_ALPINE=y
|
||||
CONFIG_ARCH_BCM_IPROC=y
|
||||
CONFIG_ARCH_BERLIN=y
|
||||
CONFIG_ARCH_EXYNOS7=y
|
||||
CONFIG_ARCH_EXYNOS=y
|
||||
CONFIG_ARCH_LAYERSCAPE=y
|
||||
CONFIG_ARCH_HISI=y
|
||||
CONFIG_ARCH_MEDIATEK=y
|
||||
CONFIG_ARCH_MVEBU=y
|
||||
CONFIG_ARCH_QCOM=y
|
||||
CONFIG_ARCH_ROCKCHIP=y
|
||||
CONFIG_ARCH_SEATTLE=y
|
||||
|
|
@ -47,6 +50,7 @@ CONFIG_ARCH_SPRD=y
|
|||
CONFIG_ARCH_THUNDER=y
|
||||
CONFIG_ARCH_UNIPHIER=y
|
||||
CONFIG_ARCH_VEXPRESS=y
|
||||
CONFIG_ARCH_VULCAN=y
|
||||
CONFIG_ARCH_XGENE=y
|
||||
CONFIG_ARCH_ZYNQMP=y
|
||||
CONFIG_PCI=y
|
||||
|
|
@ -95,6 +99,7 @@ CONFIG_ATA=y
|
|||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_SATA_AHCI_PLATFORM=y
|
||||
CONFIG_AHCI_CEVA=y
|
||||
CONFIG_AHCI_MVEBU=y
|
||||
CONFIG_AHCI_XGENE=y
|
||||
CONFIG_SATA_RCAR=y
|
||||
CONFIG_PATA_PLATFORM=y
|
||||
|
|
@ -136,24 +141,40 @@ CONFIG_SERIAL_MSM=y
|
|||
CONFIG_SERIAL_MSM_CONSOLE=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART=y
|
||||
CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
|
||||
CONFIG_SERIAL_MVEBU_UART=y
|
||||
CONFIG_VIRTIO_CONSOLE=y
|
||||
# CONFIG_HW_RANDOM is not set
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_MV64XXX=y
|
||||
CONFIG_I2C_QUP=y
|
||||
CONFIG_I2C_UNIPHIER_F=y
|
||||
CONFIG_I2C_RCAR=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_SPI_PL022=y
|
||||
CONFIG_SPI_QUP=y
|
||||
CONFIG_SPMI=y
|
||||
CONFIG_PINCTRL_MSM8916=y
|
||||
CONFIG_PINCTRL_QCOM_SPMI_PMIC=y
|
||||
CONFIG_GPIO_SYSFS=y
|
||||
CONFIG_GPIO_DWAPB=y
|
||||
CONFIG_GPIO_PL061=y
|
||||
CONFIG_GPIO_RCAR=y
|
||||
CONFIG_GPIO_XGENE=y
|
||||
CONFIG_POWER_RESET_MSM=y
|
||||
CONFIG_POWER_RESET_XGENE=y
|
||||
CONFIG_POWER_RESET_SYSCON=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_THERMAL=y
|
||||
CONFIG_THERMAL_EMULATION=y
|
||||
CONFIG_EXYNOS_THERMAL=y
|
||||
CONFIG_MFD_SPMI_PMIC=y
|
||||
CONFIG_MFD_SEC_CORE=y
|
||||
CONFIG_REGULATOR=y
|
||||
CONFIG_REGULATOR_FIXED_VOLTAGE=y
|
||||
CONFIG_REGULATOR_QCOM_SMD_RPM=y
|
||||
CONFIG_REGULATOR_QCOM_SPMI=y
|
||||
CONFIG_REGULATOR_S2MPS11=y
|
||||
CONFIG_FB=y
|
||||
CONFIG_FB_ARMCLCD=y
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
|
|
@ -166,21 +187,35 @@ CONFIG_SND_SOC=y
|
|||
CONFIG_SND_SOC_RCAR=y
|
||||
CONFIG_SND_SOC_AK4613=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_OTG=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_PLATFORM=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_MSM=y
|
||||
CONFIG_USB_EHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_OHCI_HCD_PLATFORM=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_CHIPIDEA=y
|
||||
CONFIG_USB_CHIPIDEA_UDC=y
|
||||
CONFIG_USB_CHIPIDEA_HOST=y
|
||||
CONFIG_USB_ISP1760=y
|
||||
CONFIG_USB_HSIC_USB3503=y
|
||||
CONFIG_USB_MSM_OTG=y
|
||||
CONFIG_USB_ULPI=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_MMC=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_MMC_ARMMMCI=y
|
||||
CONFIG_MMC_SDHCI=y
|
||||
CONFIG_MMC_SDHCI_PLTFM=y
|
||||
CONFIG_MMC_SDHCI_TEGRA=y
|
||||
CONFIG_MMC_SDHCI_MSM=y
|
||||
CONFIG_MMC_SPI=y
|
||||
CONFIG_MMC_SUNXI=y
|
||||
CONFIG_MMC_DW=y
|
||||
CONFIG_MMC_DW_EXYNOS=y
|
||||
CONFIG_MMC_BLOCK_MINORS=16
|
||||
CONFIG_NEW_LEDS=y
|
||||
CONFIG_LEDS_CLASS=y
|
||||
CONFIG_LEDS_SYSCON=y
|
||||
|
|
@ -188,8 +223,10 @@ CONFIG_LEDS_TRIGGERS=y
|
|||
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_S5M=y
|
||||
CONFIG_RTC_DRV_EFI=y
|
||||
CONFIG_RTC_DRV_PL031=y
|
||||
CONFIG_RTC_DRV_SUN6I=y
|
||||
CONFIG_RTC_DRV_XGENE=y
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_QCOM_BAM_DMA=y
|
||||
|
|
@ -213,6 +250,8 @@ CONFIG_QCOM_SMD_RPM=y
|
|||
CONFIG_ARCH_TEGRA_132_SOC=y
|
||||
CONFIG_ARCH_TEGRA_210_SOC=y
|
||||
CONFIG_HISILICON_IRQ_MBIGEN=y
|
||||
CONFIG_EXTCON_USB_GPIO=y
|
||||
CONFIG_PHY_RCAR_GEN3_USB2=y
|
||||
CONFIG_PHY_XGENE=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
|
|
|
|||
|
|
@ -70,6 +70,7 @@
|
|||
#define ARM_CPU_IMP_ARM 0x41
|
||||
#define ARM_CPU_IMP_APM 0x50
|
||||
#define ARM_CPU_IMP_CAVIUM 0x43
|
||||
#define ARM_CPU_IMP_BRCM 0x42
|
||||
|
||||
#define ARM_CPU_PART_AEM_V8 0xD0F
|
||||
#define ARM_CPU_PART_FOUNDATION 0xD00
|
||||
|
|
@ -80,6 +81,8 @@
|
|||
|
||||
#define CAVIUM_CPU_PART_THUNDERX 0x0A1
|
||||
|
||||
#define BRCM_CPU_PART_VULCAN 0x516
|
||||
|
||||
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
|
||||
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
|
||||
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
|
||||
|
|
|
|||
|
|
@ -202,11 +202,9 @@ config COMMON_CLK_CDCE706
|
|||
|
||||
source "drivers/clk/bcm/Kconfig"
|
||||
source "drivers/clk/hisilicon/Kconfig"
|
||||
source "drivers/clk/qcom/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
source "drivers/clk/mvebu/Kconfig"
|
||||
|
||||
source "drivers/clk/qcom/Kconfig"
|
||||
source "drivers/clk/samsung/Kconfig"
|
||||
source "drivers/clk/tegra/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
|
|
|||
|
|
@ -19,8 +19,6 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
|
||||
|
||||
static u8 clk_composite_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_composite *composite = to_clk_composite(hw);
|
||||
|
|
|
|||
|
|
@ -28,8 +28,6 @@
|
|||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#define div_mask(width) ((1 << (width)) - 1)
|
||||
|
||||
static unsigned int _get_table_maxdiv(const struct clk_div_table *table,
|
||||
|
|
@ -423,6 +421,12 @@ const struct clk_ops clk_divider_ops = {
|
|||
};
|
||||
EXPORT_SYMBOL_GPL(clk_divider_ops);
|
||||
|
||||
const struct clk_ops clk_divider_ro_ops = {
|
||||
.recalc_rate = clk_divider_recalc_rate,
|
||||
.round_rate = clk_divider_round_rate,
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(clk_divider_ro_ops);
|
||||
|
||||
static struct clk *_register_divider(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
void __iomem *reg, u8 shift, u8 width,
|
||||
|
|
@ -446,6 +450,9 @@ static struct clk *_register_divider(struct device *dev, const char *name,
|
|||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
init.name = name;
|
||||
if (clk_divider_flags & CLK_DIVIDER_READ_ONLY)
|
||||
init.ops = &clk_divider_ro_ops;
|
||||
else
|
||||
init.ops = &clk_divider_ops;
|
||||
init.flags = flags | CLK_IS_BASIC;
|
||||
init.parent_names = (parent_name ? &parent_name: NULL);
|
||||
|
|
|
|||
|
|
@ -23,8 +23,6 @@
|
|||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
|
||||
|
||||
static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@
|
|||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
|
||||
|
||||
static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -16,8 +16,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include <linux/rational.h>
|
||||
|
||||
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
|
||||
|
||||
static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@
|
|||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
/*
|
||||
* It works on following logic:
|
||||
*
|
||||
|
|
|
|||
|
|
@ -31,8 +31,6 @@
|
|||
* parent - fixed parent. No clk_set_parent support
|
||||
*/
|
||||
|
||||
#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
|
||||
|
||||
static int clk_gpio_gate_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gpio *clk = to_clk_gpio(hw);
|
||||
|
|
|
|||
|
|
@ -14,8 +14,6 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
|
||||
|
||||
static unsigned long __get_mult(struct clk_multiplier *mult,
|
||||
unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@
|
|||
* parent - parent is adjustable through clk_set_parent
|
||||
*/
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static u8 clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
|
|
|
|||
|
|
@ -28,11 +28,6 @@
|
|||
#include <linux/mfd/samsung/s5m8767.h>
|
||||
#include <linux/mfd/samsung/core.h>
|
||||
|
||||
#define s2mps11_name(a) (a->hw.init->name)
|
||||
|
||||
static struct clk **clk_table;
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
enum {
|
||||
S2MPS11_CLK_AP = 0,
|
||||
S2MPS11_CLK_CP,
|
||||
|
|
@ -99,6 +94,7 @@ static struct clk_ops s2mps11_clk_ops = {
|
|||
.recalc_rate = s2mps11_clk_recalc_rate,
|
||||
};
|
||||
|
||||
/* This s2mps11_clks_init tructure is common to s2mps11, s2mps13 and s2mps14 */
|
||||
static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
|
||||
[S2MPS11_CLK_AP] = {
|
||||
.name = "s2mps11_ap",
|
||||
|
|
@ -117,37 +113,6 @@ static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct clk_init_data s2mps13_clks_init[S2MPS11_CLKS_NUM] = {
|
||||
[S2MPS11_CLK_AP] = {
|
||||
.name = "s2mps13_ap",
|
||||
.ops = &s2mps11_clk_ops,
|
||||
.flags = CLK_IS_ROOT,
|
||||
},
|
||||
[S2MPS11_CLK_CP] = {
|
||||
.name = "s2mps13_cp",
|
||||
.ops = &s2mps11_clk_ops,
|
||||
.flags = CLK_IS_ROOT,
|
||||
},
|
||||
[S2MPS11_CLK_BT] = {
|
||||
.name = "s2mps13_bt",
|
||||
.ops = &s2mps11_clk_ops,
|
||||
.flags = CLK_IS_ROOT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct clk_init_data s2mps14_clks_init[S2MPS11_CLKS_NUM] = {
|
||||
[S2MPS11_CLK_AP] = {
|
||||
.name = "s2mps14_ap",
|
||||
.ops = &s2mps11_clk_ops,
|
||||
.flags = CLK_IS_ROOT,
|
||||
},
|
||||
[S2MPS11_CLK_BT] = {
|
||||
.name = "s2mps14_bt",
|
||||
.ops = &s2mps11_clk_ops,
|
||||
.flags = CLK_IS_ROOT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
|
||||
struct clk_init_data *clks_init)
|
||||
{
|
||||
|
|
@ -164,12 +129,9 @@ static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
|
|||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
|
||||
if (!clks_init[i].name)
|
||||
continue; /* Skip clocks not present in some devices */
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++)
|
||||
of_property_read_string_index(clk_np, "clock-output-names", i,
|
||||
&clks_init[i].name);
|
||||
}
|
||||
|
||||
return clk_np;
|
||||
}
|
||||
|
|
@ -177,39 +139,38 @@ static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev,
|
|||
static int s2mps11_clk_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
|
||||
struct s2mps11_clk *s2mps11_clks, *s2mps11_clk;
|
||||
struct s2mps11_clk *s2mps11_clks;
|
||||
struct clk_onecell_data *clk_data;
|
||||
unsigned int s2mps11_reg;
|
||||
struct clk_init_data *clks_init;
|
||||
int i, ret = 0;
|
||||
enum sec_device_type hwid = platform_get_device_id(pdev)->driver_data;
|
||||
|
||||
s2mps11_clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM,
|
||||
sizeof(*s2mps11_clk), GFP_KERNEL);
|
||||
sizeof(*s2mps11_clks), GFP_KERNEL);
|
||||
if (!s2mps11_clks)
|
||||
return -ENOMEM;
|
||||
|
||||
s2mps11_clk = s2mps11_clks;
|
||||
|
||||
clk_table = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM,
|
||||
sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clk_table)
|
||||
clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return -ENOMEM;
|
||||
|
||||
switch(platform_get_device_id(pdev)->driver_data) {
|
||||
clk_data->clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM,
|
||||
sizeof(struct clk *), GFP_KERNEL);
|
||||
if (!clk_data->clks)
|
||||
return -ENOMEM;
|
||||
|
||||
switch (hwid) {
|
||||
case S2MPS11X:
|
||||
s2mps11_reg = S2MPS11_REG_RTC_CTRL;
|
||||
clks_init = s2mps11_clks_init;
|
||||
break;
|
||||
case S2MPS13X:
|
||||
s2mps11_reg = S2MPS13_REG_RTCCTRL;
|
||||
clks_init = s2mps13_clks_init;
|
||||
break;
|
||||
case S2MPS14X:
|
||||
s2mps11_reg = S2MPS14_REG_RTCCTRL;
|
||||
clks_init = s2mps14_clks_init;
|
||||
break;
|
||||
case S5M8767X:
|
||||
s2mps11_reg = S5M8767_REG_CTRL1;
|
||||
clks_init = s2mps11_clks_init;
|
||||
break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "Invalid device type\n");
|
||||
|
|
@ -217,46 +178,39 @@ static int s2mps11_clk_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* Store clocks of_node in first element of s2mps11_clks array */
|
||||
s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, clks_init);
|
||||
s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, s2mps11_clks_init);
|
||||
if (IS_ERR(s2mps11_clks->clk_np))
|
||||
return PTR_ERR(s2mps11_clks->clk_np);
|
||||
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) {
|
||||
if (!clks_init[i].name)
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
|
||||
if (i == S2MPS11_CLK_CP && hwid == S2MPS14X)
|
||||
continue; /* Skip clocks not present in some devices */
|
||||
s2mps11_clk->iodev = iodev;
|
||||
s2mps11_clk->hw.init = &clks_init[i];
|
||||
s2mps11_clk->mask = 1 << i;
|
||||
s2mps11_clk->reg = s2mps11_reg;
|
||||
s2mps11_clks[i].iodev = iodev;
|
||||
s2mps11_clks[i].hw.init = &s2mps11_clks_init[i];
|
||||
s2mps11_clks[i].mask = 1 << i;
|
||||
s2mps11_clks[i].reg = s2mps11_reg;
|
||||
|
||||
s2mps11_clk->clk = devm_clk_register(&pdev->dev,
|
||||
&s2mps11_clk->hw);
|
||||
if (IS_ERR(s2mps11_clk->clk)) {
|
||||
s2mps11_clks[i].clk = devm_clk_register(&pdev->dev,
|
||||
&s2mps11_clks[i].hw);
|
||||
if (IS_ERR(s2mps11_clks[i].clk)) {
|
||||
dev_err(&pdev->dev, "Fail to register : %s\n",
|
||||
s2mps11_name(s2mps11_clk));
|
||||
ret = PTR_ERR(s2mps11_clk->clk);
|
||||
s2mps11_clks_init[i].name);
|
||||
ret = PTR_ERR(s2mps11_clks[i].clk);
|
||||
goto err_reg;
|
||||
}
|
||||
|
||||
s2mps11_clk->lookup = clkdev_create(s2mps11_clk->clk,
|
||||
s2mps11_name(s2mps11_clk), NULL);
|
||||
if (!s2mps11_clk->lookup) {
|
||||
s2mps11_clks[i].lookup = clkdev_create(s2mps11_clks[i].clk,
|
||||
s2mps11_clks_init[i].name, NULL);
|
||||
if (!s2mps11_clks[i].lookup) {
|
||||
ret = -ENOMEM;
|
||||
goto err_reg;
|
||||
}
|
||||
clk_data->clks[i] = s2mps11_clks[i].clk;
|
||||
}
|
||||
|
||||
for (i = 0; i < S2MPS11_CLKS_NUM; i++) {
|
||||
/* Skip clocks not present on S2MPS14 */
|
||||
if (!clks_init[i].name)
|
||||
continue;
|
||||
clk_table[i] = s2mps11_clks[i].clk;
|
||||
}
|
||||
|
||||
clk_data.clks = clk_table;
|
||||
clk_data.clk_num = S2MPS11_CLKS_NUM;
|
||||
clk_data->clk_num = S2MPS11_CLKS_NUM;
|
||||
of_clk_add_provider(s2mps11_clks->clk_np, of_clk_src_onecell_get,
|
||||
&clk_data);
|
||||
clk_data);
|
||||
|
||||
platform_set_drvdata(pdev, s2mps11_clks);
|
||||
|
||||
|
|
|
|||
|
|
@ -29,7 +29,9 @@
|
|||
#include <linux/of_address.h>
|
||||
|
||||
/* Register SCU_PCPPLL bit fields */
|
||||
#define N_DIV_RD(src) (((src) & 0x000001ff))
|
||||
#define N_DIV_RD(src) ((src) & 0x000001ff)
|
||||
#define SC_N_DIV_RD(src) ((src) & 0x0000007f)
|
||||
#define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8)
|
||||
|
||||
/* Register SCU_SOCPLL bit fields */
|
||||
#define CLKR_RD(src) (((src) & 0x07000000)>>24)
|
||||
|
|
@ -48,7 +50,7 @@ static inline u32 xgene_clk_read(void __iomem *csr)
|
|||
|
||||
static inline void xgene_clk_write(u32 data, void __iomem *csr)
|
||||
{
|
||||
return writel_relaxed(data, csr);
|
||||
writel_relaxed(data, csr);
|
||||
}
|
||||
|
||||
/* PLL Clock */
|
||||
|
|
@ -63,6 +65,7 @@ struct xgene_clk_pll {
|
|||
spinlock_t *lock;
|
||||
u32 pll_offset;
|
||||
enum xgene_pll_type type;
|
||||
int version;
|
||||
};
|
||||
|
||||
#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
|
||||
|
|
@ -92,6 +95,7 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
|
|||
|
||||
pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
|
||||
|
||||
if (pllclk->version <= 1) {
|
||||
if (pllclk->type == PLL_TYPE_PCP) {
|
||||
/*
|
||||
* PLL VCO = Reference clock * NF
|
||||
|
|
@ -111,8 +115,17 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
|
|||
fref = parent_rate / nref;
|
||||
fvco = fref * nfb;
|
||||
}
|
||||
pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw),
|
||||
fvco / nout, parent_rate);
|
||||
} else {
|
||||
/*
|
||||
* fvco = Reference clock * FBDIVC
|
||||
* PLL freq = fvco / NOUT
|
||||
*/
|
||||
nout = SC_OUTDIV2(pll) ? 2 : 3;
|
||||
fvco = parent_rate * SC_N_DIV_RD(pll);
|
||||
}
|
||||
pr_debug("%s pll recalc rate %ld parent %ld version %d\n",
|
||||
clk_hw_get_name(hw), fvco / nout, parent_rate,
|
||||
pllclk->version);
|
||||
|
||||
return fvco / nout;
|
||||
}
|
||||
|
|
@ -125,7 +138,7 @@ static const struct clk_ops xgene_clk_pll_ops = {
|
|||
static struct clk *xgene_register_clk_pll(struct device *dev,
|
||||
const char *name, const char *parent_name,
|
||||
unsigned long flags, void __iomem *reg, u32 pll_offset,
|
||||
u32 type, spinlock_t *lock)
|
||||
u32 type, spinlock_t *lock, int version)
|
||||
{
|
||||
struct xgene_clk_pll *apmclk;
|
||||
struct clk *clk;
|
||||
|
|
@ -144,6 +157,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
|
|||
init.parent_names = parent_name ? &parent_name : NULL;
|
||||
init.num_parents = parent_name ? 1 : 0;
|
||||
|
||||
apmclk->version = version;
|
||||
apmclk->reg = reg;
|
||||
apmclk->lock = lock;
|
||||
apmclk->pll_offset = pll_offset;
|
||||
|
|
@ -160,11 +174,21 @@ static struct clk *xgene_register_clk_pll(struct device *dev,
|
|||
return clk;
|
||||
}
|
||||
|
||||
static int xgene_pllclk_version(struct device_node *np)
|
||||
{
|
||||
if (of_device_is_compatible(np, "apm,xgene-socpll-clock"))
|
||||
return 1;
|
||||
if (of_device_is_compatible(np, "apm,xgene-pcppll-clock"))
|
||||
return 1;
|
||||
return 2;
|
||||
}
|
||||
|
||||
static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
|
||||
{
|
||||
const char *clk_name = np->full_name;
|
||||
struct clk *clk;
|
||||
void __iomem *reg;
|
||||
int version = xgene_pllclk_version(np);
|
||||
|
||||
reg = of_iomap(np, 0);
|
||||
if (reg == NULL) {
|
||||
|
|
@ -174,7 +198,8 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
|
|||
of_property_read_string(np, "clock-output-names", &clk_name);
|
||||
clk = xgene_register_clk_pll(NULL,
|
||||
clk_name, of_clk_get_parent_name(np, 0),
|
||||
CLK_IS_ROOT, reg, 0, pll_type, &clk_lock);
|
||||
CLK_IS_ROOT, reg, 0, pll_type, &clk_lock,
|
||||
version);
|
||||
if (!IS_ERR(clk)) {
|
||||
of_clk_add_provider(np, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
|
|
@ -518,4 +543,8 @@ err:
|
|||
|
||||
CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
|
||||
CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
|
||||
CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
|
||||
xgene_socpllclk_init);
|
||||
CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
|
||||
xgene_pcppllclk_init);
|
||||
CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ struct clk_busy_divider {
|
|||
|
||||
static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_divider *div = container_of(hw, struct clk_divider, hw);
|
||||
struct clk_divider *div = to_clk_divider(hw);
|
||||
|
||||
return container_of(div, struct clk_busy_divider, div);
|
||||
}
|
||||
|
|
@ -123,7 +123,7 @@ struct clk_busy_mux {
|
|||
|
||||
static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = container_of(hw, struct clk_mux, hw);
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
|
||||
return container_of(mux, struct clk_busy_mux, mux);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,7 +15,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
#define div_mask(d) ((1 << (d->width)) - 1)
|
||||
|
||||
/**
|
||||
|
|
@ -35,7 +34,7 @@ struct clk_fixup_div {
|
|||
|
||||
static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_divider *divider = to_clk_div(hw);
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
|
||||
return container_of(divider, struct clk_fixup_div, divider);
|
||||
}
|
||||
|
|
@ -60,7 +59,7 @@ static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
|
|||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
|
||||
struct clk_divider *div = to_clk_div(hw);
|
||||
struct clk_divider *div = to_clk_divider(hw);
|
||||
unsigned int divider, value;
|
||||
unsigned long flags = 0;
|
||||
u32 val;
|
||||
|
|
|
|||
|
|
@ -15,8 +15,6 @@
|
|||
#include <linux/slab.h>
|
||||
#include "clk.h"
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
/**
|
||||
* struct clk_fixup_mux - imx integer fixup multiplexer clock
|
||||
* @mux: the parent class
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@ struct clk_gate_exclusive {
|
|||
|
||||
static int clk_gate_exclusive_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_gate *gate = container_of(hw, struct clk_gate, hw);
|
||||
struct clk_gate *gate = to_clk_gate(hw);
|
||||
struct clk_gate_exclusive *exgate = container_of(gate,
|
||||
struct clk_gate_exclusive, gate);
|
||||
u32 val = readl(gate->reg);
|
||||
|
|
|
|||
|
|
@ -25,7 +25,7 @@
|
|||
|
||||
static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
u32 val;
|
||||
|
||||
regmap_read(cg->regmap, cg->sta_ofs, &val);
|
||||
|
|
@ -37,7 +37,7 @@ static int mtk_cg_bit_is_cleared(struct clk_hw *hw)
|
|||
|
||||
static int mtk_cg_bit_is_set(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
u32 val;
|
||||
|
||||
regmap_read(cg->regmap, cg->sta_ofs, &val);
|
||||
|
|
@ -49,14 +49,14 @@ static int mtk_cg_bit_is_set(struct clk_hw *hw)
|
|||
|
||||
static void mtk_cg_set_bit(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
|
||||
regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit));
|
||||
}
|
||||
|
||||
static void mtk_cg_clr_bit(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_clk_gate *cg = to_clk_gate(hw);
|
||||
struct mtk_clk_gate *cg = to_mtk_clk_gate(hw);
|
||||
|
||||
regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -29,7 +29,7 @@ struct mtk_clk_gate {
|
|||
u8 bit;
|
||||
};
|
||||
|
||||
static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw)
|
||||
static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw)
|
||||
{
|
||||
return container_of(hw, struct mtk_clk_gate, hw);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -209,12 +209,14 @@ struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc,
|
|||
mc->flags);
|
||||
|
||||
if (IS_ERR(clk)) {
|
||||
kfree(gate);
|
||||
kfree(mux);
|
||||
ret = PTR_ERR(clk);
|
||||
goto err_out;
|
||||
}
|
||||
|
||||
return clk;
|
||||
err_out:
|
||||
kfree(div);
|
||||
kfree(gate);
|
||||
kfree(mux);
|
||||
|
||||
return ERR_PTR(ret);
|
||||
|
|
|
|||
|
|
@ -199,8 +199,6 @@ struct clk_gating_ctrl {
|
|||
u32 saved_reg;
|
||||
};
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
static struct clk_gating_ctrl *ctrl;
|
||||
|
||||
static struct clk *clk_gating_get_src(
|
||||
|
|
|
|||
|
|
@ -256,8 +256,6 @@ static const struct clk_muxing_soc_desc kirkwood_mux_desc[] __initconst = {
|
|||
11, 1, 0 },
|
||||
};
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static struct clk *clk_muxing_get_src(
|
||||
struct of_phandle_args *clkspec, void *data)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -33,7 +33,7 @@ struct clk_div {
|
|||
|
||||
static inline struct clk_div *to_clk_div(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_divider *divider = container_of(hw, struct clk_divider, hw);
|
||||
struct clk_divider *divider = to_clk_divider(hw);
|
||||
|
||||
return container_of(divider, struct clk_div, divider);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -28,8 +28,6 @@
|
|||
#define CCU_BRANCH_IS_BUS BIT(0)
|
||||
#define CCU_BRANCH_HAVE_DIV2 BIT(1)
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
struct lpc18xx_branch_clk_data {
|
||||
const char **name;
|
||||
int num;
|
||||
|
|
@ -222,7 +220,7 @@ static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *bran
|
|||
div->width = 1;
|
||||
|
||||
div_hw = &div->hw;
|
||||
div_ops = &clk_divider_ops;
|
||||
div_ops = &clk_divider_ro_ops;
|
||||
}
|
||||
|
||||
branch->gate.reg = branch->offset + reg_base;
|
||||
|
|
|
|||
|
|
@ -90,7 +90,9 @@ static struct clk *rockchip_clk_register_branch(const char *name,
|
|||
div->width = div_width;
|
||||
div->lock = lock;
|
||||
div->table = div_table;
|
||||
div_ops = &clk_divider_ops;
|
||||
div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
|
||||
? &clk_divider_ro_ops
|
||||
: &clk_divider_ops;
|
||||
}
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
|
|
|
|||
|
|
@ -1,9 +1,17 @@
|
|||
# Recent Exynos platforms should just select COMMON_CLK_SAMSUNG:
|
||||
config COMMON_CLK_SAMSUNG
|
||||
bool
|
||||
select COMMON_CLK
|
||||
bool "Samsung Exynos clock controller support" if COMPILE_TEST
|
||||
# Clocks on ARM64 SoCs (e.g. Exynos5433, Exynos7) are chosen by
|
||||
# EXYNOS_ARM64_COMMON_CLK to avoid building them on ARMv7:
|
||||
select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS
|
||||
|
||||
config EXYNOS_ARM64_COMMON_CLK
|
||||
bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST
|
||||
depends on COMMON_CLK_SAMSUNG
|
||||
|
||||
# For S3C24XX platforms, select following symbols:
|
||||
config S3C2410_COMMON_CLK
|
||||
bool
|
||||
bool "Samsung S3C2410 clock controller support" if COMPILE_TEST
|
||||
select COMMON_CLK_SAMSUNG
|
||||
help
|
||||
Build the s3c2410 clock driver based on the common clock framework.
|
||||
|
|
@ -17,10 +25,9 @@ config S3C2410_COMMON_DCLK
|
|||
framework.
|
||||
|
||||
config S3C2412_COMMON_CLK
|
||||
bool
|
||||
bool "Samsung S3C2412 clock controller support" if COMPILE_TEST
|
||||
select COMMON_CLK_SAMSUNG
|
||||
|
||||
config S3C2443_COMMON_CLK
|
||||
bool
|
||||
bool "Samsung S3C2443 clock controller support" if COMPILE_TEST
|
||||
select COMMON_CLK_SAMSUNG
|
||||
|
||||
|
|
|
|||
|
|
@ -10,11 +10,11 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
|
|||
obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos5433.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o
|
||||
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
|
||||
obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o
|
||||
obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o
|
||||
obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o
|
||||
|
|
|
|||
|
|
@ -822,11 +822,10 @@ err:
|
|||
if (!clk_data->clks[i])
|
||||
continue;
|
||||
|
||||
composite = container_of(__clk_get_hw(clk_data->clks[i]),
|
||||
struct clk_composite, hw);
|
||||
kfree(container_of(composite->gate_hw, struct clk_gate, hw));
|
||||
kfree(container_of(composite->rate_hw, struct clk_divider, hw));
|
||||
kfree(container_of(composite->mux_hw, struct clk_mux, hw));
|
||||
composite = to_clk_composite(__clk_get_hw(clk_data->clks[i]));
|
||||
kfree(to_clk_gate(composite->gate_hw));
|
||||
kfree(to_clk_divider(composite->rate_hw));
|
||||
kfree(to_clk_mux(composite->mux_hw));
|
||||
}
|
||||
|
||||
kfree(clk_data->clks);
|
||||
|
|
|
|||
|
|
@ -28,8 +28,6 @@
|
|||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@
|
|||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#define div_mask(d) ((1 << ((d)->width)) - 1)
|
||||
|
||||
static unsigned int _get_table_maxdiv(const struct clk_div_table *table)
|
||||
|
|
|
|||
|
|
@ -24,8 +24,6 @@
|
|||
|
||||
#include "clock.h"
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
|
|
|
|||
|
|
@ -26,8 +26,6 @@
|
|||
#undef pr_fmt
|
||||
#define pr_fmt(fmt) "%s: " fmt, __func__
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
|
|
|
|||
|
|
@ -276,6 +276,8 @@ struct clk_fixed_rate {
|
|||
u8 flags;
|
||||
};
|
||||
|
||||
#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw)
|
||||
|
||||
extern const struct clk_ops clk_fixed_rate_ops;
|
||||
struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
|
|
@ -314,6 +316,8 @@ struct clk_gate {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
|
||||
|
||||
#define CLK_GATE_SET_TO_DISABLE BIT(0)
|
||||
#define CLK_GATE_HIWORD_MASK BIT(1)
|
||||
|
||||
|
|
@ -376,6 +380,8 @@ struct clk_divider {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
|
||||
|
||||
#define CLK_DIVIDER_ONE_BASED BIT(0)
|
||||
#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
|
||||
#define CLK_DIVIDER_ALLOW_ZERO BIT(2)
|
||||
|
|
@ -385,6 +391,7 @@ struct clk_divider {
|
|||
#define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
|
||||
|
||||
extern const struct clk_ops clk_divider_ops;
|
||||
extern const struct clk_ops clk_divider_ro_ops;
|
||||
|
||||
unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
|
||||
unsigned int val, const struct clk_div_table *table,
|
||||
|
|
@ -440,6 +447,8 @@ struct clk_mux {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
|
||||
|
||||
#define CLK_MUX_INDEX_ONE BIT(0)
|
||||
#define CLK_MUX_INDEX_BIT BIT(1)
|
||||
#define CLK_MUX_HIWORD_MASK BIT(2)
|
||||
|
|
@ -483,6 +492,8 @@ struct clk_fixed_factor {
|
|||
unsigned int div;
|
||||
};
|
||||
|
||||
#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
|
||||
|
||||
extern const struct clk_ops clk_fixed_factor_ops;
|
||||
struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
|
|
@ -514,6 +525,8 @@ struct clk_fractional_divider {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw)
|
||||
|
||||
extern const struct clk_ops clk_fractional_divider_ops;
|
||||
struct clk *clk_register_fractional_divider(struct device *dev,
|
||||
const char *name, const char *parent_name, unsigned long flags,
|
||||
|
|
@ -550,6 +563,8 @@ struct clk_multiplier {
|
|||
spinlock_t *lock;
|
||||
};
|
||||
|
||||
#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw)
|
||||
|
||||
#define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
|
||||
#define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
|
||||
|
||||
|
|
@ -579,6 +594,8 @@ struct clk_composite {
|
|||
const struct clk_ops *gate_ops;
|
||||
};
|
||||
|
||||
#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
|
||||
|
||||
struct clk *clk_register_composite(struct device *dev, const char *name,
|
||||
const char * const *parent_names, int num_parents,
|
||||
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
|
||||
|
|
@ -601,6 +618,8 @@ struct clk_gpio {
|
|||
struct gpio_desc *gpiod;
|
||||
};
|
||||
|
||||
#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw)
|
||||
|
||||
extern const struct clk_ops clk_gpio_gate_ops;
|
||||
struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned gpio, bool active_low,
|
||||
|
|
|
|||
Loading…
Reference in New Issue