From c840f28bbf643c361c463bcb8fb815d0b2dad4e8 Mon Sep 17 00:00:00 2001 From: Caesar Wang Date: Fri, 25 Sep 2015 10:14:57 +0800 Subject: [PATCH 01/48] arm64: Enable the timer on Rockchip architecture On the RK3368 SoC, support the APB timers for rockchip platform. Signed-off-by: Caesar Wang Signed-off-by: Heiko Stuebner --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f674bde..8a0952275291 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -60,6 +60,7 @@ config ARCH_ROCKCHIP select ARCH_REQUIRE_GPIOLIB select PINCTRL select PINCTRL_ROCKCHIP + select ROCKCHIP_TIMER help This enables support for the ARMv8 based Rockchip chipsets, like the RK3368. From ce3dd55b99b151a90ac1701c6825f2ae2d49b54e Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 22 Dec 2015 12:27:47 +0000 Subject: [PATCH 02/48] arm64: Introduce Allwinner SoC config option To prepare for supporting the Allwinner A64 SoC, introduce a config option to allow compiling Allwinner (aka. sunxi) specific drivers for ARM64. This patch just defines the ARCH_SUNXI symbol to allow Allwinner specific drivers to be selected during kernel configuration. Signed-off-by: Andre Przywara Acked-by: Arnd Bergmann Signed-off-by: Maxime Ripard --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f674bde..3f9d5ed96cc8 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -1,5 +1,10 @@ menu "Platform selection" +config ARCH_SUNXI + bool "Allwinner sunxi 64-bit SoC Family" + help + This enables support for Allwinner sunxi based SoCs like the A64. + config ARCH_BCM_IPROC bool "Broadcom iProc SoC Family" help From 8904305a473ff342bd03838ed012f5b65829048c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 4 Jan 2016 10:33:24 +0900 Subject: [PATCH 03/48] ARM: exynos_defconfig: Enable NEON, accelerated crypto and cpufreq stats Enable the kernel NEON mode and asm/NEON accelerated crypto algorithms which should bring performance benefits on Exynos SoCs. Enable these as modules because they are optional, not essential anyhow for platform booting nor related directly to Exynos Soc. All accelerated algorithms pass booting self-tests on Odroid XU4 (Exynos5422) and Trats2 (Exynos4412). Additionally enable cpufreq statistics as they are useful for debugging. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Anand Moon Reviewed-by: Javier Martinez Canillas --- arch/arm/configs/exynos_defconfig | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 24dcd2bb1215..0aee1e035be9 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -26,12 +26,14 @@ CONFIG_ARM_APPENDED_DTB=y CONFIG_ARM_ATAG_DTB_COMPAT=y CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M" CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_STAT_DETAILS=y CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y CONFIG_CPUFREQ_DT=y CONFIG_CPU_IDLE=y CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -238,7 +240,11 @@ CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_USER=y -CONFIG_CRYPTO_SHA256=y +CONFIG_ARM_CRYPTO=y +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m CONFIG_CRC_CCITT=y CONFIG_FONTS=y CONFIG_FONT_7x14=y From 2c658a730083fd84729e30a7c5b3c045347c391a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 7 Jan 2016 10:26:36 +0900 Subject: [PATCH 04/48] ARM: exynos_defconfig: Enable s5p-secss driver The Exynos SoC provides a Security SubSystem block for accelerating some cryptographic operations. Enable the driver for it - s5p-secss to utilize the hardware acceleration. Currently the s5p-secss driver supports AES in CBC and ECB modes. However on Odroid XU4 (Exynos5422) and Trats2 (Exynos4412) boards this change introduces one booting error (because of unaligned buffers): alg: skcipher: encryption failed on chunk test 1 for ecb-aes-s5p: ret=22 The cbc-aes-s5p properly registers itself and passes self-tests. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Anand Moon Reviewed-by: Javier Martinez Canillas --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 0aee1e035be9..c47c7e069873 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -240,6 +240,7 @@ CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y CONFIG_DEBUG_MUTEXES=y CONFIG_DEBUG_USER=y +CONFIG_CRYPTO_DEV_S5P=y CONFIG_ARM_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM_NEON=m CONFIG_CRYPTO_SHA256_ARM=m From 50359819794b4a16ae35051cd80f2dab025f6019 Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Thu, 21 Jan 2016 21:53:09 +0100 Subject: [PATCH 05/48] clk-divider: make sure read-only dividers do not write to their register Commit e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90be9 ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing Signed-off-by: Heiko Stuebner Signed-off-by: Stephen Boyd --- drivers/clk/clk-divider.c | 11 ++++++++++- drivers/clk/nxp/clk-lpc18xx-ccu.c | 2 +- drivers/clk/rockchip/clk.c | 4 +++- include/linux/clk-provider.h | 1 + 4 files changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index ded3ff4b91b9..aa1dacdaa39d 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -423,6 +423,12 @@ const struct clk_ops clk_divider_ops = { }; EXPORT_SYMBOL_GPL(clk_divider_ops); +const struct clk_ops clk_divider_ro_ops = { + .recalc_rate = clk_divider_recalc_rate, + .round_rate = clk_divider_round_rate, +}; +EXPORT_SYMBOL_GPL(clk_divider_ro_ops); + static struct clk *_register_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u8 shift, u8 width, @@ -446,7 +452,10 @@ static struct clk *_register_divider(struct device *dev, const char *name, return ERR_PTR(-ENOMEM); init.name = name; - init.ops = &clk_divider_ops; + if (clk_divider_flags & CLK_DIVIDER_READ_ONLY) + init.ops = &clk_divider_ro_ops; + else + init.ops = &clk_divider_ops; init.flags = flags | CLK_IS_BASIC; init.parent_names = (parent_name ? &parent_name: NULL); init.num_parents = (parent_name ? 1 : 0); diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c index 13aabbb3acbe..558da89555af 100644 --- a/drivers/clk/nxp/clk-lpc18xx-ccu.c +++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c @@ -222,7 +222,7 @@ static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *bran div->width = 1; div_hw = &div->hw; - div_ops = &clk_divider_ops; + div_ops = &clk_divider_ro_ops; } branch->gate.reg = branch->offset + reg_base; diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c index d9a0b5d4d47f..f7e8693ad28b 100644 --- a/drivers/clk/rockchip/clk.c +++ b/drivers/clk/rockchip/clk.c @@ -90,7 +90,9 @@ static struct clk *rockchip_clk_register_branch(const char *name, div->width = div_width; div->lock = lock; div->table = div_table; - div_ops = &clk_divider_ops; + div_ops = (div_flags & CLK_DIVIDER_READ_ONLY) + ? &clk_divider_ro_ops + : &clk_divider_ops; } clk = clk_register_composite(NULL, name, parent_names, num_parents, diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1143e38555a4..408a60dca353 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -385,6 +385,7 @@ struct clk_divider { #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) extern const struct clk_ops clk_divider_ops; +extern const struct clk_ops clk_divider_ro_ops; unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate, unsigned int val, const struct clk_div_table *table, From 26adc5fa276f7cfafda47d27849e6c1c3bff5aba Mon Sep 17 00:00:00 2001 From: Andi Shyti Date: Wed, 20 Jan 2016 19:14:21 +0900 Subject: [PATCH 06/48] clk: s2mps11: merge two for loops in one The driver already loops once, there is no reason to loop again for a different purpose. Merge the second loop into the first. Signed-off-by: Andi Shyti Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- drivers/clk/clk-s2mps11.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index d266299dfdb1..e7b97f4f53d3 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -244,12 +244,6 @@ static int s2mps11_clk_probe(struct platform_device *pdev) ret = -ENOMEM; goto err_reg; } - } - - for (i = 0; i < S2MPS11_CLKS_NUM; i++) { - /* Skip clocks not present on S2MPS14 */ - if (!clks_init[i].name) - continue; clk_table[i] = s2mps11_clks[i].clk; } From 31ad0e2a9ab0667b40a654e5ba412987587229ea Mon Sep 17 00:00:00 2001 From: Andi Shyti Date: Wed, 20 Jan 2016 19:14:22 +0900 Subject: [PATCH 07/48] clk: s2mps11: allocate only one structure for clock init The driver allocates three structures, s2mpsxx_clk_init, for three different clock types (s2mps11, s2mps13 and s2mps14). They are quite similar but they differ only by the name. Only one of these structures is used, while the others lie unused in the memory. The clock's name, though, is not such a meaningful information and by assigning the same name to the initial data we can avoid over allocation. The common name chosen will be s2mps11, coherently with the device driver name, instead of the clock device. Therefore, remove the structures associated to s2mps13 and s2mps14 and use only the one referred to s2mps11 for all kind of clocks. Signed-off-by: Andi Shyti Suggested-by: Krzysztof Kozlowski Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- drivers/clk/clk-s2mps11.c | 51 ++++++--------------------------------- 1 file changed, 7 insertions(+), 44 deletions(-) diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index e7b97f4f53d3..3ff2162b36ff 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -99,6 +99,7 @@ static struct clk_ops s2mps11_clk_ops = { .recalc_rate = s2mps11_clk_recalc_rate, }; +/* This s2mps11_clks_init tructure is common to s2mps11, s2mps13 and s2mps14 */ static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = { [S2MPS11_CLK_AP] = { .name = "s2mps11_ap", @@ -117,37 +118,6 @@ static struct clk_init_data s2mps11_clks_init[S2MPS11_CLKS_NUM] = { }, }; -static struct clk_init_data s2mps13_clks_init[S2MPS11_CLKS_NUM] = { - [S2MPS11_CLK_AP] = { - .name = "s2mps13_ap", - .ops = &s2mps11_clk_ops, - .flags = CLK_IS_ROOT, - }, - [S2MPS11_CLK_CP] = { - .name = "s2mps13_cp", - .ops = &s2mps11_clk_ops, - .flags = CLK_IS_ROOT, - }, - [S2MPS11_CLK_BT] = { - .name = "s2mps13_bt", - .ops = &s2mps11_clk_ops, - .flags = CLK_IS_ROOT, - }, -}; - -static struct clk_init_data s2mps14_clks_init[S2MPS11_CLKS_NUM] = { - [S2MPS11_CLK_AP] = { - .name = "s2mps14_ap", - .ops = &s2mps11_clk_ops, - .flags = CLK_IS_ROOT, - }, - [S2MPS11_CLK_BT] = { - .name = "s2mps14_bt", - .ops = &s2mps11_clk_ops, - .flags = CLK_IS_ROOT, - }, -}; - static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev, struct clk_init_data *clks_init) { @@ -164,12 +134,9 @@ static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev, return ERR_PTR(-EINVAL); } - for (i = 0; i < S2MPS11_CLKS_NUM; i++) { - if (!clks_init[i].name) - continue; /* Skip clocks not present in some devices */ + for (i = 0; i < S2MPS11_CLKS_NUM; i++) of_property_read_string_index(clk_np, "clock-output-names", i, &clks_init[i].name); - } return clk_np; } @@ -179,8 +146,8 @@ static int s2mps11_clk_probe(struct platform_device *pdev) struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct s2mps11_clk *s2mps11_clks, *s2mps11_clk; unsigned int s2mps11_reg; - struct clk_init_data *clks_init; int i, ret = 0; + enum sec_device_type hwid = platform_get_device_id(pdev)->driver_data; s2mps11_clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM, sizeof(*s2mps11_clk), GFP_KERNEL); @@ -194,22 +161,18 @@ static int s2mps11_clk_probe(struct platform_device *pdev) if (!clk_table) return -ENOMEM; - switch(platform_get_device_id(pdev)->driver_data) { + switch (hwid) { case S2MPS11X: s2mps11_reg = S2MPS11_REG_RTC_CTRL; - clks_init = s2mps11_clks_init; break; case S2MPS13X: s2mps11_reg = S2MPS13_REG_RTCCTRL; - clks_init = s2mps13_clks_init; break; case S2MPS14X: s2mps11_reg = S2MPS14_REG_RTCCTRL; - clks_init = s2mps14_clks_init; break; case S5M8767X: s2mps11_reg = S5M8767_REG_CTRL1; - clks_init = s2mps11_clks_init; break; default: dev_err(&pdev->dev, "Invalid device type\n"); @@ -217,15 +180,15 @@ static int s2mps11_clk_probe(struct platform_device *pdev) } /* Store clocks of_node in first element of s2mps11_clks array */ - s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, clks_init); + s2mps11_clks->clk_np = s2mps11_clk_parse_dt(pdev, s2mps11_clks_init); if (IS_ERR(s2mps11_clks->clk_np)) return PTR_ERR(s2mps11_clks->clk_np); for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) { - if (!clks_init[i].name) + if (i == S2MPS11_CLK_CP && hwid == S2MPS14X) continue; /* Skip clocks not present in some devices */ s2mps11_clk->iodev = iodev; - s2mps11_clk->hw.init = &clks_init[i]; + s2mps11_clk->hw.init = &s2mps11_clks_init[i]; s2mps11_clk->mask = 1 << i; s2mps11_clk->reg = s2mps11_reg; From 36da4def1ea7a5f698d3096d10316f911e819621 Mon Sep 17 00:00:00 2001 From: Andi Shyti Date: Wed, 20 Jan 2016 19:14:23 +0900 Subject: [PATCH 08/48] clk: s2mps11: remove redundant static variables declaration The clk_table and clk_data are declared static. The clk_table contains the three clock data structures belonging to the s2mps11 driver. In the probe function it gets stored into clk_data. Remove clk_table and refer directly to clk_data. clk_data, itself, is also declared static. Declare locally it and allocate it inside the probe function, as it is not used anywhere else. Signed-off-by: Andi Shyti Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- drivers/clk/clk-s2mps11.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index 3ff2162b36ff..fac0e2029adc 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -30,9 +30,6 @@ #define s2mps11_name(a) (a->hw.init->name) -static struct clk **clk_table; -static struct clk_onecell_data clk_data; - enum { S2MPS11_CLK_AP = 0, S2MPS11_CLK_CP, @@ -145,6 +142,7 @@ static int s2mps11_clk_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); struct s2mps11_clk *s2mps11_clks, *s2mps11_clk; + struct clk_onecell_data *clk_data; unsigned int s2mps11_reg; int i, ret = 0; enum sec_device_type hwid = platform_get_device_id(pdev)->driver_data; @@ -156,9 +154,13 @@ static int s2mps11_clk_probe(struct platform_device *pdev) s2mps11_clk = s2mps11_clks; - clk_table = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM, + clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM, sizeof(struct clk *), GFP_KERNEL); - if (!clk_table) + if (!clk_data->clks) return -ENOMEM; switch (hwid) { @@ -207,13 +209,12 @@ static int s2mps11_clk_probe(struct platform_device *pdev) ret = -ENOMEM; goto err_reg; } - clk_table[i] = s2mps11_clks[i].clk; + clk_data->clks[i] = s2mps11_clks[i].clk; } - clk_data.clks = clk_table; - clk_data.clk_num = S2MPS11_CLKS_NUM; + clk_data->clk_num = S2MPS11_CLKS_NUM; of_clk_add_provider(s2mps11_clks->clk_np, of_clk_src_onecell_get, - &clk_data); + clk_data); platform_set_drvdata(pdev, s2mps11_clks); From dedbb2724dca5de4073c261c52fa76bf348f6a0d Mon Sep 17 00:00:00 2001 From: Andi Shyti Date: Wed, 20 Jan 2016 19:14:24 +0900 Subject: [PATCH 09/48] clk: s2mps11: remove redundant code The definition of s2mps11_name is meant to resolve the name of a given clock. Remove it because the clocks have the same name we can get it directly from the s2mps11_clks_init structure. While in the probe function the s2mps11_clks is used only to iterate through the s2mps11_clks. The naming itself brings confusion and the readability does not improve much. Signed-off-by: Andi Shyti Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd --- drivers/clk/clk-s2mps11.c | 34 +++++++++++++++------------------- 1 file changed, 15 insertions(+), 19 deletions(-) diff --git a/drivers/clk/clk-s2mps11.c b/drivers/clk/clk-s2mps11.c index fac0e2029adc..371150aabd15 100644 --- a/drivers/clk/clk-s2mps11.c +++ b/drivers/clk/clk-s2mps11.c @@ -28,8 +28,6 @@ #include #include -#define s2mps11_name(a) (a->hw.init->name) - enum { S2MPS11_CLK_AP = 0, S2MPS11_CLK_CP, @@ -141,19 +139,17 @@ static struct device_node *s2mps11_clk_parse_dt(struct platform_device *pdev, static int s2mps11_clk_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent); - struct s2mps11_clk *s2mps11_clks, *s2mps11_clk; + struct s2mps11_clk *s2mps11_clks; struct clk_onecell_data *clk_data; unsigned int s2mps11_reg; int i, ret = 0; enum sec_device_type hwid = platform_get_device_id(pdev)->driver_data; s2mps11_clks = devm_kcalloc(&pdev->dev, S2MPS11_CLKS_NUM, - sizeof(*s2mps11_clk), GFP_KERNEL); + sizeof(*s2mps11_clks), GFP_KERNEL); if (!s2mps11_clks) return -ENOMEM; - s2mps11_clk = s2mps11_clks; - clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data), GFP_KERNEL); if (!clk_data) return -ENOMEM; @@ -186,26 +182,26 @@ static int s2mps11_clk_probe(struct platform_device *pdev) if (IS_ERR(s2mps11_clks->clk_np)) return PTR_ERR(s2mps11_clks->clk_np); - for (i = 0; i < S2MPS11_CLKS_NUM; i++, s2mps11_clk++) { + for (i = 0; i < S2MPS11_CLKS_NUM; i++) { if (i == S2MPS11_CLK_CP && hwid == S2MPS14X) continue; /* Skip clocks not present in some devices */ - s2mps11_clk->iodev = iodev; - s2mps11_clk->hw.init = &s2mps11_clks_init[i]; - s2mps11_clk->mask = 1 << i; - s2mps11_clk->reg = s2mps11_reg; + s2mps11_clks[i].iodev = iodev; + s2mps11_clks[i].hw.init = &s2mps11_clks_init[i]; + s2mps11_clks[i].mask = 1 << i; + s2mps11_clks[i].reg = s2mps11_reg; - s2mps11_clk->clk = devm_clk_register(&pdev->dev, - &s2mps11_clk->hw); - if (IS_ERR(s2mps11_clk->clk)) { + s2mps11_clks[i].clk = devm_clk_register(&pdev->dev, + &s2mps11_clks[i].hw); + if (IS_ERR(s2mps11_clks[i].clk)) { dev_err(&pdev->dev, "Fail to register : %s\n", - s2mps11_name(s2mps11_clk)); - ret = PTR_ERR(s2mps11_clk->clk); + s2mps11_clks_init[i].name); + ret = PTR_ERR(s2mps11_clks[i].clk); goto err_reg; } - s2mps11_clk->lookup = clkdev_create(s2mps11_clk->clk, - s2mps11_name(s2mps11_clk), NULL); - if (!s2mps11_clk->lookup) { + s2mps11_clks[i].lookup = clkdev_create(s2mps11_clks[i].clk, + s2mps11_clks_init[i].name, NULL); + if (!s2mps11_clks[i].lookup) { ret = -ENOMEM; goto err_reg; } From 7b63c567b5b3b3e366e6555d764318a75073f2c7 Mon Sep 17 00:00:00 2001 From: Loc Ho Date: Tue, 19 Jan 2016 19:27:41 -0700 Subject: [PATCH 10/48] Documentation: Update APM X-Gene clock binding for v2 hardware Update APM X-Gene clock binding documentation for SoC and PCP PLL for v2 hardware. Signed-off-by: Loc Ho Signed-off-by: Stephen Boyd --- Documentation/devicetree/bindings/clock/xgene.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/xgene.txt b/Documentation/devicetree/bindings/clock/xgene.txt index 1c4ef773feea..82f9638121db 100644 --- a/Documentation/devicetree/bindings/clock/xgene.txt +++ b/Documentation/devicetree/bindings/clock/xgene.txt @@ -9,6 +9,8 @@ Required properties: "apm,xgene-socpll-clock" - for a X-Gene SoC PLL clock "apm,xgene-pcppll-clock" - for a X-Gene PCP PLL clock "apm,xgene-device-clock" - for a X-Gene device clock + "apm,xgene-socpll-v2-clock" - for a X-Gene SoC PLL v2 clock + "apm,xgene-pcppll-v2-clock" - for a X-Gene PCP PLL v2 clock Required properties for SoC or PCP PLL clocks: - reg : shall be the physical PLL register address for the pll clock. From 47727beb26569725f6c200cde2c38bd1e9f6f1b0 Mon Sep 17 00:00:00 2001 From: Loc Ho Date: Tue, 19 Jan 2016 19:27:42 -0700 Subject: [PATCH 11/48] clk: xgene: Add SoC and PMD PLL clocks with v2 hardware Add X-Gene SoC and PMD PLL clocks support for v2 hardware. X-Gene SoC v2 and above use an slightly different SoC and PMD PLL hardware logic. Signed-off-by: Loc Ho Signed-off-by: Stephen Boyd --- drivers/clk/clk-xgene.c | 103 +++++++++++++++++++++++++--------------- 1 file changed, 66 insertions(+), 37 deletions(-) diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index 10224b01b97c..266d573b9134 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -29,7 +29,9 @@ #include /* Register SCU_PCPPLL bit fields */ -#define N_DIV_RD(src) (((src) & 0x000001ff)) +#define N_DIV_RD(src) ((src) & 0x000001ff) +#define SC_N_DIV_RD(src) ((src) & 0x0000007f) +#define SC_OUTDIV2(src) (((src) & 0x00000100) >> 8) /* Register SCU_SOCPLL bit fields */ #define CLKR_RD(src) (((src) & 0x07000000)>>24) @@ -63,6 +65,7 @@ struct xgene_clk_pll { spinlock_t *lock; u32 pll_offset; enum xgene_pll_type type; + int version; }; #define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw) @@ -92,27 +95,37 @@ static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw, pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); - if (pllclk->type == PLL_TYPE_PCP) { - /* - * PLL VCO = Reference clock * NF - * PCP PLL = PLL_VCO / 2 - */ - nout = 2; - fvco = parent_rate * (N_DIV_RD(pll) + 4); + if (pllclk->version <= 1) { + if (pllclk->type == PLL_TYPE_PCP) { + /* + * PLL VCO = Reference clock * NF + * PCP PLL = PLL_VCO / 2 + */ + nout = 2; + fvco = parent_rate * (N_DIV_RD(pll) + 4); + } else { + /* + * Fref = Reference Clock / NREF; + * Fvco = Fref * NFB; + * Fout = Fvco / NOUT; + */ + nref = CLKR_RD(pll) + 1; + nout = CLKOD_RD(pll) + 1; + nfb = CLKF_RD(pll); + fref = parent_rate / nref; + fvco = fref * nfb; + } } else { /* - * Fref = Reference Clock / NREF; - * Fvco = Fref * NFB; - * Fout = Fvco / NOUT; + * fvco = Reference clock * FBDIVC + * PLL freq = fvco / NOUT */ - nref = CLKR_RD(pll) + 1; - nout = CLKOD_RD(pll) + 1; - nfb = CLKF_RD(pll); - fref = parent_rate / nref; - fvco = fref * nfb; + nout = SC_OUTDIV2(pll) ? 2 : 3; + fvco = parent_rate * SC_N_DIV_RD(pll); } - pr_debug("%s pll recalc rate %ld parent %ld\n", clk_hw_get_name(hw), - fvco / nout, parent_rate); + pr_debug("%s pll recalc rate %ld parent %ld version %d\n", + clk_hw_get_name(hw), fvco / nout, parent_rate, + pllclk->version); return fvco / nout; } @@ -125,7 +138,7 @@ static const struct clk_ops xgene_clk_pll_ops = { static struct clk *xgene_register_clk_pll(struct device *dev, const char *name, const char *parent_name, unsigned long flags, void __iomem *reg, u32 pll_offset, - u32 type, spinlock_t *lock) + u32 type, spinlock_t *lock, int version) { struct xgene_clk_pll *apmclk; struct clk *clk; @@ -144,6 +157,7 @@ static struct clk *xgene_register_clk_pll(struct device *dev, init.parent_names = parent_name ? &parent_name : NULL; init.num_parents = parent_name ? 1 : 0; + apmclk->version = version; apmclk->reg = reg; apmclk->lock = lock; apmclk->pll_offset = pll_offset; @@ -160,26 +174,37 @@ static struct clk *xgene_register_clk_pll(struct device *dev, return clk; } +static int xgene_pllclk_version(struct device_node *np) +{ + if (of_device_is_compatible(np, "apm,xgene-socpll-clock")) + return 1; + if (of_device_is_compatible(np, "apm,xgene-pcppll-clock")) + return 1; + return 2; +} + static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type) { - const char *clk_name = np->full_name; - struct clk *clk; - void __iomem *reg; + const char *clk_name = np->full_name; + struct clk *clk; + void __iomem *reg; + int version = xgene_pllclk_version(np); - reg = of_iomap(np, 0); - if (reg == NULL) { - pr_err("Unable to map CSR register for %s\n", np->full_name); - return; - } - of_property_read_string(np, "clock-output-names", &clk_name); - clk = xgene_register_clk_pll(NULL, - clk_name, of_clk_get_parent_name(np, 0), - CLK_IS_ROOT, reg, 0, pll_type, &clk_lock); - if (!IS_ERR(clk)) { - of_clk_add_provider(np, of_clk_src_simple_get, clk); - clk_register_clkdev(clk, clk_name, NULL); - pr_debug("Add %s clock PLL\n", clk_name); - } + reg = of_iomap(np, 0); + if (reg == NULL) { + pr_err("Unable to map CSR register for %s\n", np->full_name); + return; + } + of_property_read_string(np, "clock-output-names", &clk_name); + clk = xgene_register_clk_pll(NULL, + clk_name, of_clk_get_parent_name(np, 0), + CLK_IS_ROOT, reg, 0, pll_type, &clk_lock, + version); + if (!IS_ERR(clk)) { + of_clk_add_provider(np, of_clk_src_simple_get, clk); + clk_register_clkdev(clk, clk_name, NULL); + pr_debug("Add %s clock PLL\n", clk_name); + } } static void xgene_socpllclk_init(struct device_node *np) @@ -460,7 +485,7 @@ static void __init xgene_devclk_init(struct device_node *np) rc = of_address_to_resource(np, i, &res); if (rc != 0) { if (i == 0) { - pr_err("no DTS register for %s\n", + pr_err("no DTS register for %s\n", np->full_name); return; } @@ -518,4 +543,8 @@ err: CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init); CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init); +CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock", + xgene_socpllclk_init); +CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock", + xgene_pcppllclk_init); CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init); From f9285b54d657f433746df9232068c32ef138ebc4 Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Fri, 29 Jan 2016 12:57:15 -0800 Subject: [PATCH 12/48] clk: xgene: Remove return from void function This function doesn't return anything because it's void. Drop the return statement. Cc: Loc Ho Signed-off-by: Stephen Boyd --- drivers/clk/clk-xgene.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c index 266d573b9134..bd7156baa08b 100644 --- a/drivers/clk/clk-xgene.c +++ b/drivers/clk/clk-xgene.c @@ -50,7 +50,7 @@ static inline u32 xgene_clk_read(void __iomem *csr) static inline void xgene_clk_write(u32 data, void __iomem *csr) { - return writel_relaxed(data, csr); + writel_relaxed(data, csr); } /* PLL Clock */ From 5fd9c05c846db98319e75496612da24435cee208 Mon Sep 17 00:00:00 2001 From: Geliang Tang Date: Fri, 8 Jan 2016 23:51:46 +0800 Subject: [PATCH 13/48] clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h to_clk_*(_hw) macros have been repeatedly defined in many places. This patch moves all the to_clk_*(_hw) definitions in the common clock framework to public header clk-provider.h, and drop the local definitions. Signed-off-by: Geliang Tang Signed-off-by: Stephen Boyd --- drivers/clk/clk-composite.c | 2 -- drivers/clk/clk-divider.c | 2 -- drivers/clk/clk-fixed-factor.c | 2 -- drivers/clk/clk-fixed-rate.c | 2 -- drivers/clk/clk-fractional-divider.c | 2 -- drivers/clk/clk-gate.c | 2 -- drivers/clk/clk-gpio.c | 2 -- drivers/clk/clk-multiplier.c | 2 -- drivers/clk/clk-mux.c | 2 -- drivers/clk/imx/clk-busy.c | 4 ++-- drivers/clk/imx/clk-fixup-div.c | 5 ++--- drivers/clk/imx/clk-fixup-mux.c | 2 -- drivers/clk/imx/clk-gate-exclusive.c | 2 +- drivers/clk/mediatek/clk-gate.c | 8 ++++---- drivers/clk/mediatek/clk-gate.h | 2 +- drivers/clk/mvebu/common.c | 2 -- drivers/clk/mvebu/kirkwood.c | 2 -- drivers/clk/mxs/clk-div.c | 2 +- drivers/clk/nxp/clk-lpc18xx-ccu.c | 2 -- drivers/clk/st/clkgen-mux.c | 9 ++++----- drivers/clk/ti/composite.c | 2 -- drivers/clk/ti/divider.c | 2 -- drivers/clk/ti/gate.c | 2 -- drivers/clk/ti/mux.c | 2 -- include/linux/clk-provider.h | 18 ++++++++++++++++++ 25 files changed, 33 insertions(+), 51 deletions(-) diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c index 4735de0660cc..1f903e1f86a2 100644 --- a/drivers/clk/clk-composite.c +++ b/drivers/clk/clk-composite.c @@ -19,8 +19,6 @@ #include #include -#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) - static u8 clk_composite_get_parent(struct clk_hw *hw) { struct clk_composite *composite = to_clk_composite(hw); diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index aa1dacdaa39d..7d62dc30e969 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -28,8 +28,6 @@ * parent - fixed parent. No clk_set_parent support */ -#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) - #define div_mask(width) ((1 << (width)) - 1) static unsigned int _get_table_maxdiv(const struct clk_div_table *table, diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index 83de57aeceea..f0ddf37d5e15 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -23,8 +23,6 @@ * parent - fixed parent. No clk_set_parent support */ -#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) - static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c index f85ec8d1711f..e156beb871f0 100644 --- a/drivers/clk/clk-fixed-rate.c +++ b/drivers/clk/clk-fixed-rate.c @@ -26,8 +26,6 @@ * parent - fixed parent. No clk_set_parent support */ -#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) - static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c index 5c4955e33f7a..1abcd76b4993 100644 --- a/drivers/clk/clk-fractional-divider.c +++ b/drivers/clk/clk-fractional-divider.c @@ -16,8 +16,6 @@ #include #include -#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) - static unsigned long clk_fd_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index de0b322f5f58..d0d8ec8e1f1b 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -26,8 +26,6 @@ * parent - fixed parent. No clk_set_parent support */ -#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) - /* * It works on following logic: * diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c index 19fed65587e8..cbbea2985cc9 100644 --- a/drivers/clk/clk-gpio.c +++ b/drivers/clk/clk-gpio.c @@ -31,8 +31,6 @@ * parent - fixed parent. No clk_set_parent support */ -#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) - static int clk_gpio_gate_enable(struct clk_hw *hw) { struct clk_gpio *clk = to_clk_gpio(hw); diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c index fe7806506bf3..9e449c7b751c 100644 --- a/drivers/clk/clk-multiplier.c +++ b/drivers/clk/clk-multiplier.c @@ -14,8 +14,6 @@ #include #include -#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) - static unsigned long __get_mult(struct clk_multiplier *mult, unsigned long rate, unsigned long parent_rate) diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 5ed03c8a8df9..252188fd8bcd 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -26,8 +26,6 @@ * parent - parent is adjustable through clk_set_parent */ -#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) - static u8 clk_mux_get_parent(struct clk_hw *hw) { struct clk_mux *mux = to_clk_mux(hw); diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c index 4bb1bc419b79..5cc99590f9a3 100644 --- a/drivers/clk/imx/clk-busy.c +++ b/drivers/clk/imx/clk-busy.c @@ -38,7 +38,7 @@ struct clk_busy_divider { static inline struct clk_busy_divider *to_clk_busy_divider(struct clk_hw *hw) { - struct clk_divider *div = container_of(hw, struct clk_divider, hw); + struct clk_divider *div = to_clk_divider(hw); return container_of(div, struct clk_busy_divider, div); } @@ -123,7 +123,7 @@ struct clk_busy_mux { static inline struct clk_busy_mux *to_clk_busy_mux(struct clk_hw *hw) { - struct clk_mux *mux = container_of(hw, struct clk_mux, hw); + struct clk_mux *mux = to_clk_mux(hw); return container_of(mux, struct clk_busy_mux, mux); } diff --git a/drivers/clk/imx/clk-fixup-div.c b/drivers/clk/imx/clk-fixup-div.c index 21db020b1f2d..ce5722732715 100644 --- a/drivers/clk/imx/clk-fixup-div.c +++ b/drivers/clk/imx/clk-fixup-div.c @@ -15,7 +15,6 @@ #include #include "clk.h" -#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw) #define div_mask(d) ((1 << (d->width)) - 1) /** @@ -35,7 +34,7 @@ struct clk_fixup_div { static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw) { - struct clk_divider *divider = to_clk_div(hw); + struct clk_divider *divider = to_clk_divider(hw); return container_of(divider, struct clk_fixup_div, divider); } @@ -60,7 +59,7 @@ static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw); - struct clk_divider *div = to_clk_div(hw); + struct clk_divider *div = to_clk_divider(hw); unsigned int divider, value; unsigned long flags = 0; u32 val; diff --git a/drivers/clk/imx/clk-fixup-mux.c b/drivers/clk/imx/clk-fixup-mux.c index 0d40b35c557c..c9b327e0a8dd 100644 --- a/drivers/clk/imx/clk-fixup-mux.c +++ b/drivers/clk/imx/clk-fixup-mux.c @@ -15,8 +15,6 @@ #include #include "clk.h" -#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) - /** * struct clk_fixup_mux - imx integer fixup multiplexer clock * @mux: the parent class diff --git a/drivers/clk/imx/clk-gate-exclusive.c b/drivers/clk/imx/clk-gate-exclusive.c index c12f5f2e04dc..3bd9dee618b2 100644 --- a/drivers/clk/imx/clk-gate-exclusive.c +++ b/drivers/clk/imx/clk-gate-exclusive.c @@ -31,7 +31,7 @@ struct clk_gate_exclusive { static int clk_gate_exclusive_enable(struct clk_hw *hw) { - struct clk_gate *gate = container_of(hw, struct clk_gate, hw); + struct clk_gate *gate = to_clk_gate(hw); struct clk_gate_exclusive *exgate = container_of(gate, struct clk_gate_exclusive, gate); u32 val = readl(gate->reg); diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c index 576bdb7c98b8..2a76901bf04b 100644 --- a/drivers/clk/mediatek/clk-gate.c +++ b/drivers/clk/mediatek/clk-gate.c @@ -25,7 +25,7 @@ static int mtk_cg_bit_is_cleared(struct clk_hw *hw) { - struct mtk_clk_gate *cg = to_clk_gate(hw); + struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); u32 val; regmap_read(cg->regmap, cg->sta_ofs, &val); @@ -37,7 +37,7 @@ static int mtk_cg_bit_is_cleared(struct clk_hw *hw) static int mtk_cg_bit_is_set(struct clk_hw *hw) { - struct mtk_clk_gate *cg = to_clk_gate(hw); + struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); u32 val; regmap_read(cg->regmap, cg->sta_ofs, &val); @@ -49,14 +49,14 @@ static int mtk_cg_bit_is_set(struct clk_hw *hw) static void mtk_cg_set_bit(struct clk_hw *hw) { - struct mtk_clk_gate *cg = to_clk_gate(hw); + struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); regmap_write(cg->regmap, cg->set_ofs, BIT(cg->bit)); } static void mtk_cg_clr_bit(struct clk_hw *hw) { - struct mtk_clk_gate *cg = to_clk_gate(hw); + struct mtk_clk_gate *cg = to_mtk_clk_gate(hw); regmap_write(cg->regmap, cg->clr_ofs, BIT(cg->bit)); } diff --git a/drivers/clk/mediatek/clk-gate.h b/drivers/clk/mediatek/clk-gate.h index 11e25c992948..b1821603b887 100644 --- a/drivers/clk/mediatek/clk-gate.h +++ b/drivers/clk/mediatek/clk-gate.h @@ -29,7 +29,7 @@ struct mtk_clk_gate { u8 bit; }; -static inline struct mtk_clk_gate *to_clk_gate(struct clk_hw *hw) +static inline struct mtk_clk_gate *to_mtk_clk_gate(struct clk_hw *hw) { return container_of(hw, struct mtk_clk_gate, hw); } diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c index 28aac67e7b92..daa6ebdac131 100644 --- a/drivers/clk/mvebu/common.c +++ b/drivers/clk/mvebu/common.c @@ -199,8 +199,6 @@ struct clk_gating_ctrl { u32 saved_reg; }; -#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) - static struct clk_gating_ctrl *ctrl; static struct clk *clk_gating_get_src( diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c index 99550f25975e..a2a8d614039d 100644 --- a/drivers/clk/mvebu/kirkwood.c +++ b/drivers/clk/mvebu/kirkwood.c @@ -256,8 +256,6 @@ static const struct clk_muxing_soc_desc kirkwood_mux_desc[] __initconst = { 11, 1, 0 }, }; -#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) - static struct clk *clk_muxing_get_src( struct of_phandle_args *clkspec, void *data) { diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c index 049ee27d5a22..f75e989c578f 100644 --- a/drivers/clk/mxs/clk-div.c +++ b/drivers/clk/mxs/clk-div.c @@ -33,7 +33,7 @@ struct clk_div { static inline struct clk_div *to_clk_div(struct clk_hw *hw) { - struct clk_divider *divider = container_of(hw, struct clk_divider, hw); + struct clk_divider *divider = to_clk_divider(hw); return container_of(divider, struct clk_div, divider); } diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c index 558da89555af..f7136b94fd0e 100644 --- a/drivers/clk/nxp/clk-lpc18xx-ccu.c +++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c @@ -28,8 +28,6 @@ #define CCU_BRANCH_IS_BUS BIT(0) #define CCU_BRANCH_HAVE_DIV2 BIT(1) -#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) - struct lpc18xx_branch_clk_data { const char **name; int num; diff --git a/drivers/clk/st/clkgen-mux.c b/drivers/clk/st/clkgen-mux.c index 5dc5ce217960..0d9a74b66ea3 100644 --- a/drivers/clk/st/clkgen-mux.c +++ b/drivers/clk/st/clkgen-mux.c @@ -822,11 +822,10 @@ err: if (!clk_data->clks[i]) continue; - composite = container_of(__clk_get_hw(clk_data->clks[i]), - struct clk_composite, hw); - kfree(container_of(composite->gate_hw, struct clk_gate, hw)); - kfree(container_of(composite->rate_hw, struct clk_divider, hw)); - kfree(container_of(composite->mux_hw, struct clk_mux, hw)); + composite = to_clk_composite(__clk_get_hw(clk_data->clks[i])); + kfree(to_clk_gate(composite->gate_hw)); + kfree(to_clk_divider(composite->rate_hw)); + kfree(to_clk_mux(composite->mux_hw)); } kfree(clk_data->clks); diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c index dbef218fe5ec..43345c417815 100644 --- a/drivers/clk/ti/composite.c +++ b/drivers/clk/ti/composite.c @@ -28,8 +28,6 @@ #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ -#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) - static unsigned long ti_composite_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c index df2558350fc1..b4e5de16e561 100644 --- a/drivers/clk/ti/divider.c +++ b/drivers/clk/ti/divider.c @@ -26,8 +26,6 @@ #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ -#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) - #define div_mask(d) ((1 << ((d)->width)) - 1) static unsigned int _get_table_maxdiv(const struct clk_div_table *table) diff --git a/drivers/clk/ti/gate.c b/drivers/clk/ti/gate.c index 5429d3534363..bc05f276f32b 100644 --- a/drivers/clk/ti/gate.c +++ b/drivers/clk/ti/gate.c @@ -24,8 +24,6 @@ #include "clock.h" -#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) - #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c index dab9ba88b9d6..618ded96ace3 100644 --- a/drivers/clk/ti/mux.c +++ b/drivers/clk/ti/mux.c @@ -26,8 +26,6 @@ #undef pr_fmt #define pr_fmt(fmt) "%s: " fmt, __func__ -#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) - static u8 ti_clk_mux_get_parent(struct clk_hw *hw) { struct clk_mux *mux = to_clk_mux(hw); diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 408a60dca353..33dc814d0f43 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -276,6 +276,8 @@ struct clk_fixed_rate { u8 flags; }; +#define to_clk_fixed_rate(_hw) container_of(_hw, struct clk_fixed_rate, hw) + extern const struct clk_ops clk_fixed_rate_ops; struct clk *clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, @@ -314,6 +316,8 @@ struct clk_gate { spinlock_t *lock; }; +#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) + #define CLK_GATE_SET_TO_DISABLE BIT(0) #define CLK_GATE_HIWORD_MASK BIT(1) @@ -376,6 +380,8 @@ struct clk_divider { spinlock_t *lock; }; +#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw) + #define CLK_DIVIDER_ONE_BASED BIT(0) #define CLK_DIVIDER_POWER_OF_TWO BIT(1) #define CLK_DIVIDER_ALLOW_ZERO BIT(2) @@ -441,6 +447,8 @@ struct clk_mux { spinlock_t *lock; }; +#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw) + #define CLK_MUX_INDEX_ONE BIT(0) #define CLK_MUX_INDEX_BIT BIT(1) #define CLK_MUX_HIWORD_MASK BIT(2) @@ -484,6 +492,8 @@ struct clk_fixed_factor { unsigned int div; }; +#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) + extern const struct clk_ops clk_fixed_factor_ops; struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, @@ -515,6 +525,8 @@ struct clk_fractional_divider { spinlock_t *lock; }; +#define to_clk_fd(_hw) container_of(_hw, struct clk_fractional_divider, hw) + extern const struct clk_ops clk_fractional_divider_ops; struct clk *clk_register_fractional_divider(struct device *dev, const char *name, const char *parent_name, unsigned long flags, @@ -551,6 +563,8 @@ struct clk_multiplier { spinlock_t *lock; }; +#define to_clk_multiplier(_hw) container_of(_hw, struct clk_multiplier, hw) + #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0) #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1) @@ -580,6 +594,8 @@ struct clk_composite { const struct clk_ops *gate_ops; }; +#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw) + struct clk *clk_register_composite(struct device *dev, const char *name, const char * const *parent_names, int num_parents, struct clk_hw *mux_hw, const struct clk_ops *mux_ops, @@ -602,6 +618,8 @@ struct clk_gpio { struct gpio_desc *gpiod; }; +#define to_clk_gpio(_hw) container_of(_hw, struct clk_gpio, hw) + extern const struct clk_ops clk_gpio_gate_ops; struct clk *clk_register_gpio_gate(struct device *dev, const char *name, const char *parent_name, unsigned gpio, bool active_low, From 4974259e18f1fd519d4329babbfefa24852375bb Mon Sep 17 00:00:00 2001 From: James Liao Date: Fri, 8 Jan 2016 16:15:33 +0800 Subject: [PATCH 14/48] clk: mediatek: Fix memory leak on clock init fail mtk_clk_register_composite() may leak memory due to some error handling path don't free all allocated memory. This patch free all pointers that may allocate memory before error return. And it's safe because kfree() can handle NULL pointers. Signed-off-by: James Liao Reviewed-by: Daniel Kurtz Signed-off-by: Stephen Boyd --- drivers/clk/mediatek/clk-mtk.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c index cf08db6c130c..352830369e0e 100644 --- a/drivers/clk/mediatek/clk-mtk.c +++ b/drivers/clk/mediatek/clk-mtk.c @@ -209,12 +209,14 @@ struct clk * __init mtk_clk_register_composite(const struct mtk_composite *mc, mc->flags); if (IS_ERR(clk)) { - kfree(gate); - kfree(mux); + ret = PTR_ERR(clk); + goto err_out; } return clk; err_out: + kfree(div); + kfree(gate); kfree(mux); return ERR_PTR(ret); From b9e65ebc654dffeb77d8ef878bd6b2da30c55a94 Mon Sep 17 00:00:00 2001 From: James Liao Date: Thu, 28 Jan 2016 16:58:57 +0800 Subject: [PATCH 15/48] clk: Move vendor's Kconfig into CCF menu section Move all vendor's Kconfig into CCF menu section to prevent new drivers putting their Kconfig files in a wrong place. Some Kconfigs need to be modified at the same time to avoid build warnings. Signed-off-by: James Liao Acked-by: Sylwester Nawrocki [sboyd@codeaurora.org: Fix typos in commit message] Acked-by: Arnd Bergmann Signed-off-by: Stephen Boyd --- arch/arm/mach-s3c24xx/Kconfig | 1 + drivers/clk/Kconfig | 8 +++----- drivers/clk/samsung/Kconfig | 1 - 3 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig index ef68ecb27396..f02495f5ca1f 100644 --- a/arch/arm/mach-s3c24xx/Kconfig +++ b/arch/arm/mach-s3c24xx/Kconfig @@ -15,6 +15,7 @@ config PLAT_S3C24XX select NO_IOPORT_MAP select S3C_DEV_NAND select IRQ_DOMAIN + select COMMON_CLK help Base platform code for any Samsung S3C24XX device diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index eca8e019e005..de707b2bfb73 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -202,11 +202,9 @@ config COMMON_CLK_CDCE706 source "drivers/clk/bcm/Kconfig" source "drivers/clk/hisilicon/Kconfig" -source "drivers/clk/qcom/Kconfig" - -endmenu - source "drivers/clk/mvebu/Kconfig" - +source "drivers/clk/qcom/Kconfig" source "drivers/clk/samsung/Kconfig" source "drivers/clk/tegra/Kconfig" + +endmenu diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index 84196ecdaa12..b3fe5cb01afe 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -1,6 +1,5 @@ config COMMON_CLK_SAMSUNG bool - select COMMON_CLK config S3C2410_COMMON_CLK bool From 7633f8fb66c6de562b6299a0c888319de9aaf494 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 27 Jan 2016 00:36:45 -0300 Subject: [PATCH 16/48] ARM: exynos_defconfig: Remove MAX77802 RTC Kconfig symbol The driver has been removed so the Kconfig symbol is not valid anymore. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/exynos_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index c47c7e069873..6ffd7e76f3ce 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -195,7 +195,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_MAX8997=y CONFIG_RTC_DRV_MAX77686=y -CONFIG_RTC_DRV_MAX77802=y CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_S3C=y CONFIG_DMADEVICES=y From 5d51f1dde207f2d5d43158da75c6608f7bfcec03 Mon Sep 17 00:00:00 2001 From: Javier Martinez Canillas Date: Wed, 27 Jan 2016 00:36:46 -0300 Subject: [PATCH 17/48] ARM: multi_v7_defconfig: Remove MAX77802 RTC Kconfig symbol The driver has been removed so the Kconfig symbol is not valid anymore. Signed-off-by: Javier Martinez Canillas Reviewed-by: Krzysztof Kozlowski Reviewed-by: Andi Shyti Signed-off-by: Krzysztof Kozlowski --- arch/arm/configs/multi_v7_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 314f6be2dca2..bdb42c09332c 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -664,7 +664,6 @@ CONFIG_RTC_DRV_MAX8907=y CONFIG_RTC_DRV_MAX8997=m CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m -CONFIG_RTC_DRV_MAX77802=m CONFIG_RTC_DRV_RS5C372=m CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_ST_LPC=y From efdda175c07f34d4c8dd38bf23be8d15ef37e32e Mon Sep 17 00:00:00 2001 From: Srinivas Kandagatla Date: Sat, 6 Feb 2016 07:07:33 +0000 Subject: [PATCH 18/48] arm64: defconfig: add spmi and usb related configs This patch adds kconfigs for spmi bus support, pinctrl drivers and usb related to get USB working on Qualcomm DB410C board. Signed-off-by: Srinivas Kandagatla Signed-off-by: Olof Johansson --- arch/arm64/configs/defconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 86581f793e39..91ae2634cae9 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -144,16 +144,20 @@ CONFIG_I2C_RCAR=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_SPI_QUP=y +CONFIG_SPMI=y CONFIG_PINCTRL_MSM8916=y +CONFIG_PINCTRL_QCOM_SPMI_PMIC=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_XGENE=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y # CONFIG_HWMON is not set +CONFIG_MFD_SPMI_PMIC=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -166,13 +170,21 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_RCAR=y CONFIG_SND_SOC_AK4613=y CONFIG_USB=y +CONFIG_USB_OTG=y CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MSM=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y CONFIG_USB_ISP1760=y +CONFIG_USB_HSIC_USB3503=y +CONFIG_USB_MSM_OTG=y CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y CONFIG_MMC=y CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y @@ -213,6 +225,7 @@ CONFIG_QCOM_SMD_RPM=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_HISILICON_IRQ_MBIGEN=y +CONFIG_EXTCON_USB_GPIO=y CONFIG_PHY_XGENE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y From 382618bb1f7ef9bcd1622b40d443c9149af60c32 Mon Sep 17 00:00:00 2001 From: Anup Patel Date: Wed, 10 Feb 2016 11:40:46 +0530 Subject: [PATCH 19/48] arm64: Select COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc SoCs We select COMMON_CLK_IPROC, PINCTRL, and GPIOLIB in arm64 Kconfig for ARCH_BCM_IPROC so that we can use COMMON_CLK, PINCTRL and GPIOLIB with iProc SoC drivers. Signed-off-by: Anup Patel Signed-off-by: Ray Jui Signed-off-by: Yendapally Reddy Dhananjaya Reddy Signed-off-by: Florian Fainelli --- arch/arm64/Kconfig.platforms | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f674bde..e20b50cbe8dc 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -2,6 +2,9 @@ menu "Platform selection" config ARCH_BCM_IPROC bool "Broadcom iProc SoC Family" + select COMMON_CLK_IPROC + select PINCTRL + select ARCH_REQUIRE_GPIOLIB help This enables support for Broadcom iProc based SoCs From 215cd9674fa02e4b341e4568d20ef5fd6fab1b0b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 Feb 2016 15:20:30 +0900 Subject: [PATCH 20/48] clk: samsung: Enable COMPILE_TEST for Samsung clocks Enable the COMPILE_TEST to get build coverage of some of Samsung clock controller drivers. Still some of them will be built only if appropriate SoC is chosen (like SOC_EXYNOS4415 or ARCH_S3C64XX). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Reviewed-by: Andi Shyti Signed-off-by: Michael Turquette --- drivers/clk/samsung/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index b3fe5cb01afe..dd6093a33f84 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -1,8 +1,8 @@ config COMMON_CLK_SAMSUNG - bool + bool "Samsung Exynos clock controller support" if COMPILE_TEST config S3C2410_COMMON_CLK - bool + bool "Samsung S3C2410 clock controller support" if COMPILE_TEST select COMMON_CLK_SAMSUNG help Build the s3c2410 clock driver based on the common clock framework. @@ -16,10 +16,10 @@ config S3C2410_COMMON_DCLK framework. config S3C2412_COMMON_CLK - bool + bool "Samsung S3C2412 clock controller support" if COMPILE_TEST select COMMON_CLK_SAMSUNG config S3C2443_COMMON_CLK - bool + bool "Samsung S3C2443 clock controller support" if COMPILE_TEST select COMMON_CLK_SAMSUNG From b4f596b19624d14864596b5b43de5f04cadd4895 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 2 Feb 2016 18:12:37 +0100 Subject: [PATCH 21/48] arm64: add mvebu architecture entry The Armada 3700 is an mvebu ARM64 SoC using one or two Cortex-A53 cores depending of the variant. Signed-off-by: Gregory CLEMENT Reviewed-by: Thomas Petazzoni --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f674bde..85bec422d508 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -48,6 +48,12 @@ config ARCH_MEDIATEK help Support for Mediatek MT65xx & MT81xx ARMv8 SoCs +config ARCH_MVEBU + bool "Marvell EBU SoC Family" + help + This enables support for Marvell EBU family such as the + Armada 3700 SoC family. + config ARCH_QCOM bool "Qualcomm Platforms" select PINCTRL From dcc3068a757ebd38b20e35221f744930b23daa45 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 2 Feb 2016 18:14:16 +0100 Subject: [PATCH 22/48] MAINTAINERS: Extend dts entry for ARM64 mvebu files Extend the mvebu entry to ARM64 device tree sources. Signed-off-by: Gregory CLEMENT Reviewed-by: Thomas Petazzoni --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 30aca4aa5467..ad49b62c5abc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1279,6 +1279,7 @@ F: arch/arm/mach-mvebu/ F: drivers/rtc/rtc-armada38x.c F: arch/arm/boot/dts/armada* F: arch/arm/boot/dts/kirkwood* +F: arch/arm64/boot/dts/marvell/armada* ARM/Marvell Berlin SoC support From a71916b027709afca630609bfa68cd3ed853cb6b Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 2 Feb 2016 18:14:33 +0100 Subject: [PATCH 23/48] Documentation: arm: update supported Marvell EBU processors Now that we support Armada 37xx, let's add this family of SoC to the Marvell documentation, and a reference to a link with more details about those processors. As for Armda 39x, no datasheet is publicly available at this time. Signed-off-by: Gregory CLEMENT --- Documentation/arm/Marvell/README | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index ae89b67d8e23..ddbc048bb467 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -118,6 +118,19 @@ EBU Armada family Linux kernel mach directory: arch/arm/mach-mvebu Linux kernel plat directory: none +EBU Armada family ARMv8 +----------------------- + + Armada 3710/3720 Flavors: + 88F3710 + 88F3720 + + Core: ARM Cortex A53 (ARMv8) + + Homepage : http://www.marvell.com/embedded-processors/armada-3700/ + + Device tree descritpion located in arch/arm64/boot/dts/marvell/armada-37* + Avanta family ------------- From e772ca05cceb1480bdc7a7579e042b18558d0959 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Tue, 2 Feb 2016 18:15:24 +0100 Subject: [PATCH 24/48] arm64: defconfig: enable Armada 3700 related config This patch enables the configuration for the Armada 3700 family and for the related driver it uses. Signed-off-by: Gregory CLEMENT Reviewed-by: Thomas Petazzoni --- arch/arm64/configs/defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 86581f793e39..00a49b4e61c1 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -30,6 +30,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_MVEBU=y CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BERLIN=y CONFIG_ARCH_EXYNOS7=y @@ -95,6 +96,7 @@ CONFIG_ATA=y CONFIG_SATA_AHCI=y CONFIG_SATA_AHCI_PLATFORM=y CONFIG_AHCI_CEVA=y +CONFIG_AHCI_MVEBU=y CONFIG_AHCI_XGENE=y CONFIG_SATA_RCAR=y CONFIG_PATA_PLATFORM=y @@ -136,6 +138,7 @@ CONFIG_SERIAL_MSM=y CONFIG_SERIAL_MSM_CONSOLE=y CONFIG_SERIAL_XILINX_PS_UART=y CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_MVEBU_UART=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C_QUP=y @@ -166,6 +169,8 @@ CONFIG_SND_SOC=y CONFIG_SND_SOC_RCAR=y CONFIG_SND_SOC_AK4613=y CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_HCD_PLATFORM=y CONFIG_USB_OHCI_HCD=y From f7e020512e10a185d58d0f11faa57093345fd5b2 Mon Sep 17 00:00:00 2001 From: Magnus Damm Date: Tue, 16 Feb 2016 11:26:53 +0900 Subject: [PATCH 25/48] arm64: renesas: Enable RENESAS_IRQC Select RENESAS_IRQC for Arm64 SoCs from Renesas to enable build of drivers/irqchip/irq-renesas-irqc.c. Signed-off-by: Magnus Damm Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f674bde..757220cb1b7f 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -77,6 +77,7 @@ config ARCH_RENESAS select ARCH_SHMOBILE select PINCTRL select PM_GENERIC_DOMAINS if PM + select RENESAS_IRQC help This enables support for the ARMv8 based Renesas SoCs. From 2ee98234b88174f2bcafefb7918e2794a1fdbc98 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 16 Feb 2016 15:29:10 +0100 Subject: [PATCH 26/48] arm64: renesas: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains All supported Renesas ARM64 SoCs have clock and power domains. To ensure proper operation of on-SoC modules, module clocks must be ungated, and power domains must be powered up when needed. Currently the user can choose to build a kernel with power management enabled or disabled: - If CONFIG_PM=y, power domains and/or module clocks are handled dynamically by Runtime PM and the generic power domain. - If CONFIG_PM=n, power domains are assumed to be powered up by reset state or by the boot loader, and module clocks are handled by the legacy clock domain on driver (un)bind. The latter is implemented using a platform bus notifier, which applies not only to all on-SoC devices, but to all platform devices present in the system. To remove the dependency on implicit assumptions, and to get rid of the peculiarities of the legacy clock domain, enable CONFIG_PM and CONFIG_PM_GENERIC_DOMAINS unconditionally. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/Kconfig.platforms | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 757220cb1b7f..e011ac0e17a3 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -76,7 +76,8 @@ config ARCH_RENESAS bool "Renesas SoC Platforms" select ARCH_SHMOBILE select PINCTRL - select PM_GENERIC_DOMAINS if PM + select PM + select PM_GENERIC_DOMAINS select RENESAS_IRQC help This enables support for the ARMv8 based Renesas SoCs. From 2859f70a0ce74df5bba7d6145a99ff54ac0e3a53 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Thu, 18 Feb 2016 17:20:25 +0100 Subject: [PATCH 27/48] Documentation: arm: update Marvell product listing I'm still getting confused regarding which core specifically is used in which SoC, so I've added some more detail to the Marvell README file. I got most of this from random sources on the internet, so it's possible that some of the information is wrong, but most of it should be pretty obvious. There are a few remaining points I could not find out: * The CPU core in Orion 88F6183 * The difference (if any) between PJ4B-MP and PJ4C * The naming of Feroceon/Jolteon/Flareon/Sheeva/Mohawk/PJ1/PJ4 is still confusing, as they tend to overlap. Signed-off-by: Arnd Bergmann [Thomas: - move Armada SP out from the EBU family into its own "Storage" family. This chip is indeed not part of the EBU family. - fixed the URL for the Armada SP information, since the link of the original patch no longer existed - explicitly indicate that there is no support in upstream for the Armada SP - indent the "Core: " description for the Armada XP to be clearly under the Armada XP category, so that it is clear it applies to Armada XP only, and not other cores of the EBU family.] Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- Documentation/arm/Marvell/README | 128 +++++++++++++++++++++++++------ 1 file changed, 103 insertions(+), 25 deletions(-) diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index ddbc048bb467..981164fe9673 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -22,7 +22,7 @@ Orion family 88F5281 Datasheet : http://www.ocmodshop.com/images/reviews/networking/qnap_ts409u/marvel_88f5281_data_sheet.pdf 88F6183 - Core: Feroceon ARMv5 compatible + Core: Feroceon 88fr331 (88f51xx) or 88fr531-vd (88f52xx) ARMv5 compatible Linux kernel mach directory: arch/arm/mach-orion5x Linux kernel plat directory: arch/arm/plat-orion @@ -52,7 +52,7 @@ Kirkwood family Hardware Spec : http://www.marvell.com/embedded-processors/kirkwood/assets/HW_88F6281_OpenSource.pdf Functional Spec: http://www.marvell.com/embedded-processors/kirkwood/assets/FS_88F6180_9x_6281_OpenSource.pdf Homepage: http://www.marvell.com/embedded-processors/kirkwood/ - Core: Feroceon ARMv5 compatible + Core: Feroceon 88fr131 ARMv5 compatible Linux kernel mach directory: arch/arm/mach-mvebu Linux kernel plat directory: none @@ -71,7 +71,7 @@ Discovery family MV76100 Not supported by the Linux kernel. - Core: Feroceon ARMv5 compatible + Core: Feroceon 88fr571-vd ARMv5 compatible Linux kernel mach directory: arch/arm/mach-mv78xx0 Linux kernel plat directory: arch/arm/plat-orion @@ -86,20 +86,25 @@ EBU Armada family Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/Marvell_ARMADA_370_SoC.pdf Hardware Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-datasheet.pdf Functional Spec: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA370-FunctionalSpec-datasheet.pdf + Core: Sheeva ARMv7 compatible PJ4B Armada 375 Flavors: 88F6720 Product Brief: http://www.marvell.com/embedded-processors/armada-300/assets/ARMADA_375_SoC-01_product_brief.pdf + Core: ARM Cortex-A9 - Armada 380/385 Flavors: - 88F6810 - 88F6820 - 88F6828 + Armada 38x Flavors: + 88F6810 Armada 380 + 88F6820 Armada 385 + 88F6828 Armada 388 + Produce infos: http://www.marvell.com/embedded-processors/armada-38x/ + Core: ARM Cortex-A9 - Armada 390/398 Flavors: - 88F6920 - 88F6928 + Armada 39x Flavors: + 88F6920 Armada 390 + 88F6928 Armada 398 Product infos: http://www.marvell.com/embedded-processors/armada-39x/ + Core: ARM Cortex-A9 Armada XP Flavors: MV78230 @@ -112,8 +117,7 @@ EBU Armada family http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78230_OS.PDF http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78260_OS.PDF http://www.marvell.com/embedded-processors/armada-xp/assets/HW_MV78460_OS.PDF - - Core: Sheeva ARMv7 compatible + Core: Sheeva ARMv7 compatible Dual-core or Quad-core PJ4B-MP Linux kernel mach directory: arch/arm/mach-mvebu Linux kernel plat directory: none @@ -148,6 +152,15 @@ Avanta family Linux kernel mach directory: no code in mainline yet, planned for the future Linux kernel plat directory: no code in mainline yet, planned for the future +Storage family +-------------- + + Armada SP: + 88RC1580 + Product infos: http://www.marvell.com/storage/armada-sp/ + Core: Sheeva ARMv7 comatible Quad-core PJ4C + (not supported in upstream Linux kernel) + Dove family (application processor) ----------------------------------- @@ -168,7 +181,7 @@ PXA 2xx/3xx/93x/95x family Flavors: PXA21x, PXA25x, PXA26x Application processor only - Core: ARMv5 XScale core + Core: ARMv5 XScale1 core PXA270, PXA271, PXA272 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_pb.pdf Design guide : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_design_guide.pdf @@ -176,7 +189,7 @@ PXA 2xx/3xx/93x/95x family Specification : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_emts.pdf Specification update : http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_spec_update.pdf Application processor only - Core: ARMv5 XScale core + Core: ARMv5 XScale2 core PXA300, PXA310, PXA320 PXA 300 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA300_PB_R4.pdf PXA 310 Product Brief : http://www.marvell.com/application-processors/pxa-family/assets/PXA310_PB_R4.pdf @@ -187,10 +200,10 @@ PXA 2xx/3xx/93x/95x family Specification Update : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_Spec_Update.zip Reference Manual : http://www.marvell.com/application-processors/pxa-family/assets/PXA3xx_TavorP_BootROM_Ref_Manual.pdf Application processor only - Core: ARMv5 XScale core + Core: ARMv5 XScale3 core PXA930, PXA935 Application processor with Communication processor - Core: ARMv5 XScale core + Core: ARMv5 XScale3 core PXA955 Application processor with Communication processor Core: ARMv7 compatible Sheeva PJ4 core @@ -209,7 +222,7 @@ PXA 2xx/3xx/93x/95x family Linux kernel mach directory: arch/arm/mach-pxa Linux kernel plat directory: arch/arm/plat-pxa -MMP/MMP2 family (communication processor) +MMP/MMP2/MMP3 family (communication processor) ----------------------------------------- Flavors: @@ -222,16 +235,32 @@ MMP/MMP2 family (communication processor) Boot ROM manual : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_ref_manual.pdf App node package : http://www.marvell.com/application-processors/armada-100/assets/armada_16x_app_note_package.pdf Application processor only - Core: ARMv5 compatible Marvell PJ1 (Mohawk) - PXA910 + Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk) + PXA910/PXA920 Homepage : http://www.marvell.com/communication-processors/pxa910/ Product Brief : http://www.marvell.com/communication-processors/pxa910/assets/Marvell_PXA910_Platform-001_PB_final.pdf Application processor with Communication processor - Core: ARMv5 compatible Marvell PJ1 (Mohawk) - MMP2, a.k.a Armada 610 + Core: ARMv5 compatible Marvell PJ1 88sv331 (Mohawk) + PXA688, a.k.a. MMP2, a.k.a Armada 610 Product Brief : http://www.marvell.com/application-processors/armada-600/assets/armada610_pb.pdf Application processor only - Core: ARMv7 compatible Sheeva PJ4 core + Core: ARMv7 compatible Sheeva PJ4 88sv581x core + PXA2128, a.k.a. MMP3 (OLPC XO4, Linux support not upstream) + Product Brief : http://www.marvell.com/application-processors/armada/pxa2128/assets/Marvell-ARMADA-PXA2128-SoC-PB.pdf + Application processor only + Core: Dual-core ARMv7 compatible Sheeva PJ4C core + PXA960/PXA968/PXA978 (Linux support not upstream) + Application processor with Communication Processor + Core: ARMv7 compatible Sheeva PJ4 core + PXA986/PXA988 (Linux support not upstream) + Application processor with Communication Processor + Core: Dual-core ARMv7 compatible Sheeva PJ4B-MP core + PXA1088/PXA1920 (Linux support not upstream) + Application processor with Communication Processor + Core: quad-core ARMv7 Cortex-A7 + PXA1908/PXA1928/PXA1936 + Application processor with Communication Processor + Core: multi-core ARMv8 Cortex-A53 Comments: @@ -250,6 +279,10 @@ Berlin family (Multimedia Solutions) ------------------------------------- Flavors: + 88DE3010, Armada 1000 (no Linux support) + Core: Marvell PJ1 (ARMv5TE), Dual-core + Product Brief: http://www.marvell.com.cn/digital-entertainment/assets/armada_1000_pb.pdf + 88DE3005, Armada 1500-mini 88DE3005, Armada 1500 Mini Design name: BG2CD Core: ARM Cortex-A9, PL310 L2CC @@ -260,14 +293,16 @@ Berlin family (Multimedia Solutions) Homepage: http://www.marvell.com/multimedia-solutions/armada-1500-mini-plus/ 88DE3100, Armada 1500 Design name: BG2 - Core: Marvell PJ4B (ARMv7), Tauros3 L2CC - Product Brief: http://www.marvell.com/multimedia-solutions/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf + Core: Marvell PJ4B-MP (ARMv7), Tauros3 L2CC + Product Brief: http://www.marvell.com/digital-entertainment/armada-1500/assets/Marvell-ARMADA-1500-Product-Brief.pdf 88DE3114, Armada 1500 Pro Design name: BG2Q Core: Quad Core ARM Cortex-A9, PL310 L2CC - 88DE???? + 88DE3214, Armada 1500 Pro 4K Design name: BG3 Core: ARM Cortex-A15, CA15 integrated L2CC + 88DE3218, ARMADA 1500 Ultra + Core: ARM Cortex-A53 Homepage: http://www.marvell.com/multimedia-solutions/ Directory: arch/arm/mach-berlin @@ -276,6 +311,49 @@ Berlin family (Multimedia Solutions) * This line of SoCs is based on Marvell Sheeva or ARM Cortex CPUs with Synopsys DesignWare (IRQ, GPIO, Timers, ...) and PXA IP (SDHCI, USB, ETH, ...). +CPU Cores +--------- + +The XScale cores were designed by Intel, and shipped by Marvell in the older +PXA processors. Feroceon is a Marvell designed core that developed in-house, +and that evolved into Sheeva. The XScale and Feroceon cores were phased out +over time and replaced with Sheeva cores in later products, which subsequently +got replaced with licensed ARM Cortex-A cores. + + XScale 1 + CPUID 0x69052xxx + ARMv5, iWMMXt + XScale 2 + CPUID 0x69054xxx + ARMv5, iWMMXt + XScale 3 + CPUID 0x69056xxx or 0x69056xxx + ARMv5, iWMMXt + Feroceon-1850 88fr331 "Mohawk" + CPUID 0x5615331x or 0x41xx926x + ARMv5TE, single issue + Feroceon-2850 88fr531-vd "Jolteon" + CPUID 0x5605531x or 0x41xx926x + ARMv5TE, VFP, dual-issue + Feroceon 88fr571-vd "Jolteon" + CPUID 0x5615571x + ARMv5TE, VFP, dual-issue + Feroceon 88fr131 "Mohawk-D" + CPUID 0x5625131x + ARMv5TE, single-issue in-order + Sheeva PJ1 88sv331 "Mohawk" + CPUID 0x561584xx + ARMv5, single-issue iWMMXt v2 + Sheeva PJ4 88sv581x "Flareon" + CPUID 0x560f581x + ARMv7, idivt, optional iWMMXt v2 + Sheeva PJ4B 88sv581x + CPUID 0x561f581x + ARMv7, idivt, optional iWMMXt v2 + Sheeva PJ4B-MP / PJ4C + CPUID 0x562f584x + ARMv7, idivt/idiva, LPAE, optional iWMMXt v2 and/or NEON + Long-term plans --------------- From e737acd6ba275b42f98c94227823dc3cc9d0bc61 Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 Feb 2016 17:20:26 +0100 Subject: [PATCH 28/48] Documentation: arm: improve Armada 37xx description In preparation to the introduction of other SoCs in the ARMv8 Armada EBU family, this commit tweaks the existing description of Armada 37xx by making the core, homepage and other informations be visible "under" the Armada 37xx item. Indeed, the new SoCs will not share the same core or homepage. In addition, a link to the Product Brief is added. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- Documentation/arm/Marvell/README | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index 981164fe9673..a78453b88cc7 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -128,12 +128,11 @@ EBU Armada family ARMv8 Armada 3710/3720 Flavors: 88F3710 88F3720 + Core: ARM Cortex A53 (ARMv8) - Core: ARM Cortex A53 (ARMv8) - - Homepage : http://www.marvell.com/embedded-processors/armada-3700/ - - Device tree descritpion located in arch/arm64/boot/dts/marvell/armada-37* + Homepage: http://www.marvell.com/embedded-processors/armada-3700/ + Product Brief: http://www.marvell.com/embedded-processors/assets/PB-88F3700-FNL.pdf + Device tree files: arch/arm64/boot/dts/marvell/armada-37* Avanta family ------------- From c44fdc3bf4cbb8a25edc2e34448d3df077ee40fa Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 Feb 2016 17:20:27 +0100 Subject: [PATCH 29/48] Documentation: arm: add link to Armada 38x Functional Spec The Armada 38x Functional Spec is now available (after registration unfortunately), so add a link to it. While at it, fix a typo in the reference to the Armada 38x product page. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- Documentation/arm/Marvell/README | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index a78453b88cc7..fe867f173959 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -97,7 +97,8 @@ EBU Armada family 88F6810 Armada 380 88F6820 Armada 385 88F6828 Armada 388 - Produce infos: http://www.marvell.com/embedded-processors/armada-38x/ + Product infos: http://www.marvell.com/embedded-processors/armada-38x/ + Functional Spec: https://marvellcorp.wufoo.com/forms/marvell-armada-38x-functional-specifications/ Core: ARM Cortex-A9 Armada 39x Flavors: From 1d0029cb36a218aeee6fbac26459c2d92c7f190d Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 Feb 2016 17:20:28 +0100 Subject: [PATCH 30/48] Documentation: arm: add Marvell Armada 7K and 8K families As we are adding support for the Armada 7K and 8K families, this commit adds them to the Marvell documentation listing all supported SoCs, together with references to their Product Brief, Homepage and Device Tree files. Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- Documentation/arm/Marvell/README | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README index fe867f173959..b5bb7f518840 100644 --- a/Documentation/arm/Marvell/README +++ b/Documentation/arm/Marvell/README @@ -135,6 +135,26 @@ EBU Armada family ARMv8 Product Brief: http://www.marvell.com/embedded-processors/assets/PB-88F3700-FNL.pdf Device tree files: arch/arm64/boot/dts/marvell/armada-37* + Armada 7K Flavors: + 88F7020 (AP806 Dual + one CP110) + 88F7040 (AP806 Quad + one CP110) + Core: ARM Cortex A72 + + Homepage: http://www.marvell.com/embedded-processors/armada-70xx/ + Product Brief: http://www.marvell.com/embedded-processors/assets/Armada7020PB-Jan2016.pdf + http://www.marvell.com/embedded-processors/assets/Armada7040PB-Jan2016.pdf + Device tree files: arch/arm64/boot/dts/marvell/armada-70* + + Armada 8K Flavors: + 88F8020 (AP806 Dual + two CP110) + 88F8040 (AP806 Quad + two CP110) + Core: ARM Cortex A72 + + Homepage: http://www.marvell.com/embedded-processors/armada-80xx/ + Product Brief: http://www.marvell.com/embedded-processors/assets/Armada8020PB-Jan2016.pdf + http://www.marvell.com/embedded-processors/assets/Armada8040PB-Jan2016.pdf + Device tree files: arch/arm64/boot/dts/marvell/armada-80* + Avanta family ------------- From b3920b2b2388117d0fae5e2d15d626050f6883ea Mon Sep 17 00:00:00 2001 From: Thomas Petazzoni Date: Thu, 18 Feb 2016 17:20:29 +0100 Subject: [PATCH 31/48] arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support This commit updates the ARCH_MVEBU Kconfig option introduced for Armada 3700 to also be used for the Armada 7K and 8K platforms, by: - Selecting the appropriate clock and irqchip drivers - Updating the help text to mention Armada 7K and 8K Signed-off-by: Thomas Petazzoni Signed-off-by: Gregory CLEMENT --- arch/arm64/Kconfig.platforms | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 85bec422d508..c9a184bd7ae2 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -50,9 +50,14 @@ config ARCH_MEDIATEK config ARCH_MVEBU bool "Marvell EBU SoC Family" + select ARMADA_AP806_CORE_CLK + select ARMADA_AP806_RING_CLK + select MVEBU_ODMI help - This enables support for Marvell EBU family such as the - Armada 3700 SoC family. + This enables support for Marvell EBU familly, including: + - Armada 3700 SoC Family + - Armada 7K SoC Family + - Armada 8K SoC Family config ARCH_QCOM bool "Qualcomm Platforms" From 4cf430ee0c2ba1da97cab10b904291eb6fc5f170 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Sat, 20 Feb 2016 19:49:22 +0530 Subject: [PATCH 32/48] arm64: defconfig: Add Broadcom Vulcan to defconfig Enable Broadcom Vulcan support in arm64 default configuration. This will build the device tree needed to boot on a Broadcom Vulcan board. Signed-off-by: Jayachandran C Signed-off-by: Florian Fainelli --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 18ca9fb9e65f..52c27117bd80 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -50,6 +50,7 @@ CONFIG_ARCH_SPRD=y CONFIG_ARCH_THUNDER=y CONFIG_ARCH_UNIPHIER=y CONFIG_ARCH_VEXPRESS=y +CONFIG_ARCH_VULCAN=y CONFIG_ARCH_XGENE=y CONFIG_ARCH_ZYNQMP=y CONFIG_PCI=y From 5bfb3889878756a7f6b673df1738c473424e169f Mon Sep 17 00:00:00 2001 From: Zi Shen Lim Date: Sat, 20 Feb 2016 19:49:20 +0530 Subject: [PATCH 33/48] arm64: Broadcom Vulcan support Add a configuration option and a device tree for Broadcom's Vulcan ARM64 processor. vulcan.dtsi has the on-chip blocks like the PCIe controller, GICv3 with ITS, PMU, system timer and the pl011 UART. vulcan-eval.dts has definitions for a basic evaluation board. Vulcan's processor cores support the ARMv8.1 instruction set and will use "brcm,vulcan" as the compatible property. The firmware has PSCI 0.2 support for cpu wakeup. Signed-off-by: Zi Shen Lim [ updated and split dts - jchandra@broadcom.com ] Signed-off-by: Jayachandran C Signed-off-by: Florian Fainelli --- arch/arm64/Kconfig.platforms | 5 + arch/arm64/boot/dts/broadcom/Makefile | 1 + arch/arm64/boot/dts/broadcom/vulcan-eval.dts | 33 +++++ arch/arm64/boot/dts/broadcom/vulcan.dtsi | 144 +++++++++++++++++++ 4 files changed, 183 insertions(+) create mode 100644 arch/arm64/boot/dts/broadcom/vulcan-eval.dts create mode 100644 arch/arm64/boot/dts/broadcom/vulcan.dtsi diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index e20b50cbe8dc..c57b2cf516ac 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -134,6 +134,11 @@ config ARCH_VEXPRESS This enables support for the ARMv8 software model (Versatile Express). +config ARCH_VULCAN + bool "Broadcom Vulcan SOC Family" + help + This enables support for Broadcom Vulcan SoC Family + config ARCH_XGENE bool "AppliedMicro X-Gene SOC Family" help diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile index e21fe66f1837..bec1f8b36f60 100644 --- a/arch/arm64/boot/dts/broadcom/Makefile +++ b/arch/arm64/boot/dts/broadcom/Makefile @@ -1,4 +1,5 @@ dtb-$(CONFIG_ARCH_BCM_IPROC) += ns2-svk.dtb +dtb-$(CONFIG_ARCH_VULCAN) += vulcan-eval.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/boot/dts/broadcom/vulcan-eval.dts b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts new file mode 100644 index 000000000000..9ee8d3da0e3f --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/vulcan-eval.dts @@ -0,0 +1,33 @@ +/* + * dts file for Broadcom (BRCM) Vulcan Evaluation Platform + * + * Copyright (c) 2013-2016 Broadcom + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/dts-v1/; + +#include "vulcan.dtsi" + +/ { + model = "Broadcom Vulcan Eval Platform"; + compatible = "brcm,vulcan-eval", "brcm,vulcan-soc"; + + memory { + device_type = "memory"; + reg = <0x00000000 0x80000000 0x0 0x80000000>, /* 2G @ 2G */ + <0x00000008 0x80000000 0x0 0x80000000>; /* 2G @ 34G */ + }; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; diff --git a/arch/arm64/boot/dts/broadcom/vulcan.dtsi b/arch/arm64/boot/dts/broadcom/vulcan.dtsi new file mode 100644 index 000000000000..c49b5a85809c --- /dev/null +++ b/arch/arm64/boot/dts/broadcom/vulcan.dtsi @@ -0,0 +1,144 @@ +/* + * dtsi file for Broadcom (BRCM) Vulcan processor + * + * Copyright (c) 2013-2016 Broadcom + * Author: Zi Shen Lim + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include + +/ { + model = "Broadcom Vulcan"; + compatible = "brcm,vulcan-soc"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + /* just 4 cpus now, 128 needed in full config */ + cpus { + #address-cells = <0x2>; + #size-cells = <0x0>; + + cpu@0 { + device_type = "cpu"; + compatible = "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "brcm,vulcan", "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + gic: interrupt-controller@400080000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupt-controller; + #redistributor-regions = <1>; + reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */ + <0x04 0x01000000 0x0 0x1000000>; /* GICR */ + interrupts = ; + + gicits: gic-its@40010000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */ + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; /* PMU overflow */ + }; + + clk125mhz: uart_clk125mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clk125mhz"; + }; + + pci { + compatible = "pci-host-ecam-generic"; + device_type = "pci"; + #interrupt-cells = <1>; + #address-cells = <3>; + #size-cells = <2>; + + /* ECAM at 0x3000_0000 - 0x4000_0000 */ + reg = <0x0 0x30000000 0x0 0x10000000>; + reg-names = "PCI ECAM"; + + /* IO 0x4000_0000 - 0x4001_0000 */ + ranges = <0x01000000 0 0x40000000 0 0x40000000 0 0x00010000 + /* MEM 0x4800_0000 - 0x5000_0000 */ + 0x02000000 0 0x48000000 0 0x48000000 0 0x08000000 + /* MEM64 pref 0x6_0000_0000 - 0x7_0000_0000 */ + 0x43000000 6 0x00000000 6 0x00000000 1 0x00000000>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = + /* addr pin ic icaddr icintr */ + <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; + msi-parent = <&gicits>; + dma-coherent; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + uart0: serial@402020000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x04 0x02020000 0x0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&clk125mhz>; + clock-names = "apb_pclk"; + }; + }; + +}; From 9eb8a2cdf65ce47c3aa68f1297c84d8bcf5a7b3a Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Sat, 20 Feb 2016 19:49:23 +0530 Subject: [PATCH 34/48] arm64: cputype info for Broadcom Vulcan Add Broadcom Vulcan implementor ID and part ID in cputype.h. This is to document the values. Signed-off-by: Jayachandran C Acked-by: Will Deacon Acked-by: Catalin Marinas Signed-off-by: Florian Fainelli --- arch/arm64/include/asm/cputype.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index 1a5949364ed0..3dcecdf3d6ee 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -65,6 +65,7 @@ #define ARM_CPU_IMP_ARM 0x41 #define ARM_CPU_IMP_APM 0x50 #define ARM_CPU_IMP_CAVIUM 0x43 +#define ARM_CPU_IMP_BRCM 0x42 #define ARM_CPU_PART_AEM_V8 0xD0F #define ARM_CPU_PART_FOUNDATION 0xD00 @@ -75,6 +76,8 @@ #define CAVIUM_CPU_PART_THUNDERX 0x0A1 +#define BRCM_CPU_PART_VULCAN 0x516 + #ifndef __ASSEMBLY__ /* From 42515e61d414abff6cdded90ef0f607347e0ceb7 Mon Sep 17 00:00:00 2001 From: Jayachandran C Date: Sat, 20 Feb 2016 19:49:24 +0530 Subject: [PATCH 35/48] MAINTAINERS: Add entry for Broadcom Vulcan SoC Add maintainer information for Broadcom's Vulcan arm64 SoC. Signed-off-by: Jayachandran C Signed-off-by: Florian Fainelli --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 30aca4aa5467..d30f3e2724b9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2515,6 +2515,13 @@ L: netdev@vger.kernel.org S: Supported F: drivers/net/ethernet/broadcom/bcmsysport.* +BROADCOM VULCAN ARM64 SOC +M: Jayachandran C. +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +L: bcm-kernel-feedback-list@broadcom.com +S: Maintained +F: arch/arm64/boot/dts/broadcom/vulcan* + BROCADE BFA FC SCSI DRIVER M: Anil Gurumurthy M: Sudarsana Kalluru From 85997a7cba7bc1578eb554e88f82023d85fb499a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 16 Feb 2016 15:20:31 +0900 Subject: [PATCH 36/48] clk: samsung: Don't build ARMv8 clock drivers on ARMv7 Currently the Exynos5433 (ARMv8 SoC) clock driver depends on ARCH_EXYNOS so it is built also on ARMv7. This does not bring any kind of benefit. There won't be a single kernel image for ARMv7 and ARMv8 SoCs (like multi_v7 for ARMv7). Instead build clock drivers only for respective SoC's architecture. Signed-off-by: Krzysztof Kozlowski Acked-by: Sylwester Nawrocki Signed-off-by: Michael Turquette --- drivers/clk/samsung/Kconfig | 10 +++++++++- drivers/clk/samsung/Makefile | 4 ++-- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig index dd6093a33f84..20c5fe92ab4a 100644 --- a/drivers/clk/samsung/Kconfig +++ b/drivers/clk/samsung/Kconfig @@ -1,6 +1,15 @@ +# Recent Exynos platforms should just select COMMON_CLK_SAMSUNG: config COMMON_CLK_SAMSUNG bool "Samsung Exynos clock controller support" if COMPILE_TEST + # Clocks on ARM64 SoCs (e.g. Exynos5433, Exynos7) are chosen by + # EXYNOS_ARM64_COMMON_CLK to avoid building them on ARMv7: + select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS +config EXYNOS_ARM64_COMMON_CLK + bool "Samsung Exynos ARMv8-family clock controller support" if COMPILE_TEST + depends on COMMON_CLK_SAMSUNG + +# For S3C24XX platforms, select following symbols: config S3C2410_COMMON_CLK bool "Samsung S3C2410 clock controller support" if COMPILE_TEST select COMMON_CLK_SAMSUNG @@ -22,4 +31,3 @@ config S3C2412_COMMON_CLK config S3C2443_COMMON_CLK bool "Samsung S3C2443 clock controller support" if COMPILE_TEST select COMMON_CLK_SAMSUNG - diff --git a/drivers/clk/samsung/Makefile b/drivers/clk/samsung/Makefile index 5f6833ea355d..fc367d4b2902 100644 --- a/drivers/clk/samsung/Makefile +++ b/drivers/clk/samsung/Makefile @@ -10,11 +10,11 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o -obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos5433.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos5433.o obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-clkout.o -obj-$(CONFIG_ARCH_EXYNOS7) += clk-exynos7.o +obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o obj-$(CONFIG_S3C2410_COMMON_CLK)+= clk-s3c2410.o obj-$(CONFIG_S3C2410_COMMON_DCLK)+= clk-s3c2410-dclk.o obj-$(CONFIG_S3C2412_COMMON_CLK)+= clk-s3c2412.o From c87b3e970c70d5e27f9eb9acd09c6b5b9d589860 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 16 Nov 2015 10:09:13 +0900 Subject: [PATCH 37/48] arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS The ARMv8 Exynos family SoCs in Linux kernel are currently: - Exynos5433 (controlled by ARCH_EXYNOS), - Exynos7 (controlled by ARCH_EXYNOS7). It duplicates Kconfig symbols unnecessarily, so consolidate them into one ARCH_EXYNOS. Future SoCs could fall also under the ARCH_EXYNOS symbol. The commit should not bring any visible functional change. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Reviewed-by: Pankaj Dubey Tested-by: Alim Akhtar Reviewed-by: Tomasz Figa Reviewed-by: Javier Martinez Canillas Reviewed-by: Andi Shyti --- arch/arm64/Kconfig.platforms | 11 ++--------- arch/arm64/boot/dts/exynos/Makefile | 2 +- arch/arm64/configs/defconfig | 2 +- 3 files changed, 4 insertions(+), 11 deletions(-) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f674bde..653662bbafeb 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -14,21 +14,14 @@ config ARCH_BERLIN This enables support for Marvell Berlin SoC Family config ARCH_EXYNOS - bool - help - This enables support for Samsung Exynos SoC family - -config ARCH_EXYNOS7 - bool "ARMv8 based Samsung Exynos7" - select ARCH_EXYNOS + bool "ARMv8 based Samsung Exynos SoC family" select COMMON_CLK_SAMSUNG select HAVE_S3C2410_WATCHDOG if WATCHDOG select HAVE_S3C_RTC if RTC_CLASS select PINCTRL select PINCTRL_EXYNOS - help - This enables support for Samsung Exynos7 SoC family + This enables support for ARMv8 based Samsung Exynos SoC family. config ARCH_LAYERSCAPE bool "ARMv8 based Freescale Layerscape SoC family" diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile index 20310e5b6d6f..50c9b9383cfa 100644 --- a/arch/arm64/boot/dts/exynos/Makefile +++ b/arch/arm64/boot/dts/exynos/Makefile @@ -1,4 +1,4 @@ -dtb-$(CONFIG_ARCH_EXYNOS7) += exynos7-espresso.dtb +dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb always := $(dtb-y) subdir-y := $(dts-dirs) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 18ca9fb9e65f..331a843cf122 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -33,7 +33,7 @@ CONFIG_MODULE_UNLOAD=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BERLIN=y -CONFIG_ARCH_EXYNOS7=y +CONFIG_ARCH_EXYNOS=y CONFIG_ARCH_LAYERSCAPE=y CONFIG_ARCH_HISI=y CONFIG_ARCH_MEDIATEK=y From a9c42f02387ce8a231bce7c0901ef15fe4bfc3b4 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 23 Feb 2016 21:28:36 +0900 Subject: [PATCH 38/48] arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support Signed-off-by: Yoshihiro Shimoda Signed-off-by: Simon Horman --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 86581f793e39..eaf738a59927 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -213,6 +213,7 @@ CONFIG_QCOM_SMD_RPM=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_HISILICON_IRQ_MBIGEN=y +CONFIG_PHY_RCAR_GEN3_USB2=y CONFIG_PHY_XGENE=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y From c966f0521db49f561d18820107654b0895c1c394 Mon Sep 17 00:00:00 2001 From: Kefeng Wang Date: Fri, 29 Jan 2016 16:39:06 +0800 Subject: [PATCH 39/48] arm64: defconfig: Enable DesignWare APB GPIO controller The Synopsys DesignWare APB GPIO controller is used by several vender's socs, like apm/marvell/altera/hisilicon, enable it by default. Signed-off-by: Kefeng Wang Signed-off-by: Wei Xu --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 18ca9fb9e65f..a5eb1b723e39 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -141,6 +141,7 @@ CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_SPI_QUP=y CONFIG_PINCTRL_MSM8916=y +CONFIG_GPIO_DWAPB=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_XGENE=y From 22b0898e831bc1ffb64ce0b8452a376f0892b478 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 22 Feb 2016 18:20:55 +0000 Subject: [PATCH 40/48] arm64: add defconfig options for Allwinner SoCs With the Allwinner platform now supported, enable it in the defconfig and add some options to give some decent out-of-the-box experience on those SoCs. Signed-off-by: Andre Przywara Signed-off-by: Maxime Ripard --- arch/arm64/configs/defconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 18ca9fb9e65f..7acadce74d4d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -31,6 +31,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_SUNXI=y CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BERLIN=y CONFIG_ARCH_EXYNOS7=y @@ -135,12 +136,15 @@ CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y CONFIG_VIRTIO_CONSOLE=y # CONFIG_HW_RANDOM is not set CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MV64XXX=y CONFIG_I2C_QUP=y CONFIG_I2C_RCAR=y CONFIG_SPI=y CONFIG_SPI_PL022=y CONFIG_SPI_QUP=y CONFIG_PINCTRL_MSM8916=y +CONFIG_GPIO_SYSFS=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_XGENE=y @@ -175,10 +179,12 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_TEGRA=y CONFIG_MMC_SPI=y +CONFIG_MMC_SUNXI=y CONFIG_MMC_DW=y CONFIG_MMC_DW_IDMAC=y CONFIG_MMC_DW_PLTFM=y CONFIG_MMC_DW_EXYNOS=y +CONFIG_MMC_BLOCK_MINORS=16 CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_SYSCON=y @@ -187,6 +193,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_EFI=y +CONFIG_RTC_DRV_SUN6I=y CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y CONFIG_RCAR_DMAC=y From 617fe7196d54e60eaa67f436848b7036d8d6e531 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Thu, 25 Feb 2016 09:04:09 +0530 Subject: [PATCH 41/48] arm64: defconfig: Enable exynos thermal config This patch enables Exynos thermal and related configs for the TMU found on Exynos7 SoC. This also enables thermal emulation mode to test trip points. Signed-off-by: Alim Akhtar Signed-off-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 18ca9fb9e65f..05c8ba5c9769 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -147,6 +147,9 @@ CONFIG_GPIO_XGENE=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y # CONFIG_HWMON is not set +CONFIG_THERMAL=y +CONFIG_THERMAL_EMULATION=y +CONFIG_EXYNOS_THERMAL=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_QCOM_SMD_RPM=y From e2f0abaf45bcdcf4408615d90a58730847304df7 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 25 Feb 2016 11:14:51 +0100 Subject: [PATCH 42/48] arm64: add Alpine SoC family This patch introduces ARCH_ALPINE to add the support of the Alpine SoC family for the arm64 architecture. Signed-off-by: Antoine Tenart Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 5938fd1b308d..6230a744fb0e 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -1,5 +1,11 @@ menu "Platform selection" +config ARCH_ALPINE + bool "Annapurna Labs Alpine platform" + help + This enables support for the Annapurna Labs Alpine + Soc family. + config ARCH_BCM_IPROC bool "Broadcom iProc SoC Family" help From 476cfc05f327d855ab98e7ba017f2cf04543de61 Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 25 Feb 2016 11:14:53 +0100 Subject: [PATCH 43/48] arm64: defconfig: enable the Alpine family Enable the Alpine SoC family in the arm64 defconfig. Signed-off-by: Antoine Tenart Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 774e51fda7fa..15cdb4734440 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -30,6 +30,7 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_IOSCHED_DEADLINE is not set +CONFIG_ARCH_ALPINE=y CONFIG_ARCH_BCM_IPROC=y CONFIG_ARCH_BERLIN=y CONFIG_ARCH_EXYNOS7=y From 93df6d16afbe54045f22c88a09ffa41436d6c68b Mon Sep 17 00:00:00 2001 From: Antoine Tenart Date: Thu, 25 Feb 2016 11:14:56 +0100 Subject: [PATCH 44/48] arm64: alpine: select the Alpine MSI controller driver Select the Alpine MSI controller driver when using an Alpine platform. Signed-off-by: Antoine Tenart Signed-off-by: Tsahee Zidenberg Signed-off-by: Arnd Bergmann --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6230a744fb0e..638dee72131b 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -2,6 +2,7 @@ menu "Platform selection" config ARCH_ALPINE bool "Annapurna Labs Alpine platform" + select ALPINE_MSI help This enables support for the Annapurna Labs Alpine Soc family. From 6bb8371893889ba877652107ae59eecb8d86edc4 Mon Sep 17 00:00:00 2001 From: Alim Akhtar Date: Fri, 5 Feb 2016 11:34:29 +0530 Subject: [PATCH 45/48] arm64: defconfig: Enable Samsung MFD and related configs Exynos7 based espresso board uses S2MPS15, a multifunction device. This patch enables S2MPS1X regulator, pmic-clk and rtc drivers utilized by the same. Signed-off-by: Alim Akhtar Reviewed-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Kozlowski --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 05c8ba5c9769..01168e656362 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -150,9 +150,11 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_EXYNOS_THERMAL=y +CONFIG_MFD_SEC_CORE=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_QCOM_SMD_RPM=y +CONFIG_REGULATOR_S2MPS11=y CONFIG_FB=y CONFIG_FB_ARMCLCD=y CONFIG_FRAMEBUFFER_CONSOLE=y @@ -189,6 +191,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_LEDS_TRIGGER_HEARTBEAT=y CONFIG_LEDS_TRIGGER_CPU=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_S5M=y CONFIG_RTC_DRV_EFI=y CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y From 451e9e54e259f1f223763e191393c47383674256 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 2 Mar 2016 03:34:56 +0100 Subject: [PATCH 46/48] ARM64: Enable Amlogic Meson GXBaby platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Provide the ARCH_MESON Kconfig symbol to allow enabling existing serial and i2c drivers. Signed-off-by: Andreas Färber Signed-off-by: Carlo Caione --- arch/arm64/Kconfig.platforms | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 21074f674bde..c900e1708d18 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -48,6 +48,11 @@ config ARCH_MEDIATEK help Support for Mediatek MT65xx & MT81xx ARMv8 SoCs +config ARCH_MESON + bool "Amlogic Platforms" + help + This enables support for the Amlogic S905 SoCs. + config ARCH_QCOM bool "Qualcomm Platforms" select PINCTRL From d1be05ab23a67876b7e6a64734fd617978fa6f0c Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 25 Feb 2016 12:46:31 +0200 Subject: [PATCH 47/48] arm64: defconfig: Add Qualcomm sdhci and restart functionality Enable sdhci and restart functionality for devices based on msm8916 platform. Signed-off-by: Georgi Djakov Signed-off-by: Olof Johansson --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b81cdf94c89d..542d22e609af 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -161,6 +161,7 @@ CONFIG_GPIO_DWAPB=y CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_XGENE=y +CONFIG_POWER_RESET_MSM=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y # CONFIG_HWMON is not set @@ -208,6 +209,7 @@ CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_TEGRA=y +CONFIG_MMC_SDHCI_MSM=y CONFIG_MMC_SPI=y CONFIG_MMC_SUNXI=y CONFIG_MMC_DW=y From 2f85bb09d95e27c2932fc86e41318962bd33af96 Mon Sep 17 00:00:00 2001 From: Georgi Djakov Date: Thu, 25 Feb 2016 12:46:32 +0200 Subject: [PATCH 48/48] arm64: defconfig: Increase MMC_BLOCK_MINORS to 16 Increase the block minors from the default 8 to 16. The db410c board by default has eMMC rootfs on the 10th partition. Signed-off-by: Georgi Djakov Signed-off-by: Olof Johansson --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 542d22e609af..872fa01499c3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -205,6 +205,7 @@ CONFIG_USB_MSM_OTG=y CONFIG_USB_ULPI=y CONFIG_USB_GADGET=y CONFIG_MMC=y +CONFIG_MMC_BLOCK_MINORS=16 CONFIG_MMC_ARMMMCI=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y