qed: Make qed_int_cau_conf_pi() static
Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1300,6 +1300,40 @@ void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
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SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
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SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
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}
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}
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static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u16 igu_sb_id,
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u32 pi_index,
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enum qed_coalescing_fsm coalescing_fsm,
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u8 timeset)
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{
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struct cau_pi_entry pi_entry;
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u32 sb_offset, pi_offset;
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if (IS_VF(p_hwfn->cdev))
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return;
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sb_offset = igu_sb_id * PIS_PER_SB;
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memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
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SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
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if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
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SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
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else
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SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
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pi_offset = sb_offset + pi_index;
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if (p_hwfn->hw_init_done) {
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qed_wr(p_hwfn, p_ptt,
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CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
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*((u32 *)&(pi_entry)));
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} else {
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STORE_RT_REG(p_hwfn,
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CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
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*((u32 *)&(pi_entry)));
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}
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}
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void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
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void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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struct qed_ptt *p_ptt,
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dma_addr_t sb_phys,
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dma_addr_t sb_phys,
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@ -1366,40 +1400,6 @@ void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
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}
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}
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}
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}
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void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u16 igu_sb_id,
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u32 pi_index,
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enum qed_coalescing_fsm coalescing_fsm,
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u8 timeset)
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{
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struct cau_pi_entry pi_entry;
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u32 sb_offset, pi_offset;
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if (IS_VF(p_hwfn->cdev))
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return;
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sb_offset = igu_sb_id * PIS_PER_SB;
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memset(&pi_entry, 0, sizeof(struct cau_pi_entry));
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SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
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if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
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SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0);
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else
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SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1);
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pi_offset = sb_offset + pi_index;
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if (p_hwfn->hw_init_done) {
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qed_wr(p_hwfn, p_ptt,
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CAU_REG_PI_MEMORY + pi_offset * sizeof(u32),
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*((u32 *)&(pi_entry)));
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} else {
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STORE_RT_REG(p_hwfn,
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CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
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*((u32 *)&(pi_entry)));
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}
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}
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void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
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void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
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struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
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{
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{
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@ -78,24 +78,6 @@ enum qed_coalescing_fsm {
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QED_COAL_TX_STATE_MACHINE
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QED_COAL_TX_STATE_MACHINE
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};
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};
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/**
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* @brief qed_int_cau_conf_pi - configure cau for a given
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* status block
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*
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* @param p_hwfn
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* @param p_ptt
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* @param igu_sb_id
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* @param pi_index
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* @param state
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* @param timeset
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*/
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void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
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struct qed_ptt *p_ptt,
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u16 igu_sb_id,
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u32 pi_index,
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enum qed_coalescing_fsm coalescing_fsm,
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u8 timeset);
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/**
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/**
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* @brief qed_int_igu_enable_int - enable device interrupts
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* @brief qed_int_igu_enable_int - enable device interrupts
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*
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*
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