hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

A lot display-controller nodes for DSI and the Analogix DP on rk3288 

as well as general display+hdmi support on rk3036. With the Analogix
 DP support, Veyron Chromeboks can now finally use their internal
 display.
 
 Other than this big improvement we have thermal support on the rk3228,
 a long time missing binding document for the General Register Files
 block, better operating points for Veyron devices and a bunch of fixes
 with parts stemming from warnings that new dtc version can generate.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJXDI8tAAoJEPOmecmc0R2BwksIAK/l/K03RwWzT20pc9UZIBPL
 YevlAXKFa7io9Wju0gfGJOQNo+UAUQh6Rhcuf/J3odiDl2URoHqu1xIR+KOKWZrO
 aD72VorCOcrPYck3BTyTLCtfG+zr8Q3t/i5f3ghitK5XdnW2MtE6SIjZ5x8Md+M8
 6D4svbgLIh16/kq1XzjcQkf5c7sf7xSABhZEE8Xb7CuPmeBe/j6ORMMuUqIA0rJi
 ZbW0+MyAiuAYD7vyQm/IiPk9nw12nnD+zjVg3Nz3YwmXYb4cNQfHdCJbjxezbw80
 R96VS4OdAlOZocETi5GljC97fdAtTSBJXOogeK1/pXQfbQFlkWeDYzsF9l/oJYI=
 =+WKk
 -----END PGP SIGNATURE-----

Merge tag 'v4.7-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

A lot display-controller nodes for DSI and the Analogix DP on rk3288
as well as general display+hdmi support on rk3036. With the Analogix
DP support, Veyron Chromeboks can now finally use their internal
display.

Other than this big improvement we have thermal support on the rk3228,
a long time missing binding document for the General Register Files
block, better operating points for Veyron devices and a bunch of fixes
with parts stemming from warnings that new dtc version can generate.

* tag 'v4.7-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (27 commits)
  ARM: dts: rockchip: move rk3036 memory definition to board files
  ARM: dts: rockchip: enable the eDP on rk3288 veyron devices
  ARM: dts: rockchip: simple panel and backlight supplies on veyron boards
  ARM: dts: rockchip: override edp hpd handling on veyron-pinky and speedy
  ARM: dts: rockchip: add rk3288-veyron-minnie backlight and panel settings
  ARM: dts: rockchip: add rk3288-veyron-jaq backlight and panel overrides
  ARM: dts: rockchip: add core rk3288-veyron backlight and panel nodes
  ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators
  ARM: dts: rockchip: move edp-hpd pin definition into common location
  ARM: dts: rockchip: add rk3288 displayport controller node
  ARM: dts: rockchip: add rk3288 edp-phy node
  ARM: dts: rockchip: add missing unitname to cpu_leakage efuse
  ARM: dts: rockchip: drop unneeded properties from mipi node
  ARM: dts: rockchip: clean up gpio-keys nodes
  ARM: dts: rockchip: fix missing usbphy unit-names
  ARM: dts: rockchip: fix rk3288 power-domain unit names
  ARM: dts: rockchip: update rk3288-veyron cpu operating points
  ARM: dts: rockchip: remove broken-cd from emmc and sdio
  ARM: dts: rockchip: enable the tsadc for rk3228 evb
  ARM: dts: rockchip: add the thermal main info found on rk3228
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2016-04-13 15:27:33 -07:00
parent ed53ecbea7 fbf15046f1
commit 8bd641ff01
23 changed files with 532 additions and 73 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
Documentation/devicetree/bindings/soc/rockchip/grf.txt Normal file
View File

@ -0,0 +1,35 @@
* Rockchip General Register Files (GRF)
The general register file will be used to do static set by software, which
is composed of many registers for system control.
From RK3368 SoCs, the GRF is divided into two sections,
- GRF, used for general non-secure system,
- PMUGRF, used for always on system
Required Properties:
- compatible: GRF should be one of the followings
- "rockchip,rk3066-grf", "syscon": for rk3066
- "rockchip,rk3188-grf", "syscon": for rk3188
- "rockchip,rk3228-grf", "syscon": for rk3228
- "rockchip,rk3288-grf", "syscon": for rk3288
- "rockchip,rk3368-grf", "syscon": for rk3368
- "rockchip,rk3399-grf", "syscon": for rk3399
- compatible: PMUGRF should be one of the followings
- "rockchip,rk3368-pmugrf", "syscon": for rk3368
- "rockchip,rk3399-pmugrf", "syscon": for rk3399
- reg: physical base address of the controller and length of memory mapped
region.
Example: GRF and PMUGRF of RK3399 SoCs
pmugrf: syscon@ff320000 {
compatible = "rockchip,rk3399-pmugrf", "syscon";
reg = <0x0 0xff320000 0x0 0x1000>;
};
grf: syscon@ff770000 {
compatible = "rockchip,rk3399-grf", "syscon";
reg = <0x0 0xff770000 0x0 0x10000>;
};

5
arch/arm/boot/dts/rk3036-evb.dts
View File

@ -45,6 +45,11 @@
/ {
model = "Rockchip RK3036 Evaluation board";
compatible = "rockchip,rk3036-evb", "rockchip,rk3036";
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
};
&emac {

18
arch/arm/boot/dts/rk3036-kylin.dts
View File

@ -46,6 +46,11 @@
model = "Rockchip RK3036 KylinBoard";
compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
memory {
device_type = "memory";
reg = <0x60000000 0x20000000>;
};
leds: gpio-leds {
compatible = "gpio-leds";
@ -130,6 +135,10 @@
status = "okay";
};
&hdmi {
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
@ -341,7 +350,6 @@
&sdio {
status = "okay";
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;
@ -385,6 +393,14 @@
status = "okay";
};
&vop {
status = "okay";
};
&vop_mmu {
status = "okay";
};
&pinctrl {
leds {
led_ctl: led-ctl {

71
arch/arm/boot/dts/rk3036.dtsi
View File

@ -63,11 +63,6 @@
spi = &spi;
};
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -119,6 +114,11 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
display-subsystem {
compatible = "rockchip,display-subsystem";
ports = <&vop_out>;
};
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
@ -149,6 +149,36 @@
};
};
vop: vop@10118000 {
compatible = "rockchip,rk3036-vop";
reg = <0x10118000 0x19c>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC>, <&cru SCLK_LCDC>, <&cru HCLK_LCDC>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
reset-names = "axi", "ahb", "dclk";
iommus = <&vop_mmu>;
status = "disabled";
vop_out: port {
#address-cells = <1>;
#size-cells = <0>;
vop_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
};
};
};
vop_mmu: iommu@10118300 {
compatible = "rockchip,iommu";
reg = <0x10118300 0x100>;
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vop_mmu";
#iommu-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@10139000 {
compatible = "arm,gic-400";
interrupt-controller;
@ -237,7 +267,6 @@
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
clock-frequency = <37500000>;
@ -297,6 +326,27 @@
status = "disabled";
};
hdmi: hdmi@20034000 {
compatible = "rockchip,rk3036-inno-hdmi";
reg = <0x20034000 0x4000>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_HDMI>;
clock-names = "pclk";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_ctl>;
status = "disabled";
hdmi_in: port {
#address-cells = <1>;
#size-cells = <0>;
hdmi_in_vop: endpoint@0 {
reg = <0>;
remote-endpoint = <&vop_out_hdmi>;
};
};
};
timer: timer@20044000 {
compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
@ -644,6 +694,15 @@
};
};
hdmi {
hdmi_ctl: hdmi-ctl {
rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>,
<1 9 RK_FUNC_1 &pcfg_pull_none>,
<1 10 RK_FUNC_1 &pcfg_pull_none>,
<1 11 RK_FUNC_1 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,

11
arch/arm/boot/dts/rk3066a-bqcurie2.dts
View File

@ -42,6 +42,7 @@
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3066a.dtsi"
/ {
@ -77,21 +78,19 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
power {
gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
linux,code = <116>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
wakeup-source;
debounce-interval = <100>;
};
button@1 {
volume-down {
gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
linux,code = <104>;
linux,code = <KEY_VOLUMEDOWN>;
label = "GPIO Key Vol-";
linux,input-type = <1>;
debounce-interval = <100>;

9
arch/arm/boot/dts/rk3066a-rayeager.dts
View File

@ -41,6 +41,7 @@
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3066a.dtsi"
/ {
@ -61,14 +62,12 @@
keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@0 {
power {
wakeup-source;
gpios = <&gpio6 2 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <116>;
linux,code = <KEY_POWER>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
};
@ -182,7 +181,6 @@
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
@ -348,7 +346,6 @@
};
&mmc1 {
broken-cd;
bus-width = <4>;
disable-wp;
non-removable;

6
arch/arm/boot/dts/rk3066a.dtsi
View File

@ -169,7 +169,7 @@
clocks = <&cru PCLK_EFUSE>;
clock-names = "pclk_efuse";
cpu_leakage: cpu_leakage {
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
};
@ -207,7 +207,7 @@
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy0 {
usbphy0: usb-phy@17c {
#phy-cells = <0>;
reg = <0x17c>;
clocks = <&cru SCLK_OTGPHY0>;
@ -215,7 +215,7 @@
#clock-cells = <0>;
};
usbphy1: usb-phy1 {
usbphy1: usb-phy@188 {
#phy-cells = <0>;
reg = <0x188>;
clocks = <&cru SCLK_OTGPHY1>;

7
arch/arm/boot/dts/rk3188-radxarock.dts
View File

@ -41,6 +41,7 @@
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3188.dtsi"
/ {
@ -54,13 +55,11 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
button@0 {
power {
gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
linux,code = <116>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
wakeup-source;

6
arch/arm/boot/dts/rk3188.dtsi
View File

@ -154,7 +154,7 @@
clocks = <&cru PCLK_EFUSE>;
clock-names = "pclk_efuse";
cpu_leakage: cpu_leakage {
cpu_leakage: cpu_leakage@17 {
reg = <0x17 0x1>;
};
};
@ -166,7 +166,7 @@
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy0 {
usbphy0: usb-phy@10c {
#phy-cells = <0>;
reg = <0x10c>;
clocks = <&cru SCLK_OTGPHY0>;
@ -174,7 +174,7 @@
#clock-cells = <0>;
};
usbphy1: usb-phy1 {
usbphy1: usb-phy@11c {
#phy-cells = <0>;
reg = <0x11c>;
clocks = <&cru SCLK_OTGPHY1>;

8
arch/arm/boot/dts/rk3228-evb.dts
View File

@ -53,7 +53,6 @@
};
&emmc {
broken-cd;
cap-mmc-highspeed;
mmc-ddr-1_8v;
disable-wp;
@ -61,6 +60,13 @@
status = "okay";
};
&tsadc {
status = "okay";
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
};
&uart2 {
status = "okay";
};

69
arch/arm/boot/dts/rk3228.dtsi
View File

@ -43,6 +43,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3228-cru.h>
#include <dt-bindings/thermal/thermal.h>
#include "skeleton.dtsi"
/ {
@ -69,6 +70,7 @@
/* KHz uV */
816000 1000000
>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <40000>;
clocks = <&cru ARMCLK>;
};
@ -247,6 +249,63 @@
assigned-clock-rates = <594000000>;
};
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <100>; /* milliseconds */
polling-delay = <5000>; /* milliseconds */
thermal-sensors = <&tsadc 0>;
trips {
cpu_alert0: cpu_alert0 {
temperature = <70000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_alert1: cpu_alert1 {
temperature = <75000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "passive";
};
cpu_crit: cpu_crit {
temperature = <90000>; /* millicelsius */
hysteresis = <2000>; /* millicelsius */
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 6>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
tsadc: tsadc@11150000 {
compatible = "rockchip,rk3228-tsadc";
reg = <0x11150000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
pinctrl-names = "init", "default", "sleep";
pinctrl-0 = <&otp_gpio>;
pinctrl-1 = <&otp_out>;
pinctrl-2 = <&otp_gpio>;
#thermal-sensor-cells = <0>;
rockchip,hw-tshut-temp = <95000>;
status = "disabled";
};
emmc: dwmmc@30020000 {
compatible = "rockchip,rk3288-dw-mshc";
reg = <0x30020000 0x4000>;
@ -394,6 +453,16 @@
};
};
tsadc {
otp_gpio: otp-gpio {
rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
};
otp_out: otp-out {
rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
};
};
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,

8
arch/arm/boot/dts/rk3288-evb.dtsi
View File

@ -38,6 +38,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3288.dtsi"
@ -98,16 +99,14 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
button@0 {
power {
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
wakeup-source;
@ -172,7 +171,6 @@
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;

9
arch/arm/boot/dts/rk3288-firefly.dtsi
View File

@ -40,6 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include <dt-bindings/input/input.h>
#include "rk3288.dtsi"
/ {
@ -87,14 +88,12 @@
keys: gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
button@0 {
power {
wakeup-source;
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
label = "GPIO Power";
linux,code = <116>;
linux,code = <KEY_POWER>;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
};
@ -208,7 +207,6 @@
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;
@ -509,7 +507,6 @@
};
&sdio0 {
broken-cd;
bus-width = <4>;
disable-wp;
non-removable;

9
arch/arm/boot/dts/rk3288-popmetal.dts
View File

@ -41,7 +41,7 @@
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include "rk3288.dtsi"
/ {
@ -62,16 +62,14 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
button@0 {
power {
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
wakeup-source;
@ -162,7 +160,6 @@
};
&emmc {
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
disable-wp;

7
arch/arm/boot/dts/rk3288-r89.dts
View File

@ -41,6 +41,7 @@
*/
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/pwm/pwm.h>
#include "rk3288.dtsi"
@ -61,16 +62,14 @@
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwrbtn>;
button@0 {
power {
gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
linux,code = <116>;
linux,code = <KEY_POWER>;
label = "GPIO Key Power";
linux,input-type = <1>;
wakeup-source;

100
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
View File

@ -54,6 +54,50 @@
i2c20 = &i2c_tunnel;
};
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <128>;
enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
backlight-boot-off;
pinctrl-names = "default";
pinctrl-0 = <&bl_en>;
pwms = <&pwm0 0 1000000 0>;
pwm-delay-us = <10000>;
};
gpio-charger {
compatible = "gpio-charger";
charger-type = "mains";
@ -62,6 +106,21 @@
pinctrl-0 = <&ac_present_ap>;
};
panel: panel {
compatible ="innolux,n116bge", "simple-panel";
status = "okay";
power-supply = <&vcc33_lcd>;
backlight = <&backlight>;
ports {
panel_in: port {
panel_in_edp: endpoint {
remote-endpoint = <&edp_out_panel>;
};
};
};
};
/* A non-regulated voltage from power supply or battery */
vccsys: vccsys {
compatible = "regulator-fixed";
@ -103,6 +162,29 @@
};
};
&edp {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&edp_hpd>;
ports {
edp_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
edp_out_panel: endpoint {
reg = <0>;
remote-endpoint = <&panel_in_edp>;
};
};
};
};
&edp_phy {
status = "okay";
};
&gpio_keys {
pinctrl-0 = <&pwr_key_l &ap_lid_int_l>;
lid {
@ -115,6 +197,10 @@
};
};
&pwm0 {
status = "okay";
};
&rk808 {
vcc11-supply = <&vcc_5v>;
@ -168,6 +254,14 @@
};
};
&vopl {
status = "okay";
};
&vopl_mmu {
status = "okay";
};
&pinctrl {
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
@ -184,6 +278,12 @@
&suspend_l_sleep
>;
backlight {
bl_en: bl-en {
rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
buttons {
ap_lid_int_l: ap-lid-int-l {
rockchip,pins = <0 6 RK_FUNC_GPIO &pcfg_pull_up>;

49
arch/arm/boot/dts/rk3288-veyron-jaq.dts
View File

@ -61,6 +61,7 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
@ -88,6 +89,48 @@
};
};
&backlight {
/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
brightness-levels = <
0
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
power-supply = <&backlight_regulator>;
};
&panel {
power-supply = <&panel_regulator>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
@ -142,12 +185,6 @@
};
};
edp {
edp_hpd: edp_hpd {
rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
};
};
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;

9
arch/arm/boot/dts/rk3288-veyron-jerry.dts
View File

@ -60,6 +60,7 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
@ -87,6 +88,14 @@
};
};
&backlight {
power-supply = <&backlight_regulator>;
};
&panel {
power-supply= <&panel_regulator>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;

44
arch/arm/boot/dts/rk3288-veyron-minnie.dts
View File

@ -70,6 +70,7 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
@ -86,6 +87,44 @@
};
};
&backlight {
/* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
brightness-levels = <
0 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
power-supply = <&backlight_regulator>;
};
&emmc {
/delete-property/mmc-hs200-1_8v;
};
@ -135,6 +174,11 @@
};
};
&panel {
compatible = "auo,b101ean01", "simple-panel";
power-supply= <&panel_regulator>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;

7
arch/arm/boot/dts/rk3288-veyron-pinky.dts
View File

@ -65,6 +65,13 @@
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8 &emmc_reset>;
};
&edp {
/delete-property/pinctrl-names;
/delete-property/pinctrl-0;
force-hpd;
};
&gpio_keys {
pinctrl-0 = <&pwr_key_h &ap_lid_int_l>;

16
arch/arm/boot/dts/rk3288-veyron-speedy.dts
View File

@ -61,6 +61,7 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_enable_h>;
regulator-name = "panel_regulator";
startup-delay-us = <100000>;
vin-supply = <&vcc33_sys>;
};
@ -88,6 +89,10 @@
};
};
&backlight {
power-supply = <&backlight_regulator>;
};
&cpu_alert0 {
temperature = <65000>;
};
@ -96,6 +101,17 @@
temperature = <70000>;
};
&edp {
/delete-property/pinctrl-names;
/delete-property/pinctrl-0;
force-hpd;
};
&panel {
power-supply= <&panel_regulator>;
};
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;

18
arch/arm/boot/dts/rk3288-veyron.dtsi
View File

@ -141,12 +141,27 @@
&cpu0 {
cpu0-supply = <&vdd_cpu>;
operating-points = <
/* KHz uV */
1800000 1400000
1704000 1350000
1608000 1300000
1512000 1250000
1416000 1200000
1200000 1100000
1008000 1050000
816000 1000000
696000 950000
600000 900000
408000 900000
216000 900000
126000 900000
>;
};
&emmc {
status = "okay";
broken-cd;
bus-width = <8>;
cap-mmc-highspeed;
rockchip,default-sample-phase = <158>;
@ -347,7 +362,6 @@
&sdio0 {
status = "okay";
broken-cd;
bus-width = <4>;
cap-sd-highspeed;
cap-sdio-irq;

84
arch/arm/boot/dts/rk3288.dtsi
View File

@ -201,6 +201,15 @@
#clock-cells = <0>;
};
edp_phy: edp-phy {
compatible = "rockchip,rk3288-dp-phy";
clocks = <&cru SCLK_EDP_24M>;
clock-names = "24m";
rockchip,grf = <&grf>;
#phy-cells = <0>;
status = "disabled";
};
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
@ -659,7 +668,7 @@
* *_HDMI HDMI
* *_MIPI_* MIPI
*/
pd_vio {
pd_vio@RK3288_PD_VIO {
reg = <RK3288_PD_VIO>;
clocks = <&cru ACLK_IEP>,
<&cru ACLK_ISP>,
@ -692,7 +701,7 @@
* Note: The following 3 are HEVC(H.265) clocks,
* and on the ACLK_HEVC_NIU (NOC).
*/
pd_hevc {
pd_hevc@RK3288_PD_HEVC {
reg = <RK3288_PD_HEVC>;
clocks = <&cru ACLK_HEVC>,
<&cru SCLK_HEVC_CABAC>,
@ -704,7 +713,7 @@
* (video endecoder & decoder) clocks that on the
* ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
*/
pd_video {
pd_video@RK3288_PD_VIDEO {
reg = <RK3288_PD_VIDEO>;
clocks = <&cru ACLK_VCODEC>,
<&cru HCLK_VCODEC>;
@ -714,7 +723,7 @@
* Note: ACLK_GPU is the GPU clock,
* and on the ACLK_GPU_NIU (NOC).
*/
pd_gpu {
pd_gpu@RK3288_PD_GPU {
reg = <RK3288_PD_GPU>;
clocks = <&cru ACLK_GPU>;
};
@ -765,7 +774,7 @@
clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
dmas = <&dmac_bus_s 3>;
dma-names = "tx";
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&spdif_tx>;
rockchip,grf = <&grf>;
@ -775,7 +784,7 @@
i2s: i2s@ff890000 {
compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
reg = <0xff890000 0x10000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
@ -821,6 +830,12 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopb>;
};
vopb_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopb>;
};
vopb_out_mipi: endpoint@2 {
reg = <2>;
remote-endpoint = <&mipi_in_vopb>;
@ -858,6 +873,12 @@
reg = <0>;
remote-endpoint = <&hdmi_in_vopl>;
};
vopl_out_edp: endpoint@1 {
reg = <1>;
remote-endpoint = <&edp_in_vopl>;
};
vopl_out_mipi: endpoint@2 {
reg = <2>;
remote-endpoint = <&mipi_in_vopl>;
@ -878,19 +899,16 @@
mipi_dsi: mipi@ff960000 {
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
reg = <0xff960000 0x4000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
clock-names = "ref", "pclk";
power-domains = <&power RK3288_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
mipi_in: port {
#address-cells = <1>;
#size-cells = <0>;
@ -906,6 +924,38 @@
};
};
edp: dp@ff970000 {
compatible = "rockchip,rk3288-dp";
reg = <0xff970000 0x4000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
clock-names = "dp", "pclk";
phys = <&edp_phy>;
phy-names = "dp";
resets = <&cru SRST_EDP>;
reset-names = "dp";
rockchip,grf = <&grf>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
edp_in: port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
edp_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_edp>;
};
edp_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_edp>;
};
};
};
};
hdmi: hdmi@ff980000 {
compatible = "rockchip,rk3288-dw-hdmi";
reg = <0xff980000 0x20000>;
@ -966,7 +1016,7 @@
#size-cells = <0>;
status = "disabled";
usbphy0: usb-phy0 {
usbphy0: usb-phy@320 {
#phy-cells = <0>;
reg = <0x320>;
clocks = <&cru SCLK_OTGPHY0>;
@ -974,7 +1024,7 @@
#clock-cells = <0>;
};
usbphy1: usb-phy1 {
usbphy1: usb-phy@334 {
#phy-cells = <0>;
reg = <0x334>;
clocks = <&cru SCLK_OTGPHY1>;
@ -982,7 +1032,7 @@
#clock-cells = <0>;
};
usbphy2: usb-phy2 {
usbphy2: usb-phy@348 {
#phy-cells = <0>;
reg = <0x348>;
clocks = <&cru SCLK_OTGPHY2>;
@ -1158,6 +1208,12 @@
};
};
edp {
edp_hpd: edp-hpd {
rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
};
};
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,