ath9k_htc: add new WMI_REG_RMW_CMDID command
Since usb bus add extra delay on each request, a command with read + write requests is too expensive. We can dramtically reduce usb load by moving this command to firmware. In my tests, this patch will reduce channel scan time for about 5-10 seconds. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
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@ -131,6 +131,9 @@ struct ath_ops {
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void (*enable_write_buffer)(void *);
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void (*write_flush) (void *);
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u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
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void (*enable_rmw_buffer)(void *);
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void (*rmw_flush) (void *);
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};
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struct ath_common;
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@ -444,6 +444,10 @@ static inline void ath9k_htc_stop_btcoex(struct ath9k_htc_priv *priv)
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#define OP_BT_SCAN BIT(4)
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#define OP_TSF_RESET BIT(6)
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enum htc_op_flags {
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HTC_FWFLAG_NO_RMW,
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};
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struct ath9k_htc_priv {
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struct device *dev;
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struct ieee80211_hw *hw;
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@ -482,6 +486,7 @@ struct ath9k_htc_priv {
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bool reconfig_beacon;
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unsigned int rxfilter;
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unsigned long op_flags;
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unsigned long fw_flags;
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struct ath9k_hw_cal_data caldata;
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struct ath_spec_scan_priv spec_priv;
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@ -376,15 +376,137 @@ static void ath9k_regwrite_flush(void *hw_priv)
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mutex_unlock(&priv->wmi->multi_write_mutex);
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}
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static void ath9k_reg_rmw_buffer(void *hw_priv,
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u32 reg_offset, u32 set, u32 clr)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
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u32 rsp_status;
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int r;
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mutex_lock(&priv->wmi->multi_rmw_mutex);
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/* Store the register/value */
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priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].reg =
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cpu_to_be32(reg_offset);
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priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].set =
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cpu_to_be32(set);
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priv->wmi->multi_rmw[priv->wmi->multi_rmw_idx].clr =
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cpu_to_be32(clr);
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priv->wmi->multi_rmw_idx++;
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/* If the buffer is full, send it out. */
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if (priv->wmi->multi_rmw_idx == MAX_RMW_CMD_NUMBER) {
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r = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
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(u8 *) &priv->wmi->multi_rmw,
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sizeof(struct register_write) * priv->wmi->multi_rmw_idx,
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(u8 *) &rsp_status, sizeof(rsp_status),
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100);
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if (unlikely(r)) {
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ath_dbg(common, WMI,
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"REGISTER RMW FAILED, multi len: %d\n",
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priv->wmi->multi_rmw_idx);
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}
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priv->wmi->multi_rmw_idx = 0;
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}
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mutex_unlock(&priv->wmi->multi_rmw_mutex);
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}
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static void ath9k_reg_rmw_flush(void *hw_priv)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
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u32 rsp_status;
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int r;
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if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags))
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return;
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atomic_dec(&priv->wmi->m_rmw_cnt);
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mutex_lock(&priv->wmi->multi_rmw_mutex);
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if (priv->wmi->multi_rmw_idx) {
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r = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
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(u8 *) &priv->wmi->multi_rmw,
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sizeof(struct register_rmw) * priv->wmi->multi_rmw_idx,
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(u8 *) &rsp_status, sizeof(rsp_status),
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100);
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if (unlikely(r)) {
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ath_dbg(common, WMI,
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"REGISTER RMW FAILED, multi len: %d\n",
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priv->wmi->multi_rmw_idx);
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}
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priv->wmi->multi_rmw_idx = 0;
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}
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mutex_unlock(&priv->wmi->multi_rmw_mutex);
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}
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static void ath9k_enable_rmw_buffer(void *hw_priv)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
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if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags))
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return;
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atomic_inc(&priv->wmi->m_rmw_cnt);
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}
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static u32 ath9k_reg_rmw_single(void *hw_priv,
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u32 reg_offset, u32 set, u32 clr)
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{
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
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struct register_rmw buf, buf_ret;
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int ret;
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u32 val = 0;
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buf.reg = cpu_to_be32(reg_offset);
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buf.set = cpu_to_be32(set);
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buf.clr = cpu_to_be32(clr);
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ret = ath9k_wmi_cmd(priv->wmi, WMI_REG_RMW_CMDID,
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(u8 *) &buf, sizeof(buf),
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(u8 *) &buf_ret, sizeof(buf_ret),
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100);
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if (unlikely(ret)) {
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ath_dbg(common, WMI, "REGISTER RMW FAILED:(0x%04x, %d)\n",
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reg_offset, ret);
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}
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return val;
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}
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static u32 ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
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{
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u32 val;
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struct ath_hw *ah = (struct ath_hw *) hw_priv;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv;
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val = ath9k_regread(hw_priv, reg_offset);
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val &= ~clr;
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val |= set;
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ath9k_regwrite(hw_priv, val, reg_offset);
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return val;
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if (test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags)) {
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u32 val;
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val = REG_READ(ah, reg_offset);
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val &= ~clr;
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val |= set;
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REG_WRITE(ah, reg_offset, val);
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return 0;
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}
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if (atomic_read(&priv->wmi->m_rmw_cnt))
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ath9k_reg_rmw_buffer(hw_priv, reg_offset, set, clr);
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else
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ath9k_reg_rmw_single(hw_priv, reg_offset, set, clr);
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return 0;
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}
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static void ath_usb_read_cachesize(struct ath_common *common, int *csz)
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@ -501,6 +623,8 @@ static int ath9k_init_priv(struct ath9k_htc_priv *priv,
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ah->reg_ops.write = ath9k_regwrite;
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ah->reg_ops.enable_write_buffer = ath9k_enable_regwrite_buffer;
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ah->reg_ops.write_flush = ath9k_regwrite_flush;
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ah->reg_ops.enable_rmw_buffer = ath9k_enable_rmw_buffer;
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ah->reg_ops.rmw_flush = ath9k_reg_rmw_flush;
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ah->reg_ops.rmw = ath9k_reg_rmw;
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priv->ah = ah;
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@ -686,6 +810,12 @@ static int ath9k_init_firmware_version(struct ath9k_htc_priv *priv)
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return -EINVAL;
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}
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if (priv->fw_version_major == 1 && priv->fw_version_minor < 4)
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set_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags);
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dev_info(priv->dev, "FW RMW support: %s\n",
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test_bit(HTC_FWFLAG_NO_RMW, &priv->fw_flags) ? "Off" : "On");
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return 0;
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}
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@ -100,6 +100,18 @@
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(_ah)->reg_ops.write_flush((_ah)); \
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} while (0)
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#define ENABLE_REG_RMW_BUFFER(_ah) \
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do { \
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if ((_ah)->reg_ops.enable_rmw_buffer) \
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(_ah)->reg_ops.enable_rmw_buffer((_ah)); \
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} while (0)
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#define REG_RMW_BUFFER_FLUSH(_ah) \
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do { \
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if ((_ah)->reg_ops.rmw_flush) \
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(_ah)->reg_ops.rmw_flush((_ah)); \
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} while (0)
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#define PR_EEP(_s, _val) \
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do { \
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len += scnprintf(buf + len, size - len, "%20s : %10d\n",\
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@ -61,6 +61,8 @@ static const char *wmi_cmd_to_name(enum wmi_cmd_id wmi_cmd)
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return "WMI_REG_READ_CMDID";
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case WMI_REG_WRITE_CMDID:
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return "WMI_REG_WRITE_CMDID";
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case WMI_REG_RMW_CMDID:
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return "WMI_REG_RMW_CMDID";
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case WMI_RC_STATE_CHANGE_CMDID:
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return "WMI_RC_STATE_CHANGE_CMDID";
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case WMI_RC_RATE_UPDATE_CMDID:
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spin_lock_init(&wmi->event_lock);
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mutex_init(&wmi->op_mutex);
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mutex_init(&wmi->multi_write_mutex);
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mutex_init(&wmi->multi_rmw_mutex);
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init_completion(&wmi->cmd_wait);
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INIT_LIST_HEAD(&wmi->pending_tx_events);
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tasklet_init(&wmi->wmi_event_tasklet, ath9k_wmi_event_tasklet,
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@ -112,6 +112,7 @@ enum wmi_cmd_id {
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WMI_TX_STATS_CMDID,
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WMI_RX_STATS_CMDID,
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WMI_BITRATE_MASK_CMDID,
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WMI_REG_RMW_CMDID,
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};
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enum wmi_event_id {
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};
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#define MAX_CMD_NUMBER 62
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#define MAX_RMW_CMD_NUMBER 15
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struct register_write {
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__be32 reg;
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__be32 val;
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};
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struct register_rmw {
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__be32 reg;
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__be32 set;
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__be32 clr;
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} __packed;
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struct ath9k_htc_tx_event {
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int count;
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struct __wmi_event_txstatus txs;
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spinlock_t wmi_lock;
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/* multi write section */
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atomic_t mwrite_cnt;
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struct register_write multi_write[MAX_CMD_NUMBER];
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u32 multi_write_idx;
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struct mutex multi_write_mutex;
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/* multi rmw section */
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atomic_t m_rmw_cnt;
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struct register_rmw multi_rmw[MAX_RMW_CMD_NUMBER];
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u32 multi_rmw_idx;
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struct mutex multi_rmw_mutex;
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};
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struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv);
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