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[CPUFREQ] speedstep-centrino should ignore upper performance control bits 

On some systems there could be bits set in the upper half of
the control value provided by the _PSS object.  These bits are
only relevant for cpufreq drivers that use IO ports which are not
currently supported by the speedstep-centrino driver.  The current
MSR oriented code assumes that upper bits are not set and thus
fails to work correctly when they are.  e.g. the control and status
value equality check failed on the IBM x3650 even though the ACPI
spec allows inequality.

Signed-off-by: Gary Hade <garyhade@us.ibm.com>
Signed-off-by: Dave Jones <davej@redhat.com>
This commit is contained in:
Gary Hade 2006-11-10 11:20:47 -08:00 committed by Dave Jones
parent 55e337345d
commit 8b9c6671f8
1 changed files with 5 additions and 3 deletions
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8
arch/i386/kernel/cpu/cpufreq/speedstep-centrino.c
View File

@ -36,6 +36,7 @@
#define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "speedstep-centrino", msg)
#define INTEL_MSR_RANGE (0xffff)
struct cpu_id
{
@ -463,8 +464,9 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
}
for (i=0; i<p->state_count; i++) {
if (p->states[i].control != p->states[i].status) {
dprintk("Different control (%llu) and status values (%llu)\n",
if ((p->states[i].control & INTEL_MSR_RANGE) !=
(p->states[i].status & INTEL_MSR_RANGE)) {
dprintk("Different MSR bits in control (%llu) and status (%llu)\n",
p->states[i].control, p->states[i].status);
result = -EINVAL;
goto err_unreg;
@ -500,7 +502,7 @@ static int centrino_cpu_init_acpi(struct cpufreq_policy *policy)
}
for (i=0; i<p->state_count; i++) {
centrino_model[cpu]->op_points[i].index = p->states[i].control;
centrino_model[cpu]->op_points[i].index = p->states[i].control & INTEL_MSR_RANGE;
centrino_model[cpu]->op_points[i].frequency = p->states[i].core_frequency * 1000;
dprintk("adding state %i with frequency %u and control value %04x\n",
i, centrino_model[cpu]->op_points[i].frequency, centrino_model[cpu]->op_points[i].index);