ARM: entry: prefetch abort helper: pass aborted pc in r4 rather than r0

This avoids unnecessary instructions for CPUs which implement the IFAR
(instruction fault address register).

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Russell King 2011-06-25 19:25:02 +01:00
parent b059bdc393
commit 8b4186160b
4 changed files with 6 additions and 4 deletions

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@ -45,7 +45,7 @@
.endm
.macro pabt_helper
mov r0, r4 @ pass address of aborted instruction.
@ PABORT handler takes fault address in r4
#ifdef MULTI_PABORT
ldr ip, .LCprocfns
mov lr, pc

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@ -4,7 +4,7 @@
/*
* Function: legacy_pabort
*
* Params : r0 = address of aborted instruction
* Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = Simulated IFSR with section translation fault status
@ -14,6 +14,7 @@
.align 5
ENTRY(legacy_pabort)
mov r0, r4
mov r1, #5
mov pc, lr
ENDPROC(legacy_pabort)

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@ -4,7 +4,7 @@
/*
* Function: v6_pabort
*
* Params : r0 = address of aborted instruction
* Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR
@ -14,6 +14,7 @@
.align 5
ENTRY(v6_pabort)
mov r0, r4
mrc p15, 0, r1, c5, c0, 1 @ get IFSR
mov pc, lr
ENDPROC(v6_pabort)

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@ -4,7 +4,7 @@
/*
* Function: v6_pabort
*
* Params : r0 = address of aborted instruction
* Params : r4 = address of aborted instruction
*
* Returns : r0 = address of abort
* : r1 = IFSR