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drm/radeon: fill in GPU init for Hainan (v2) 

v2: fix gb_addr_config value

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2012-07-31 12:42:48 -04:00
parent b5d9d72624
commit 8b02859d77
2 changed files with 20 additions and 1 deletions
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20
drivers/gpu/drm/radeon/si.c
View File

@ -2003,7 +2003,8 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
}
} else if ((rdev->family == CHIP_VERDE) ||
(rdev->family == CHIP_OLAND)) {
(rdev->family == CHIP_OLAND) ||
(rdev->family == CHIP_HAINAN)) {
for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
switch (reg_offset) {
case 0: /* non-AA compressed depth or any compressed stencil */
@ -2466,6 +2467,23 @@ static void si_gpu_init(struct radeon_device *rdev)
rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
break;
case CHIP_HAINAN:
rdev->config.si.max_shader_engines = 1;
rdev->config.si.max_tile_pipes = 4;
rdev->config.si.max_cu_per_sh = 5;
rdev->config.si.max_sh_per_se = 1;
rdev->config.si.max_backends_per_se = 1;
rdev->config.si.max_texture_channel_caches = 2;
rdev->config.si.max_gprs = 256;
rdev->config.si.max_gs_threads = 16;
rdev->config.si.max_hw_contexts = 8;
rdev->config.si.sc_prim_fifo_size_frontend = 0x20;
rdev->config.si.sc_prim_fifo_size_backend = 0x40;
rdev->config.si.sc_hiz_tile_fifo_size = 0x30;
rdev->config.si.sc_earlyz_tile_fifo_size = 0x130;
gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
break;
}
/* Initialize HDP */

1
drivers/gpu/drm/radeon/sid.h
View File

@ -28,6 +28,7 @@
#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002
#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001
/* discrete uvd clocks */
#define CG_UPLL_FUNC_CNTL 0x634