Merge branch 'pci/enumeration'
- Fix pci_register_host_bridge() device_register() error handling (Rob
Herring)
- Fix pci_host_bridge struct device release/free handling (Rob Herring)
- Program MPS for RCiEP devices (Ashok Raj)
- Inherit PTM settings from Switch Upstream Port so we can enable PTM on
Endpoints (Bjorn Helgaas)
- Add #defines for bridge windows (PCI_BRIDGE_IO_WINDOW,
PCI_BRIDGE_MEM_WINDOW, etc) (Krzysztof Wilczynski)
* pci/enumeration:
pcmcia: Use CardBus window names (PCI_CB_BRIDGE_IO_0_WINDOW etc) when freeing
PCI: Use bridge window names (PCI_BRIDGE_IO_WINDOW etc)
PCI/PTM: Inherit Switch Downstream Port PTM settings from Upstream Port
PCI: Program MPS for RCiEP devices
PCI: Fix pci_host_bridge struct device release/free handling
PCI: Fix pci_register_host_bridge() device_register() error handling
This commit is contained in:
Bjorn Helgaas
commit
8ab064e931
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@ -39,10 +39,6 @@ void pci_ptm_init(struct pci_dev *dev)
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if (!pci_is_pcie(dev))
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return;
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
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if (!pos)
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return;
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/*
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* Enable PTM only on interior devices (root ports, switch ports,
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* etc.) on the assumption that it causes no link traffic until an
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@ -52,6 +48,23 @@ void pci_ptm_init(struct pci_dev *dev)
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pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
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return;
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/*
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* Switch Downstream Ports are not permitted to have a PTM
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* capability; their PTM behavior is controlled by the Upstream
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* Port (PCIe r5.0, sec 7.9.16).
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*/
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ups = pci_upstream_bridge(dev);
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM &&
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ups && ups->ptm_enabled) {
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dev->ptm_granularity = ups->ptm_granularity;
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dev->ptm_enabled = 1;
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return;
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}
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
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if (!pos)
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return;
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pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
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local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
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@ -61,7 +74,6 @@ void pci_ptm_init(struct pci_dev *dev)
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* the spec recommendation (PCIe r3.1, sec 7.32.3), select the
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* furthest upstream Time Source as the PTM Root.
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*/
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ups = pci_upstream_bridge(dev);
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if (ups && ups->ptm_enabled) {
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ctrl = PCI_PTM_CTRL_ENABLE;
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if (ups->ptm_granularity == 0)
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@ -565,7 +565,7 @@ static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
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return b;
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}
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static void devm_pci_release_host_bridge_dev(struct device *dev)
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static void pci_release_host_bridge_dev(struct device *dev)
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{
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struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
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@ -574,12 +574,7 @@ static void devm_pci_release_host_bridge_dev(struct device *dev)
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pci_free_resource_list(&bridge->windows);
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pci_free_resource_list(&bridge->dma_ranges);
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}
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static void pci_release_host_bridge_dev(struct device *dev)
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{
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devm_pci_release_host_bridge_dev(dev);
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kfree(to_pci_host_bridge(dev));
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kfree(bridge);
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}
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static void pci_init_host_bridge(struct pci_host_bridge *bridge)
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@ -599,6 +594,8 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
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bridge->native_pme = 1;
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bridge->native_ltr = 1;
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bridge->native_dpc = 1;
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device_initialize(&bridge->dev);
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}
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struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
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@ -616,17 +613,25 @@ struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
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}
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EXPORT_SYMBOL(pci_alloc_host_bridge);
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static void devm_pci_alloc_host_bridge_release(void *data)
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{
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pci_free_host_bridge(data);
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}
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struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
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size_t priv)
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{
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int ret;
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struct pci_host_bridge *bridge;
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bridge = devm_kzalloc(dev, sizeof(*bridge) + priv, GFP_KERNEL);
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bridge = pci_alloc_host_bridge(priv);
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if (!bridge)
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return NULL;
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pci_init_host_bridge(bridge);
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bridge->dev.release = devm_pci_release_host_bridge_dev;
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ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
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bridge);
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if (ret)
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return NULL;
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return bridge;
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}
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@ -634,10 +639,7 @@ EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
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void pci_free_host_bridge(struct pci_host_bridge *bridge)
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{
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pci_free_resource_list(&bridge->windows);
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pci_free_resource_list(&bridge->dma_ranges);
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kfree(bridge);
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put_device(&bridge->dev);
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}
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EXPORT_SYMBOL(pci_free_host_bridge);
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@ -908,10 +910,11 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
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if (err)
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goto free;
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err = device_register(&bridge->dev);
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if (err)
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err = device_add(&bridge->dev);
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if (err) {
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put_device(&bridge->dev);
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goto free;
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}
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bus->bridge = get_device(&bridge->dev);
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device_enable_async_suspend(bus->bridge);
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pci_set_bus_of_node(bus);
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@ -977,7 +980,7 @@ static int pci_register_host_bridge(struct pci_host_bridge *bridge)
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unregister:
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put_device(&bridge->dev);
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device_unregister(&bridge->dev);
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device_del(&bridge->dev);
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free:
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kfree(bus);
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@ -1934,13 +1937,33 @@ static void pci_configure_mps(struct pci_dev *dev)
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struct pci_dev *bridge = pci_upstream_bridge(dev);
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int mps, mpss, p_mps, rc;
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if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
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if (!pci_is_pcie(dev))
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return;
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/* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
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if (dev->is_virtfn)
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return;
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/*
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* For Root Complex Integrated Endpoints, program the maximum
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* supported value unless limited by the PCIE_BUS_PEER2PEER case.
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*/
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if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
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if (pcie_bus_config == PCIE_BUS_PEER2PEER)
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mps = 128;
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else
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mps = 128 << dev->pcie_mpss;
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rc = pcie_set_mps(dev, mps);
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if (rc) {
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pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
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mps);
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}
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return;
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}
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if (!bridge || !pci_is_pcie(bridge))
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return;
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mps = pcie_get_mps(dev);
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p_mps = pcie_get_mps(bridge);
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@ -2952,7 +2975,7 @@ struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
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return bridge->bus;
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err_out:
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kfree(bridge);
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put_device(&bridge->dev);
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return NULL;
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}
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EXPORT_SYMBOL_GPL(pci_create_root_bus);
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@ -160,6 +160,6 @@ void pci_remove_root_bus(struct pci_bus *bus)
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host_bridge->bus = NULL;
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/* remove the host bridge */
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device_unregister(&host_bridge->dev);
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device_del(&host_bridge->dev);
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}
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EXPORT_SYMBOL_GPL(pci_remove_root_bus);
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@ -583,7 +583,7 @@ static void pci_setup_bridge_io(struct pci_dev *bridge)
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io_mask = PCI_IO_1K_RANGE_MASK;
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/* Set up the top and bottom of the PCI I/O segment for this bus */
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res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
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res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
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pcibios_resource_to_bus(bridge->bus, ®ion, res);
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if (res->flags & IORESOURCE_IO) {
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pci_read_config_word(bridge, PCI_IO_BASE, &l);
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@ -613,7 +613,7 @@ static void pci_setup_bridge_mmio(struct pci_dev *bridge)
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u32 l;
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/* Set up the top and bottom of the PCI Memory segment for this bus */
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res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
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res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
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pcibios_resource_to_bus(bridge->bus, ®ion, res);
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if (res->flags & IORESOURCE_MEM) {
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l = (region.start >> 16) & 0xfff0;
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@ -640,7 +640,7 @@ static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
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/* Set up PREF base/limit */
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bu = lu = 0;
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res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
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res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
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pcibios_resource_to_bus(bridge->bus, ®ion, res);
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if (res->flags & IORESOURCE_PREFETCH) {
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l = (region.start >> 16) & 0xfff0;
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@ -707,14 +707,14 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
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if (!pci_bus_clip_resource(bridge, i))
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return -EINVAL; /* Clipping didn't change anything */
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switch (i - PCI_BRIDGE_RESOURCES) {
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case 0:
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switch (i) {
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case PCI_BRIDGE_IO_WINDOW:
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pci_setup_bridge_io(bridge);
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break;
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case 1:
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case PCI_BRIDGE_MEM_WINDOW:
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pci_setup_bridge_mmio(bridge);
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break;
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case 2:
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case PCI_BRIDGE_PREF_MEM_WINDOW:
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pci_setup_bridge_mmio_pref(bridge);
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break;
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default:
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@ -735,18 +735,22 @@ int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
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static void pci_bridge_check_ranges(struct pci_bus *bus)
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{
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struct pci_dev *bridge = bus->self;
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struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
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struct resource *b_res;
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b_res[1].flags |= IORESOURCE_MEM;
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b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
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b_res->flags |= IORESOURCE_MEM;
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if (bridge->io_window)
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b_res[0].flags |= IORESOURCE_IO;
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if (bridge->io_window) {
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b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
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b_res->flags |= IORESOURCE_IO;
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}
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if (bridge->pref_window) {
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b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
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b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
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b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
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if (bridge->pref_64_window) {
|
||||
b_res[2].flags |= IORESOURCE_MEM_64;
|
||||
b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
|
||||
b_res->flags |= IORESOURCE_MEM_64 |
|
||||
PCI_PREF_RANGE_TYPE_64;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
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@ -1105,35 +1109,37 @@ static void pci_bus_size_cardbus(struct pci_bus *bus,
|
|||
struct list_head *realloc_head)
|
||||
{
|
||||
struct pci_dev *bridge = bus->self;
|
||||
struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
|
||||
struct resource *b_res;
|
||||
resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
|
||||
u16 ctrl;
|
||||
|
||||
if (b_res[0].parent)
|
||||
b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW];
|
||||
if (b_res->parent)
|
||||
goto handle_b_res_1;
|
||||
/*
|
||||
* Reserve some resources for CardBus. We reserve a fixed amount
|
||||
* of bus space for CardBus bridges.
|
||||
*/
|
||||
b_res[0].start = pci_cardbus_io_size;
|
||||
b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
|
||||
b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
|
||||
b_res->start = pci_cardbus_io_size;
|
||||
b_res->end = b_res->start + pci_cardbus_io_size - 1;
|
||||
b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
b_res[0].end -= pci_cardbus_io_size;
|
||||
b_res->end -= pci_cardbus_io_size;
|
||||
add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
|
||||
pci_cardbus_io_size);
|
||||
pci_cardbus_io_size);
|
||||
}
|
||||
|
||||
handle_b_res_1:
|
||||
if (b_res[1].parent)
|
||||
b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
|
||||
if (b_res->parent)
|
||||
goto handle_b_res_2;
|
||||
b_res[1].start = pci_cardbus_io_size;
|
||||
b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
|
||||
b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
|
||||
b_res->start = pci_cardbus_io_size;
|
||||
b_res->end = b_res->start + pci_cardbus_io_size - 1;
|
||||
b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
b_res[1].end -= pci_cardbus_io_size;
|
||||
add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
|
||||
pci_cardbus_io_size);
|
||||
b_res->end -= pci_cardbus_io_size;
|
||||
add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
|
||||
pci_cardbus_io_size);
|
||||
}
|
||||
|
||||
handle_b_res_2:
|
||||
|
|
@ -1153,21 +1159,22 @@ handle_b_res_2:
|
|||
pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
|
||||
}
|
||||
|
||||
if (b_res[2].parent)
|
||||
b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW];
|
||||
if (b_res->parent)
|
||||
goto handle_b_res_3;
|
||||
/*
|
||||
* If we have prefetchable memory support, allocate two regions.
|
||||
* Otherwise, allocate one region of twice the size.
|
||||
*/
|
||||
if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
|
||||
b_res[2].start = pci_cardbus_mem_size;
|
||||
b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
|
||||
b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
|
||||
IORESOURCE_STARTALIGN;
|
||||
b_res->start = pci_cardbus_mem_size;
|
||||
b_res->end = b_res->start + pci_cardbus_mem_size - 1;
|
||||
b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
|
||||
IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
b_res[2].end -= pci_cardbus_mem_size;
|
||||
add_to_list(realloc_head, bridge, b_res+2,
|
||||
pci_cardbus_mem_size, pci_cardbus_mem_size);
|
||||
b_res->end -= pci_cardbus_mem_size;
|
||||
add_to_list(realloc_head, bridge, b_res,
|
||||
pci_cardbus_mem_size, pci_cardbus_mem_size);
|
||||
}
|
||||
|
||||
/* Reduce that to half */
|
||||
|
|
@ -1175,15 +1182,16 @@ handle_b_res_2:
|
|||
}
|
||||
|
||||
handle_b_res_3:
|
||||
if (b_res[3].parent)
|
||||
b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
|
||||
if (b_res->parent)
|
||||
goto handle_done;
|
||||
b_res[3].start = pci_cardbus_mem_size;
|
||||
b_res[3].end = b_res[3].start + b_res_3_size - 1;
|
||||
b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
|
||||
b_res->start = pci_cardbus_mem_size;
|
||||
b_res->end = b_res->start + b_res_3_size - 1;
|
||||
b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
|
||||
if (realloc_head) {
|
||||
b_res[3].end -= b_res_3_size;
|
||||
add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
|
||||
pci_cardbus_mem_size);
|
||||
b_res->end -= b_res_3_size;
|
||||
add_to_list(realloc_head, bridge, b_res, b_res_3_size,
|
||||
pci_cardbus_mem_size);
|
||||
}
|
||||
|
||||
handle_done:
|
||||
|
|
@ -1227,7 +1235,7 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
|
|||
break;
|
||||
hdr_type = -1; /* Intentionally invalid - not a PCI device. */
|
||||
} else {
|
||||
pref = &bus->self->resource[PCI_BRIDGE_RESOURCES + 2];
|
||||
pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
|
||||
hdr_type = bus->self->hdr_type;
|
||||
}
|
||||
|
||||
|
|
@ -1885,9 +1893,9 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
|
|||
struct pci_dev *dev, *bridge = bus->self;
|
||||
resource_size_t io_per_hp, mmio_per_hp, mmio_pref_per_hp, align;
|
||||
|
||||
io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
|
||||
mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
|
||||
mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
|
||||
io_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
|
||||
mmio_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
|
||||
mmio_pref_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
|
||||
|
||||
/*
|
||||
* The alignment of this bridge is yet to be considered, hence it must
|
||||
|
|
@ -1960,21 +1968,21 @@ static void pci_bus_distribute_available_resources(struct pci_bus *bus,
|
|||
* Reduce the available resource space by what the
|
||||
* bridge and devices below it occupy.
|
||||
*/
|
||||
res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
|
||||
res = &dev->resource[PCI_BRIDGE_IO_WINDOW];
|
||||
align = pci_resource_alignment(dev, res);
|
||||
align = align ? ALIGN(io.start, align) - io.start : 0;
|
||||
used_size = align + resource_size(res);
|
||||
if (!res->parent)
|
||||
io.start = min(io.start + used_size, io.end + 1);
|
||||
|
||||
res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
|
||||
res = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
|
||||
align = pci_resource_alignment(dev, res);
|
||||
align = align ? ALIGN(mmio.start, align) - mmio.start : 0;
|
||||
used_size = align + resource_size(res);
|
||||
if (!res->parent)
|
||||
mmio.start = min(mmio.start + used_size, mmio.end + 1);
|
||||
|
||||
res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
|
||||
res = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
|
||||
align = pci_resource_alignment(dev, res);
|
||||
align = align ? ALIGN(mmio_pref.start, align) -
|
||||
mmio_pref.start : 0;
|
||||
|
|
@ -2027,9 +2035,9 @@ static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
|
|||
return;
|
||||
|
||||
/* Take the initial extra resources from the hotplug port */
|
||||
available_io = bridge->resource[PCI_BRIDGE_RESOURCES + 0];
|
||||
available_mmio = bridge->resource[PCI_BRIDGE_RESOURCES + 1];
|
||||
available_mmio_pref = bridge->resource[PCI_BRIDGE_RESOURCES + 2];
|
||||
available_io = bridge->resource[PCI_BRIDGE_IO_WINDOW];
|
||||
available_mmio = bridge->resource[PCI_BRIDGE_MEM_WINDOW];
|
||||
available_mmio_pref = bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
|
||||
|
||||
pci_bus_distribute_available_resources(bridge->subordinate,
|
||||
add_list, available_io,
|
||||
|
|
|
|||
|
|
@ -694,7 +694,7 @@ static int yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned type
|
|||
struct pci_bus_region region;
|
||||
unsigned mask;
|
||||
|
||||
res = dev->resource + PCI_BRIDGE_RESOURCES + nr;
|
||||
res = &dev->resource[nr];
|
||||
/* Already allocated? */
|
||||
if (res->parent)
|
||||
return 0;
|
||||
|
|
@ -711,7 +711,7 @@ static int yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned type
|
|||
region.end = config_readl(socket, addr_end) | ~mask;
|
||||
if (region.start && region.end > region.start && !override_bios) {
|
||||
pcibios_bus_to_resource(dev->bus, res, ®ion);
|
||||
if (pci_claim_resource(dev, PCI_BRIDGE_RESOURCES + nr) == 0)
|
||||
if (pci_claim_resource(dev, nr) == 0)
|
||||
return 0;
|
||||
dev_info(&dev->dev,
|
||||
"Preassigned resource %d busy or not available, reconfiguring...\n",
|
||||
|
|
@ -745,19 +745,35 @@ static int yenta_allocate_res(struct yenta_socket *socket, int nr, unsigned type
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void yenta_free_res(struct yenta_socket *socket, int nr)
|
||||
{
|
||||
struct pci_dev *dev = socket->dev;
|
||||
struct resource *res;
|
||||
|
||||
res = &dev->resource[nr];
|
||||
if (res->start != 0 && res->end != 0)
|
||||
release_resource(res);
|
||||
|
||||
res->start = res->end = res->flags = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Allocate the bridge mappings for the device..
|
||||
*/
|
||||
static void yenta_allocate_resources(struct yenta_socket *socket)
|
||||
{
|
||||
int program = 0;
|
||||
program += yenta_allocate_res(socket, 0, IORESOURCE_IO,
|
||||
program += yenta_allocate_res(socket, PCI_CB_BRIDGE_IO_0_WINDOW,
|
||||
IORESOURCE_IO,
|
||||
PCI_CB_IO_BASE_0, PCI_CB_IO_LIMIT_0);
|
||||
program += yenta_allocate_res(socket, 1, IORESOURCE_IO,
|
||||
program += yenta_allocate_res(socket, PCI_CB_BRIDGE_IO_1_WINDOW,
|
||||
IORESOURCE_IO,
|
||||
PCI_CB_IO_BASE_1, PCI_CB_IO_LIMIT_1);
|
||||
program += yenta_allocate_res(socket, 2, IORESOURCE_MEM|IORESOURCE_PREFETCH,
|
||||
program += yenta_allocate_res(socket, PCI_CB_BRIDGE_MEM_0_WINDOW,
|
||||
IORESOURCE_MEM | IORESOURCE_PREFETCH,
|
||||
PCI_CB_MEMORY_BASE_0, PCI_CB_MEMORY_LIMIT_0);
|
||||
program += yenta_allocate_res(socket, 3, IORESOURCE_MEM,
|
||||
program += yenta_allocate_res(socket, PCI_CB_BRIDGE_MEM_1_WINDOW,
|
||||
IORESOURCE_MEM,
|
||||
PCI_CB_MEMORY_BASE_1, PCI_CB_MEMORY_LIMIT_1);
|
||||
if (program)
|
||||
pci_setup_cardbus(socket->dev->subordinate);
|
||||
|
|
@ -769,14 +785,10 @@ static void yenta_allocate_resources(struct yenta_socket *socket)
|
|||
*/
|
||||
static void yenta_free_resources(struct yenta_socket *socket)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < 4; i++) {
|
||||
struct resource *res;
|
||||
res = socket->dev->resource + PCI_BRIDGE_RESOURCES + i;
|
||||
if (res->start != 0 && res->end != 0)
|
||||
release_resource(res);
|
||||
res->start = res->end = res->flags = 0;
|
||||
}
|
||||
yenta_free_res(socket, PCI_CB_BRIDGE_IO_0_WINDOW);
|
||||
yenta_free_res(socket, PCI_CB_BRIDGE_IO_1_WINDOW);
|
||||
yenta_free_res(socket, PCI_CB_BRIDGE_MEM_0_WINDOW);
|
||||
yenta_free_res(socket, PCI_CB_BRIDGE_MEM_1_WINDOW);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -100,9 +100,21 @@ enum {
|
|||
PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
|
||||
#endif
|
||||
|
||||
/* Resources assigned to buses behind the bridge */
|
||||
/* PCI-to-PCI (P2P) bridge windows */
|
||||
#define PCI_BRIDGE_IO_WINDOW (PCI_BRIDGE_RESOURCES + 0)
|
||||
#define PCI_BRIDGE_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 1)
|
||||
#define PCI_BRIDGE_PREF_MEM_WINDOW (PCI_BRIDGE_RESOURCES + 2)
|
||||
|
||||
/* CardBus bridge windows */
|
||||
#define PCI_CB_BRIDGE_IO_0_WINDOW (PCI_BRIDGE_RESOURCES + 0)
|
||||
#define PCI_CB_BRIDGE_IO_1_WINDOW (PCI_BRIDGE_RESOURCES + 1)
|
||||
#define PCI_CB_BRIDGE_MEM_0_WINDOW (PCI_BRIDGE_RESOURCES + 2)
|
||||
#define PCI_CB_BRIDGE_MEM_1_WINDOW (PCI_BRIDGE_RESOURCES + 3)
|
||||
|
||||
/* Total number of bridge resources for P2P and CardBus */
|
||||
#define PCI_BRIDGE_RESOURCE_NUM 4
|
||||
|
||||
/* Resources assigned to buses behind the bridge */
|
||||
PCI_BRIDGE_RESOURCES,
|
||||
PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
|
||||
PCI_BRIDGE_RESOURCE_NUM - 1,
|
||||
|
|
|
|||
Loading…
Reference in New Issue