Samsung DTS ARM64 changes for v4.21, part 2

Add IMEM clock controller (for Security SubSystem) and Bluetooth chip to
 Exynos5433 TM2(e) boards.
 -----BEGIN PGP SIGNATURE-----
 
 iQJEBAABCgAuFiEE3dJiKD0RGyM7briowTdm5oaLg9cFAlwZUDoQHGtyemtAa2Vy
 bmVsLm9yZwAKCRDBN2bmhouD1w6DD/0Uew7/eRS16gt6EChKidNjbMsAeMoe790n
 +CxlMEcopK4Eab1q0gftu1D++nTNHD0k6jxYLNQgKqg+zovDg/csYZiLX4F6W1Re
 jSWNXUQvoTXKc85MvCJW2tpo5if9rEJLm+OBDSL4ih524SMzPvySp9eRFNKP7jy3
 PPgdkwkXiCtRhzIIGa/fWxYhbkJ//k6poKFRPgVwQbcqKhbRLsHZCXRe7NRzTejU
 o8hGonjoekrou9JRR0jC82qNOan3vrAH//aAZJNlYdpjRC+tW/iGMLXK9wfPMQGO
 I1SaMETdfEES+uORqaVhcz778rCoBtj9jk9S2QnKLUhpLV6d+RcLHUMkXBQ3A9ZX
 EgtuzGcedcQHQiHvn0OBwOJYfY2cmQ+cQMWgL2jiETqlJD7bpAl8Zsv5rjZ/+vdI
 WGPC/4NSukbS8Va8gqqkLs6UElSJlV18NUayBqSPDvH2UMMSwn/ILV39fSxVpG/0
 y1Tu2cpsMMwapHv3zC6RigvWZkOMx5DwD0TJg43iyCvvVhmo+9JV/GWhe7wM0ymX
 29GL2F6PmIzpzAa3HdNeS7iAqYWmMvZ5e2c+6gvc0LGoP+QO2a2eRH8sy+iVF5JU
 uk8BZbXFfVeKU+K71Z83fm0zpQZY2GD9GJZYwEKVfQ0wGoXtjeJ5iQhWPohCC15V
 coWHMUKp2A==
 =JVh0
 -----END PGP SIGNATURE-----

Merge tag 'samsung-dt64-4.21-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late

Samsung DTS ARM64 changes for v4.21, part 2

Add IMEM clock controller (for Security SubSystem) and Bluetooth chip to
Exynos5433 TM2(e) boards.

* tag 'samsung-dt64-4.21-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Add Bluetooth chip to TM2(e) boards
  arm64: dts: exynos: Add IMEM clock controller to Exynos5433
  arm64: dts: exynos: Add all CPUs in cooling maps
  arm64: dts: exynos: Update DWC3 modules on Exynos5433 SoCs

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2018-12-31 13:11:04 -08:00
commit 8a66c20e66
3 changed files with 71 additions and 18 deletions

View File

@ -1202,6 +1202,20 @@
status = "okay";
};
&serial_3 {
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
clock-names = "extclk";
};
};
&spi_1 {
cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
status = "okay";

View File

@ -55,37 +55,44 @@ thermal-zones {
map0 {
/* Set maximum frequency as 1800MHz */
trip = <&atlas0_alert_0>;
cooling-device = <&cpu4 1 2>;
cooling-device = <&cpu4 1 2>, <&cpu5 1 2>,
<&cpu6 1 2>, <&cpu7 1 2>;
};
map1 {
/* Set maximum frequency as 1700MHz */
trip = <&atlas0_alert_1>;
cooling-device = <&cpu4 2 3>;
cooling-device = <&cpu4 2 3>, <&cpu5 2 3>,
<&cpu6 2 3>, <&cpu7 2 3>;
};
map2 {
/* Set maximum frequency as 1600MHz */
trip = <&atlas0_alert_2>;
cooling-device = <&cpu4 3 4>;
cooling-device = <&cpu4 3 4>, <&cpu5 3 4>,
<&cpu6 3 4>, <&cpu7 3 4>;
};
map3 {
/* Set maximum frequency as 1500MHz */
trip = <&atlas0_alert_3>;
cooling-device = <&cpu4 4 5>;
cooling-device = <&cpu4 4 5>, <&cpu5 4 5>,
<&cpu6 4 5>, <&cpu7 4 5>;
};
map4 {
/* Set maximum frequency as 1400MHz */
trip = <&atlas0_alert_4>;
cooling-device = <&cpu4 5 7>;
cooling-device = <&cpu4 5 7>, <&cpu5 5 7>,
<&cpu6 5 7>, <&cpu7 5 7>;
};
map5 {
/* Set maximum frequencyas 1200MHz */
trip = <&atlas0_alert_5>;
cooling-device = <&cpu4 7 9>;
cooling-device = <&cpu4 7 9>, <&cpu5 7 9>,
<&cpu6 7 9>, <&cpu7 7 9>;
};
map6 {
/* Set maximum frequency as 1000MHz */
trip = <&atlas0_alert_6>;
cooling-device = <&cpu4 9 14>;
cooling-device = <&cpu4 9 14>, <&cpu5 9 14>,
<&cpu6 9 14>, <&cpu7 9 14>;
};
};
};
@ -222,27 +229,32 @@ thermal-zones {
map0 {
/* Set maximum frequency as 1200MHz */
trip = <&apollo_alert_2>;
cooling-device = <&cpu0 1 2>;
cooling-device = <&cpu0 1 2>, <&cpu1 1 2>,
<&cpu2 1 2>, <&cpu3 1 2>;
};
map1 {
/* Set maximum frequency as 1100MHz */
trip = <&apollo_alert_3>;
cooling-device = <&cpu0 2 3>;
cooling-device = <&cpu0 2 3>, <&cpu1 2 3>,
<&cpu2 2 3>, <&cpu3 2 3>;
};
map2 {
/* Set maximum frequency as 1000MHz */
trip = <&apollo_alert_4>;
cooling-device = <&cpu0 3 4>;
cooling-device = <&cpu0 3 4>, <&cpu1 3 4>,
<&cpu2 3 4>, <&cpu3 3 4>;
};
map3 {
/* Set maximum frequency as 900MHz */
trip = <&apollo_alert_5>;
cooling-device = <&cpu0 4 5>;
cooling-device = <&cpu0 4 5>, <&cpu1 4 5>,
<&cpu2 4 5>, <&cpu3 4 5>;
};
map4 {
/* Set maximum frequency as 800MHz */
trip = <&apollo_alert_6>;
cooling-device = <&cpu0 5 9>;
cooling-device = <&cpu0 5 9>, <&cpu1 5 9>,
<&cpu2 5 9>, <&cpu3 5 9>;
};
};
};

View File

@ -544,6 +544,21 @@
power-domains = <&pd_cam1>;
};
cmu_imem: clock-controller@11060000 {
compatible = "samsung,exynos5433-cmu-imem";
reg = <0x11060000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_imem_sssx_266",
"aclk_imem_266",
"aclk_imem_200";
clocks = <&xxti>,
<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
<&cmu_top CLK_DIV_ACLK_IMEM_266>,
<&cmu_top CLK_DIV_ACLK_IMEM_200>;
};
pd_gscl: power-domain@105c4000 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4000 0x20>;
@ -1559,10 +1574,12 @@
};
usbdrd30: usbdrd {
compatible = "samsung,exynos5250-dwusb3";
compatible = "samsung,exynos5433-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
<&cmu_fsys CLK_SCLK_USBDRD30>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
<&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>;
clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -1570,6 +1587,10 @@
usbdrd_dwc3: dwc3@15400000 {
compatible = "snps,dwc3";
clocks = <&cmu_fsys CLK_SCLK_USBDRD30>,
<&cmu_fsys CLK_ACLK_USBDRD30>,
<&cmu_fsys CLK_SCLK_USBDRD30>;
clock-names = "ref", "bus_early", "suspend";
reg = <0x15400000 0x10000>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
@ -1606,10 +1627,12 @@
};
usbhost30: usbhost {
compatible = "samsung,exynos5250-dwusb3";
compatible = "samsung,exynos5433-dwusb3";
clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "usbdrd30", "usbdrd30_susp_clk";
<&cmu_fsys CLK_SCLK_USBHOST30>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
<&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>;
clock-names = "aclk", "susp_clk", "phyclk", "pipe_pclk";
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -1617,6 +1640,10 @@
usbhost_dwc3: dwc3@15a00000 {
compatible = "snps,dwc3";
clocks = <&cmu_fsys CLK_SCLK_USBHOST30>,
<&cmu_fsys CLK_ACLK_USBHOST30>,
<&cmu_fsys CLK_SCLK_USBHOST30>;
clock-names = "ref", "bus_early", "suspend";
reg = <0x15a00000 0x10000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;