mtip32xx: avoid to read HOST_CAP from HW in .queue_rq()
It is observed reading the register from HW takes a bit long, for example in my box, the following difference of 'perf report --no-children fio ...' can be seen when running I/O: 1) V4.12 without patch + 9.28% fio [mtip32xx] [k] mtip_irq_handler + 8.48% fio [mtip32xx] [k] mtip_init_cmd_header 2) V4.12 with the following patch + 9.14% fio [mtip32xx] [k] mtip_irq_handler ...... + 1.14% fio [mtip32xx] [k] mtip_init_cmd_header IOPS can be increased by ~5% with this patch too. Fixes: a4e84aae8139(mtip32xx: use runtime tag to initialize command header) Signed-off-by: Ming Lei <ming.lei@redhat.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Jens Axboe <axboe@kernel.dk>
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@ -174,7 +174,6 @@ static void mtip_init_cmd_header(struct request *rq)
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{
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{
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struct driver_data *dd = rq->q->queuedata;
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struct driver_data *dd = rq->q->queuedata;
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struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
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struct mtip_cmd *cmd = blk_mq_rq_to_pdu(rq);
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u32 host_cap_64 = readl(dd->mmio + HOST_CAP) & HOST_CAP_64;
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/* Point the command headers at the command tables. */
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/* Point the command headers at the command tables. */
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cmd->command_header = dd->port->command_list +
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cmd->command_header = dd->port->command_list +
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@ -182,7 +181,7 @@ static void mtip_init_cmd_header(struct request *rq)
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cmd->command_header_dma = dd->port->command_list_dma +
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cmd->command_header_dma = dd->port->command_list_dma +
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(sizeof(struct mtip_cmd_hdr) * rq->tag);
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(sizeof(struct mtip_cmd_hdr) * rq->tag);
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if (host_cap_64)
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if (test_bit(MTIP_PF_HOST_CAP_64, &dd->port->flags))
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cmd->command_header->ctbau = __force_bit2int cpu_to_le32((cmd->command_dma >> 16) >> 16);
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cmd->command_header->ctbau = __force_bit2int cpu_to_le32((cmd->command_dma >> 16) >> 16);
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cmd->command_header->ctba = __force_bit2int cpu_to_le32(cmd->command_dma & 0xFFFFFFFF);
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cmd->command_header->ctba = __force_bit2int cpu_to_le32(cmd->command_dma & 0xFFFFFFFF);
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@ -386,6 +385,7 @@ static void mtip_init_port(struct mtip_port *port)
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port->mmio + PORT_LST_ADDR_HI);
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port->mmio + PORT_LST_ADDR_HI);
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writel((port->rxfis_dma >> 16) >> 16,
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writel((port->rxfis_dma >> 16) >> 16,
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port->mmio + PORT_FIS_ADDR_HI);
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port->mmio + PORT_FIS_ADDR_HI);
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set_bit(MTIP_PF_HOST_CAP_64, &port->flags);
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}
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}
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writel(port->command_list_dma & 0xFFFFFFFF,
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writel(port->command_list_dma & 0xFFFFFFFF,
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@ -140,6 +140,7 @@ enum {
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(1 << MTIP_PF_SE_ACTIVE_BIT) |
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(1 << MTIP_PF_SE_ACTIVE_BIT) |
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(1 << MTIP_PF_DM_ACTIVE_BIT) |
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(1 << MTIP_PF_DM_ACTIVE_BIT) |
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(1 << MTIP_PF_TO_ACTIVE_BIT)),
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(1 << MTIP_PF_TO_ACTIVE_BIT)),
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MTIP_PF_HOST_CAP_64 = 10, /* cache HOST_CAP_64 */
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MTIP_PF_SVC_THD_ACTIVE_BIT = 4,
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MTIP_PF_SVC_THD_ACTIVE_BIT = 4,
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MTIP_PF_ISSUE_CMDS_BIT = 5,
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MTIP_PF_ISSUE_CMDS_BIT = 5,
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