ARM: dts: Fix incorrect dcan register mapping for am3, am4 and dra7
We are currently using a wrong register for dcan revision. Although this is currently only used for detecting the dcan module, let's fix it to avoid confusion. Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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2e8647bbe1
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@ -1758,6 +1758,8 @@
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target-module@cc000 { /* 0x481cc000, ap 60 46.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0xcc020 0x4>;
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reg-names = "rev";
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ti,hwmods = "d_can0";
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/* Domains (P, C): per_pwrdm, l4ls_clkdm */
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clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN0_CLKCTRL 0>,
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@ -1780,6 +1782,8 @@
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target-module@d0000 { /* 0x481d0000, ap 62 42.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0xd0020 0x4>;
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reg-names = "rev";
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ti,hwmods = "d_can1";
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/* Domains (P, C): per_pwrdm, l4ls_clkdm */
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clocks = <&l4ls_clkctrl AM3_L4LS_D_CAN1_CLKCTRL 0>,
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@ -1574,6 +1574,8 @@
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target-module@cc000 { /* 0x481cc000, ap 50 46.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0xcc020 0x4>;
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reg-names = "rev";
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ti,hwmods = "d_can0";
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/* Domains (P, C): per_pwrdm, l4ls_clkdm */
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clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN0_CLKCTRL 0>;
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@ -1593,6 +1595,8 @@
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target-module@d0000 { /* 0x481d0000, ap 52 3a.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0xd0020 0x4>;
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reg-names = "rev";
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ti,hwmods = "d_can1";
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/* Domains (P, C): per_pwrdm, l4ls_clkdm */
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clocks = <&l4ls_clkctrl AM4_L4LS_D_CAN1_CLKCTRL 0>;
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@ -3025,7 +3025,7 @@
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target-module@80000 { /* 0x48480000, ap 31 16.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0x80000 0x4>;
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reg = <0x80020 0x4>;
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reg-names = "rev";
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clocks = <&l4per2_clkctrl DRA7_L4PER2_DCAN2_CLKCTRL 0>;
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clock-names = "fck";
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@ -4577,7 +4577,7 @@
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target-module@c000 { /* 0x4ae3c000, ap 30 04.0 */
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compatible = "ti,sysc-omap4", "ti,sysc";
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reg = <0xc000 0x4>;
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reg = <0xc020 0x4>;
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reg-names = "rev";
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clocks = <&wkupaon_clkctrl DRA7_WKUPAON_DCAN1_CLKCTRL 0>;
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clock-names = "fck";
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@ -1267,7 +1267,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = {
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SYSC_QUIRK("control", 0, 0, 0x10, -1, 0x40000900, 0xffffffff, 0),
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SYSC_QUIRK("cpgmac", 0, 0x1200, 0x1208, 0x1204, 0x4edb1902,
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0xffff00f0, 0),
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SYSC_QUIRK("dcan", 0, 0, -1, -1, 0xffffffff, 0xffffffff, 0),
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SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0xa3170504, 0xffffffff, 0),
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SYSC_QUIRK("dcan", 0, 0x20, -1, -1, 0x4edb1902, 0xffffffff, 0),
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SYSC_QUIRK("dmic", 0, 0, 0x10, -1, 0x50010000, 0xffffffff, 0),
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SYSC_QUIRK("dwc3", 0, 0, 0x10, -1, 0x500a0200, 0xffffffff, 0),
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SYSC_QUIRK("epwmss", 0, 0, 0x4, -1, 0x47400001, 0xffffffff, 0),
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