MIPS: i8259: Convert IRQ controller lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
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598c5abad7
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8965087055
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@ -35,7 +35,7 @@
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#define SLAVE_ICW4_DEFAULT 0x01
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#define PIC_ICW4_AEOI 2
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extern spinlock_t i8259A_lock;
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extern raw_spinlock_t i8259A_lock;
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extern int i8259A_irq_pending(unsigned int irq);
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extern void make_8259A_irq(unsigned int irq);
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@ -51,7 +51,7 @@ static inline int i8259_irq(void)
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{
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int irq;
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spin_lock(&i8259A_lock);
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raw_spin_lock(&i8259A_lock);
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/* Perform an interrupt acknowledge cycle on controller 1. */
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outb(0x0C, PIC_MASTER_CMD); /* prepare for poll */
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@ -78,7 +78,7 @@ static inline int i8259_irq(void)
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irq = -1;
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}
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spin_unlock(&i8259A_lock);
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raw_spin_unlock(&i8259A_lock);
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return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
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}
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@ -29,7 +29,7 @@
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*/
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static int i8259A_auto_eoi = -1;
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DEFINE_SPINLOCK(i8259A_lock);
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DEFINE_RAW_SPINLOCK(i8259A_lock);
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static void disable_8259A_irq(unsigned int irq);
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static void enable_8259A_irq(unsigned int irq);
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static void mask_and_ack_8259A(unsigned int irq);
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@ -65,13 +65,13 @@ static void disable_8259A_irq(unsigned int irq)
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irq -= I8259A_IRQ_BASE;
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mask = 1 << irq;
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spin_lock_irqsave(&i8259A_lock, flags);
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask |= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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static void enable_8259A_irq(unsigned int irq)
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@ -81,13 +81,13 @@ static void enable_8259A_irq(unsigned int irq)
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irq -= I8259A_IRQ_BASE;
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mask = ~(1 << irq);
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spin_lock_irqsave(&i8259A_lock, flags);
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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cached_irq_mask &= mask;
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if (irq & 8)
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outb(cached_slave_mask, PIC_SLAVE_IMR);
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else
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outb(cached_master_mask, PIC_MASTER_IMR);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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int i8259A_irq_pending(unsigned int irq)
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@ -98,12 +98,12 @@ int i8259A_irq_pending(unsigned int irq)
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irq -= I8259A_IRQ_BASE;
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mask = 1 << irq;
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spin_lock_irqsave(&i8259A_lock, flags);
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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if (irq < 8)
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ret = inb(PIC_MASTER_CMD) & mask;
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else
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ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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return ret;
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}
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@ -151,7 +151,7 @@ static void mask_and_ack_8259A(unsigned int irq)
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irq -= I8259A_IRQ_BASE;
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irqmask = 1 << irq;
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spin_lock_irqsave(&i8259A_lock, flags);
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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/*
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* Lightweight spurious IRQ detection. We do not want
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* to overdo spurious IRQ handling - it's usually a sign
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@ -183,7 +183,7 @@ handle_real_irq:
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outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
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}
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smtc_im_ack_irq(irq);
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spin_unlock_irqrestore(&i8259A_lock, flags);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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return;
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spurious_8259A_irq:
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@ -264,7 +264,7 @@ static void init_8259A(int auto_eoi)
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i8259A_auto_eoi = auto_eoi;
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spin_lock_irqsave(&i8259A_lock, flags);
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raw_spin_lock_irqsave(&i8259A_lock, flags);
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outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
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outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
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@ -298,7 +298,7 @@ static void init_8259A(int auto_eoi)
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outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
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outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
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spin_unlock_irqrestore(&i8259A_lock, flags);
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raw_spin_unlock_irqrestore(&i8259A_lock, flags);
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}
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/*
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@ -38,7 +38,7 @@ int mach_i8259_irq(void)
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irq = -1;
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if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) {
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spin_lock(&i8259A_lock);
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raw_spin_lock(&i8259A_lock);
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isr = inb(PIC_MASTER_CMD) &
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~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR);
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if (!isr)
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@ -56,7 +56,7 @@ int mach_i8259_irq(void)
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if (~inb(PIC_MASTER_ISR) & 0x80)
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irq = -1;
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}
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spin_unlock(&i8259A_lock);
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raw_spin_unlock(&i8259A_lock);
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}
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return irq;
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