PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP. [bhelgaas: minor whitespace fixes] Signed-off-by: Srikanth Thokala <sthokal@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Srikanth Thokala
Bjorn Helgaas
parent
52addcf9d6
commit
8961def568
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@ -0,0 +1,62 @@
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* Xilinx AXI PCIe Root Port Bridge DT description
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Required properties:
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- #address-cells: Address representation for root ports, set to <3>
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- #size-cells: Size representation for root ports, set to <2>
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
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- reg: Should contain AXI PCIe registers location and length
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- device_type: must be "pci"
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- interrupts: Should contain AXI PCIe interrupt
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- interrupt-map-mask,
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interrupt-map: standard PCI properties to define the mapping of the
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PCI interface to interrupt numbers.
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- ranges: ranges for the PCI memory regions (I/O space region is not
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supported by hardware)
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Please refer to the standard PCI bus binding document for a more
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detailed explanation
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Optional properties:
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- bus-range: PCI bus numbers covered
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Interrupt controller child node
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+++++++++++++++++++++++++++++++
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Required properties:
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- interrupt-controller: identifies the node as an interrupt controller
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- #address-cells: specifies the number of cells needed to encode an
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address. The value must be 0.
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- #interrupt-cells: specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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NOTE:
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The core provides a single interrupt for both INTx/MSI messages. So,
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created a interrupt controller node to support 'interrupt-map' DT
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functionality. The driver will create an IRQ domain for this map, decode
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the four INTx interrupts in ISR and route them to this domain.
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Example:
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++++++++
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pci_express: axi-pcie@50000000 {
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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compatible = "xlnx,axi-pcie-host-1.00.a";
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reg = < 0x50000000 0x10000000 >;
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device_type = "pci";
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interrupts = < 0 52 4 >;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 1>,
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<0 0 0 2 &pcie_intc 2>,
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<0 0 0 3 &pcie_intc 3>,
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<0 0 0 4 &pcie_intc 4>;
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ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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}
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};
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@ -63,4 +63,11 @@ config PCIE_SPEAR13XX
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help
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Say Y here if you want PCIe support on SPEAr13XX SoCs.
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config PCIE_XILINX
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bool "Xilinx AXI PCIe host bridge support"
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depends on ARCH_ZYNQ
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help
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Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
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Host Bridge driver.
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endmenu
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@ -8,3 +8,4 @@ obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
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obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
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obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
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obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx.o
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@ -0,0 +1,970 @@
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/*
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* PCIe host controller driver for Xilinx AXI PCIe Bridge
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*
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* Copyright (c) 2012 - 2014 Xilinx, Inc.
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*
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* Based on the Tegra PCIe driver
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*
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* Bits taken from Synopsys Designware Host controller driver and
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* ARM PCI Host generic driver.
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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/* Register definitions */
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#define XILINX_PCIE_REG_BIR 0x00000130
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#define XILINX_PCIE_REG_IDR 0x00000138
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#define XILINX_PCIE_REG_IMR 0x0000013c
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#define XILINX_PCIE_REG_PSCR 0x00000144
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#define XILINX_PCIE_REG_RPSC 0x00000148
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#define XILINX_PCIE_REG_MSIBASE1 0x0000014c
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#define XILINX_PCIE_REG_MSIBASE2 0x00000150
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#define XILINX_PCIE_REG_RPEFR 0x00000154
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#define XILINX_PCIE_REG_RPIFR1 0x00000158
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#define XILINX_PCIE_REG_RPIFR2 0x0000015c
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/* Interrupt registers definitions */
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#define XILINX_PCIE_INTR_LINK_DOWN BIT(0)
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#define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
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#define XILINX_PCIE_INTR_STR_ERR BIT(2)
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#define XILINX_PCIE_INTR_HOT_RESET BIT(3)
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#define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8)
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#define XILINX_PCIE_INTR_CORRECTABLE BIT(9)
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#define XILINX_PCIE_INTR_NONFATAL BIT(10)
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#define XILINX_PCIE_INTR_FATAL BIT(11)
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#define XILINX_PCIE_INTR_INTX BIT(16)
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#define XILINX_PCIE_INTR_MSI BIT(17)
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#define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20)
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#define XILINX_PCIE_INTR_SLV_UNEXP BIT(21)
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#define XILINX_PCIE_INTR_SLV_COMPL BIT(22)
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#define XILINX_PCIE_INTR_SLV_ERRP BIT(23)
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#define XILINX_PCIE_INTR_SLV_CMPABT BIT(24)
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#define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25)
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#define XILINX_PCIE_INTR_MST_DECERR BIT(26)
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#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)
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#define XILINX_PCIE_INTR_MST_ERRP BIT(28)
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#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED
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#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF
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/* Root Port Error FIFO Read Register definitions */
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#define XILINX_PCIE_RPEFR_ERR_VALID BIT(18)
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#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
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#define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
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/* Root Port Interrupt FIFO Read Register 1 definitions */
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#define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31)
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#define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30)
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#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)
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#define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF
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#define XILINX_PCIE_RPIFR1_INTR_SHIFT 27
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/* Bridge Info Register definitions */
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#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)
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#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16
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/* Root Port Interrupt FIFO Read Register 2 definitions */
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#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)
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/* Root Port Status/control Register definitions */
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#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
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/* Phy Status/Control Register definitions */
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#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
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/* ECAM definitions */
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#define ECAM_BUS_NUM_SHIFT 20
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#define ECAM_DEV_NUM_SHIFT 12
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/* Number of MSI IRQs */
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#define XILINX_NUM_MSI_IRQS 128
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/* Number of Memory Resources */
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#define XILINX_MAX_NUM_RESOURCES 3
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/**
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* struct xilinx_pcie_port - PCIe port information
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* @reg_base: IO Mapped Register Base
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* @irq: Interrupt number
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* @msi_pages: MSI pages
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* @root_busno: Root Bus number
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* @dev: Device pointer
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* @irq_domain: IRQ domain pointer
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* @bus_range: Bus range
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* @resources: Bus Resources
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*/
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struct xilinx_pcie_port {
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void __iomem *reg_base;
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u32 irq;
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unsigned long msi_pages;
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u8 root_busno;
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struct device *dev;
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struct irq_domain *irq_domain;
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struct resource bus_range;
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struct list_head resources;
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};
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static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
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static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
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{
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return sys->private_data;
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}
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static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
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{
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return readl(port->reg_base + reg);
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}
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static inline void pcie_write(struct xilinx_pcie_port *port, u32 val, u32 reg)
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{
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writel(val, port->reg_base + reg);
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}
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static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
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{
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return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
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XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
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}
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/**
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* xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
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* @port: PCIe port information
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*/
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static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
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{
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u32 val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
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if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
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dev_dbg(port->dev, "Requester ID %d\n",
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val & XILINX_PCIE_RPEFR_REQ_ID);
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pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
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XILINX_PCIE_REG_RPEFR);
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}
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}
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/**
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* xilinx_pcie_valid_device - Check if a valid device is present on bus
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* @bus: PCI Bus structure
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* @devfn: device/function
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*
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* Return: 'true' on success and 'false' if invalid device is found
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*/
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static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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{
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struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
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/* Check if link is up when trying to access downstream ports */
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if (bus->number != port->root_busno)
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if (!xilinx_pcie_link_is_up(port))
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return false;
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/* Only one device down on each root port */
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if (bus->number == port->root_busno && devfn > 0)
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return false;
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/*
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* Do not read more than one device on the bus directly attached
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* to RC.
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*/
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if (bus->primary == port->root_busno && devfn > 0)
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return false;
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return true;
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}
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/**
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* xilinx_pcie_config_base - Get configuration base
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* @bus: PCI Bus structure
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* @devfn: Device/function
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* @where: Offset from base
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*
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* Return: Base address of the configuration space needed to be
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* accessed.
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*/
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static void __iomem *xilinx_pcie_config_base(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
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int relbus;
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relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
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(devfn << ECAM_DEV_NUM_SHIFT);
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return port->reg_base + relbus + where;
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}
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/**
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* xilinx_pcie_read_config - Read configuration space
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* @bus: PCI Bus structure
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* @devfn: Device/function
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* @where: Offset from base
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* @size: Byte/word/dword
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* @val: Value to be read
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*
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* Return: PCIBIOS_SUCCESSFUL on success
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* PCIBIOS_DEVICE_NOT_FOUND on failure
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*/
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static int xilinx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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void __iomem *addr;
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if (!xilinx_pcie_valid_device(bus, devfn)) {
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*val = 0xFFFFFFFF;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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addr = xilinx_pcie_config_base(bus, devfn, where);
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switch (size) {
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case 1:
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*val = readb(addr);
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break;
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case 2:
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*val = readw(addr);
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break;
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default:
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*val = readl(addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/**
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* xilinx_pcie_write_config - Write configuration space
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* @bus: PCI Bus structure
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* @devfn: Device/function
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* @where: Offset from base
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* @size: Byte/word/dword
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* @val: Value to be written to device
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*
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* Return: PCIBIOS_SUCCESSFUL on success
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* PCIBIOS_DEVICE_NOT_FOUND on failure
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*/
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static int xilinx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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void __iomem *addr;
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if (!xilinx_pcie_valid_device(bus, devfn))
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return PCIBIOS_DEVICE_NOT_FOUND;
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addr = xilinx_pcie_config_base(bus, devfn, where);
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switch (size) {
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case 1:
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writeb(val, addr);
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break;
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case 2:
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writew(val, addr);
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break;
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default:
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writel(val, addr);
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break;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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/* PCIe operations */
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static struct pci_ops xilinx_pcie_ops = {
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.read = xilinx_pcie_read_config,
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.write = xilinx_pcie_write_config,
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};
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/* MSI functions */
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/**
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* xilinx_pcie_destroy_msi - Free MSI number
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* @irq: IRQ to be freed
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*/
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static void xilinx_pcie_destroy_msi(unsigned int irq)
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{
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struct irq_desc *desc;
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struct msi_desc *msi;
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struct xilinx_pcie_port *port;
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desc = irq_to_desc(irq);
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msi = irq_desc_get_msi_desc(desc);
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port = sys_to_pcie(msi->dev->bus->sysdata);
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if (!test_bit(irq, msi_irq_in_use))
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dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
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else
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clear_bit(irq, msi_irq_in_use);
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}
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/**
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* xilinx_pcie_assign_msi - Allocate MSI number
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* @port: PCIe port structure
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*
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* Return: A valid IRQ on success and error value on failure.
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*/
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static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
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{
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int pos;
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pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
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if (pos < XILINX_NUM_MSI_IRQS)
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set_bit(pos, msi_irq_in_use);
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else
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return -ENOSPC;
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return pos;
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}
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/**
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* xilinx_msi_teardown_irq - Destroy the MSI
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* @chip: MSI Chip descriptor
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* @irq: MSI IRQ to destroy
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*/
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static void xilinx_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
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{
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xilinx_pcie_destroy_msi(irq);
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}
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/**
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* xilinx_pcie_msi_setup_irq - Setup MSI request
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* @chip: MSI chip pointer
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* @pdev: PCIe device pointer
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* @desc: MSI descriptor pointer
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*
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* Return: '0' on success and error value on failure
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*/
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static int xilinx_pcie_msi_setup_irq(struct msi_chip *chip,
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struct pci_dev *pdev,
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struct msi_desc *desc)
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{
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struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
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unsigned int irq;
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int hwirq;
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struct msi_msg msg;
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phys_addr_t msg_addr;
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|
||||
hwirq = xilinx_pcie_assign_msi(port);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
irq = irq_create_mapping(port->irq_domain, hwirq);
|
||||
if (!irq)
|
||||
return -EINVAL;
|
||||
|
||||
irq_set_msi_desc(irq, desc);
|
||||
|
||||
msg_addr = virt_to_phys((void *)port->msi_pages);
|
||||
|
||||
msg.address_hi = 0;
|
||||
msg.address_lo = msg_addr;
|
||||
msg.data = irq;
|
||||
|
||||
write_msi_msg(irq, &msg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* MSI Chip Descriptor */
|
||||
static struct msi_chip xilinx_pcie_msi_chip = {
|
||||
.setup_irq = xilinx_pcie_msi_setup_irq,
|
||||
.teardown_irq = xilinx_msi_teardown_irq,
|
||||
};
|
||||
|
||||
/* HW Interrupt Chip Descriptor */
|
||||
static struct irq_chip xilinx_msi_irq_chip = {
|
||||
.name = "Xilinx PCIe MSI",
|
||||
.irq_enable = unmask_msi_irq,
|
||||
.irq_disable = mask_msi_irq,
|
||||
.irq_mask = mask_msi_irq,
|
||||
.irq_unmask = unmask_msi_irq,
|
||||
};
|
||||
|
||||
/**
|
||||
* xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
|
||||
* @domain: IRQ domain
|
||||
* @irq: Virtual IRQ number
|
||||
* @hwirq: HW interrupt number
|
||||
*
|
||||
* Return: Always returns 0.
|
||||
*/
|
||||
static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
|
||||
irq_set_chip_data(irq, domain->host_data);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* IRQ Domain operations */
|
||||
static const struct irq_domain_ops msi_domain_ops = {
|
||||
.map = xilinx_pcie_msi_map,
|
||||
};
|
||||
|
||||
/**
|
||||
* xilinx_pcie_enable_msi - Enable MSI support
|
||||
* @port: PCIe port information
|
||||
*/
|
||||
static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
|
||||
{
|
||||
phys_addr_t msg_addr;
|
||||
|
||||
port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
|
||||
msg_addr = virt_to_phys((void *)port->msi_pages);
|
||||
pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
|
||||
pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_add_bus - Add MSI chip info to PCIe bus
|
||||
* @bus: PCIe bus
|
||||
*/
|
||||
static void xilinx_pcie_add_bus(struct pci_bus *bus)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
|
||||
|
||||
xilinx_pcie_msi_chip.dev = port->dev;
|
||||
bus->msi = &xilinx_pcie_msi_chip;
|
||||
}
|
||||
}
|
||||
|
||||
/* INTx Functions */
|
||||
|
||||
/**
|
||||
* xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
|
||||
* @domain: IRQ domain
|
||||
* @irq: Virtual IRQ number
|
||||
* @hwirq: HW interrupt number
|
||||
*
|
||||
* Return: Always returns 0.
|
||||
*/
|
||||
static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
|
||||
irq_hw_number_t hwirq)
|
||||
{
|
||||
irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
|
||||
irq_set_chip_data(irq, domain->host_data);
|
||||
set_irq_flags(irq, IRQF_VALID);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* INTx IRQ Domain operations */
|
||||
static const struct irq_domain_ops intx_domain_ops = {
|
||||
.map = xilinx_pcie_intx_map,
|
||||
};
|
||||
|
||||
/* PCIe HW Functions */
|
||||
|
||||
/**
|
||||
* xilinx_pcie_intr_handler - Interrupt Service Handler
|
||||
* @irq: IRQ number
|
||||
* @data: PCIe port information
|
||||
*
|
||||
* Return: IRQ_HANDLED on success and IRQ_NONE on failure
|
||||
*/
|
||||
static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
|
||||
{
|
||||
struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
|
||||
u32 val, mask, status, msi_data;
|
||||
|
||||
/* Read interrupt decode and mask registers */
|
||||
val = pcie_read(port, XILINX_PCIE_REG_IDR);
|
||||
mask = pcie_read(port, XILINX_PCIE_REG_IMR);
|
||||
|
||||
status = val & mask;
|
||||
if (!status)
|
||||
return IRQ_NONE;
|
||||
|
||||
if (status & XILINX_PCIE_INTR_LINK_DOWN)
|
||||
dev_warn(port->dev, "Link Down\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_ECRC_ERR)
|
||||
dev_warn(port->dev, "ECRC failed\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_STR_ERR)
|
||||
dev_warn(port->dev, "Streaming error\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_HOT_RESET)
|
||||
dev_info(port->dev, "Hot reset\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
|
||||
dev_warn(port->dev, "ECAM access timeout\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_CORRECTABLE) {
|
||||
dev_warn(port->dev, "Correctable error message\n");
|
||||
xilinx_pcie_clear_err_interrupts(port);
|
||||
}
|
||||
|
||||
if (status & XILINX_PCIE_INTR_NONFATAL) {
|
||||
dev_warn(port->dev, "Non fatal error message\n");
|
||||
xilinx_pcie_clear_err_interrupts(port);
|
||||
}
|
||||
|
||||
if (status & XILINX_PCIE_INTR_FATAL) {
|
||||
dev_warn(port->dev, "Fatal error message\n");
|
||||
xilinx_pcie_clear_err_interrupts(port);
|
||||
}
|
||||
|
||||
if (status & XILINX_PCIE_INTR_INTX) {
|
||||
/* INTx interrupt received */
|
||||
val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
|
||||
|
||||
/* Check whether interrupt valid */
|
||||
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
|
||||
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/* Clear interrupt FIFO register 1 */
|
||||
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
|
||||
XILINX_PCIE_REG_RPIFR1);
|
||||
|
||||
/* Handle INTx Interrupt */
|
||||
val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
|
||||
XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
|
||||
generic_handle_irq(irq_find_mapping(port->irq_domain, val));
|
||||
}
|
||||
|
||||
if (status & XILINX_PCIE_INTR_MSI) {
|
||||
/* MSI Interrupt */
|
||||
val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
|
||||
|
||||
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
|
||||
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
|
||||
msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
|
||||
XILINX_PCIE_RPIFR2_MSG_DATA;
|
||||
|
||||
/* Clear interrupt FIFO register 1 */
|
||||
pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
|
||||
XILINX_PCIE_REG_RPIFR1);
|
||||
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
/* Handle MSI Interrupt */
|
||||
generic_handle_irq(msi_data);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
|
||||
dev_warn(port->dev, "Slave unsupported request\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_SLV_UNEXP)
|
||||
dev_warn(port->dev, "Slave unexpected completion\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_SLV_COMPL)
|
||||
dev_warn(port->dev, "Slave completion timeout\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_SLV_ERRP)
|
||||
dev_warn(port->dev, "Slave Error Poison\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_SLV_CMPABT)
|
||||
dev_warn(port->dev, "Slave Completer Abort\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
|
||||
dev_warn(port->dev, "Slave Illegal Burst\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_MST_DECERR)
|
||||
dev_warn(port->dev, "Master decode error\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_MST_SLVERR)
|
||||
dev_warn(port->dev, "Master slave error\n");
|
||||
|
||||
if (status & XILINX_PCIE_INTR_MST_ERRP)
|
||||
dev_warn(port->dev, "Master error poison\n");
|
||||
|
||||
/* Clear the Interrupt Decode register */
|
||||
pcie_write(port, status, XILINX_PCIE_REG_IDR);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_free_irq_domain - Free IRQ domain
|
||||
* @port: PCIe port information
|
||||
*/
|
||||
static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
|
||||
{
|
||||
int i;
|
||||
u32 irq, num_irqs;
|
||||
|
||||
/* Free IRQ Domain */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
|
||||
free_pages(port->msi_pages, 0);
|
||||
|
||||
num_irqs = XILINX_NUM_MSI_IRQS;
|
||||
} else {
|
||||
/* INTx */
|
||||
num_irqs = 4;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_irqs; i++) {
|
||||
irq = irq_find_mapping(port->irq_domain, i);
|
||||
if (irq > 0)
|
||||
irq_dispose_mapping(irq);
|
||||
}
|
||||
|
||||
irq_domain_remove(port->irq_domain);
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_init_irq_domain - Initialize IRQ domain
|
||||
* @port: PCIe port information
|
||||
*
|
||||
* Return: '0' on success and error value on failure
|
||||
*/
|
||||
static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
|
||||
{
|
||||
struct device *dev = port->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct device_node *pcie_intc_node;
|
||||
|
||||
/* Setup INTx */
|
||||
pcie_intc_node = of_get_next_child(node, NULL);
|
||||
if (!pcie_intc_node) {
|
||||
dev_err(dev, "No PCIe Intc node found\n");
|
||||
return PTR_ERR(pcie_intc_node);
|
||||
}
|
||||
|
||||
port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
|
||||
&intx_domain_ops,
|
||||
port);
|
||||
if (!port->irq_domain) {
|
||||
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
||||
return PTR_ERR(port->irq_domain);
|
||||
}
|
||||
|
||||
/* Setup MSI */
|
||||
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||||
port->irq_domain = irq_domain_add_linear(node,
|
||||
XILINX_NUM_MSI_IRQS,
|
||||
&msi_domain_ops,
|
||||
&xilinx_pcie_msi_chip);
|
||||
if (!port->irq_domain) {
|
||||
dev_err(dev, "Failed to get a MSI IRQ domain\n");
|
||||
return PTR_ERR(port->irq_domain);
|
||||
}
|
||||
|
||||
xilinx_pcie_enable_msi(port);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_init_port - Initialize hardware
|
||||
* @port: PCIe port information
|
||||
*/
|
||||
static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
|
||||
{
|
||||
if (xilinx_pcie_link_is_up(port))
|
||||
dev_info(port->dev, "PCIe Link is UP\n");
|
||||
else
|
||||
dev_info(port->dev, "PCIe Link is DOWN\n");
|
||||
|
||||
/* Disable all interrupts */
|
||||
pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
|
||||
XILINX_PCIE_REG_IMR);
|
||||
|
||||
/* Clear pending interrupts */
|
||||
pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
|
||||
XILINX_PCIE_IMR_ALL_MASK,
|
||||
XILINX_PCIE_REG_IDR);
|
||||
|
||||
/* Enable all interrupts */
|
||||
pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
|
||||
|
||||
/* Enable the Bridge enable bit */
|
||||
pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
|
||||
XILINX_PCIE_REG_RPSC_BEN,
|
||||
XILINX_PCIE_REG_RPSC);
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_setup - Setup memory resources
|
||||
* @nr: Bus number
|
||||
* @sys: Per controller structure
|
||||
*
|
||||
* Return: '1' on success and error value on failure
|
||||
*/
|
||||
static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
|
||||
{
|
||||
struct xilinx_pcie_port *port = sys_to_pcie(sys);
|
||||
|
||||
list_splice_init(&port->resources, &sys->resources);
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_scan_bus - Scan PCIe bus for devices
|
||||
* @nr: Bus number
|
||||
* @sys: Per controller structure
|
||||
*
|
||||
* Return: Valid Bus pointer on success and NULL on failure
|
||||
*/
|
||||
static struct pci_bus *xilinx_pcie_scan_bus(int nr, struct pci_sys_data *sys)
|
||||
{
|
||||
struct xilinx_pcie_port *port = sys_to_pcie(sys);
|
||||
struct pci_bus *bus;
|
||||
|
||||
port->root_busno = sys->busnr;
|
||||
bus = pci_scan_root_bus(port->dev, sys->busnr, &xilinx_pcie_ops,
|
||||
sys, &sys->resources);
|
||||
|
||||
return bus;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
|
||||
* @port: PCIe port information
|
||||
*
|
||||
* Return: '0' on success and error value on failure
|
||||
*/
|
||||
static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
|
||||
{
|
||||
struct device *dev = port->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct resource *mem;
|
||||
resource_size_t offset;
|
||||
struct of_pci_range_parser parser;
|
||||
struct of_pci_range range;
|
||||
struct pci_host_bridge_window *win;
|
||||
int err = 0, mem_resno = 0;
|
||||
|
||||
/* Get the ranges */
|
||||
if (of_pci_range_parser_init(&parser, node)) {
|
||||
dev_err(dev, "missing \"ranges\" property\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Parse the ranges and add the resources found to the list */
|
||||
for_each_of_pci_range(&parser, &range) {
|
||||
|
||||
if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
|
||||
dev_err(dev, "Maximum memory resources exceeded\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
|
||||
if (!mem) {
|
||||
err = -ENOMEM;
|
||||
goto free_resources;
|
||||
}
|
||||
|
||||
of_pci_range_to_resource(&range, node, mem);
|
||||
|
||||
switch (mem->flags & IORESOURCE_TYPE_BITS) {
|
||||
case IORESOURCE_MEM:
|
||||
offset = range.cpu_addr - range.pci_addr;
|
||||
mem_resno++;
|
||||
break;
|
||||
default:
|
||||
err = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
if (err < 0) {
|
||||
dev_warn(dev, "Invalid resource found %pR\n", mem);
|
||||
continue;
|
||||
}
|
||||
|
||||
err = request_resource(&iomem_resource, mem);
|
||||
if (err)
|
||||
goto free_resources;
|
||||
|
||||
pci_add_resource_offset(&port->resources, mem, offset);
|
||||
}
|
||||
|
||||
/* Get the bus range */
|
||||
if (of_pci_parse_bus_range(node, &port->bus_range)) {
|
||||
u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
|
||||
u8 last;
|
||||
|
||||
last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
|
||||
XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
|
||||
|
||||
port->bus_range = (struct resource) {
|
||||
.name = node->name,
|
||||
.start = 0,
|
||||
.end = last,
|
||||
.flags = IORESOURCE_BUS,
|
||||
};
|
||||
}
|
||||
|
||||
/* Register bus resource */
|
||||
pci_add_resource(&port->resources, &port->bus_range);
|
||||
|
||||
return 0;
|
||||
|
||||
free_resources:
|
||||
release_child_resources(&iomem_resource);
|
||||
list_for_each_entry(win, &port->resources, list)
|
||||
devm_kfree(dev, win->res);
|
||||
pci_free_resource_list(&port->resources);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_parse_dt - Parse Device tree
|
||||
* @port: PCIe port information
|
||||
*
|
||||
* Return: '0' on success and error value on failure
|
||||
*/
|
||||
static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
|
||||
{
|
||||
struct device *dev = port->dev;
|
||||
struct device_node *node = dev->of_node;
|
||||
struct resource regs;
|
||||
const char *type;
|
||||
int err;
|
||||
|
||||
type = of_get_property(node, "device_type", NULL);
|
||||
if (!type || strcmp(type, "pci")) {
|
||||
dev_err(dev, "invalid \"device_type\" %s\n", type);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
err = of_address_to_resource(node, 0, ®s);
|
||||
if (err) {
|
||||
dev_err(dev, "missing \"reg\" property\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
port->reg_base = devm_ioremap_resource(dev, ®s);
|
||||
if (IS_ERR(port->reg_base))
|
||||
return PTR_ERR(port->reg_base);
|
||||
|
||||
port->irq = irq_of_parse_and_map(node, 0);
|
||||
err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
|
||||
IRQF_SHARED, "xilinx-pcie", port);
|
||||
if (err) {
|
||||
dev_err(dev, "unable to request irq %d\n", port->irq);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_probe - Probe function
|
||||
* @pdev: Platform device pointer
|
||||
*
|
||||
* Return: '0' on success and error value on failure
|
||||
*/
|
||||
static int xilinx_pcie_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct xilinx_pcie_port *port;
|
||||
struct hw_pci hw;
|
||||
struct device *dev = &pdev->dev;
|
||||
int err;
|
||||
|
||||
if (!dev->of_node)
|
||||
return -ENODEV;
|
||||
|
||||
port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
|
||||
if (!port)
|
||||
return -ENOMEM;
|
||||
|
||||
port->dev = dev;
|
||||
|
||||
err = xilinx_pcie_parse_dt(port);
|
||||
if (err) {
|
||||
dev_err(dev, "Parsing DT failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
xilinx_pcie_init_port(port);
|
||||
|
||||
err = xilinx_pcie_init_irq_domain(port);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed creating IRQ Domain\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
/*
|
||||
* Parse PCI ranges, configuration bus range and
|
||||
* request their resources
|
||||
*/
|
||||
INIT_LIST_HEAD(&port->resources);
|
||||
err = xilinx_pcie_parse_and_add_res(port);
|
||||
if (err) {
|
||||
dev_err(dev, "Failed adding resources\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, port);
|
||||
|
||||
/* Register the device */
|
||||
memset(&hw, 0, sizeof(hw));
|
||||
hw = (struct hw_pci) {
|
||||
.nr_controllers = 1,
|
||||
.private_data = (void **)&port,
|
||||
.setup = xilinx_pcie_setup,
|
||||
.map_irq = of_irq_parse_and_map_pci,
|
||||
.add_bus = xilinx_pcie_add_bus,
|
||||
.scan = xilinx_pcie_scan_bus,
|
||||
.ops = &xilinx_pcie_ops,
|
||||
};
|
||||
pci_common_init_dev(dev, &hw);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_pcie_remove - Remove function
|
||||
* @pdev: Platform device pointer
|
||||
*
|
||||
* Return: '0' always
|
||||
*/
|
||||
static int xilinx_pcie_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
|
||||
|
||||
xilinx_pcie_free_irq_domain(port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct of_device_id xilinx_pcie_of_match[] = {
|
||||
{ .compatible = "xlnx,axi-pcie-host-1.00.a", },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct platform_driver xilinx_pcie_driver = {
|
||||
.driver = {
|
||||
.name = "xilinx-pcie",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = xilinx_pcie_of_match,
|
||||
.suppress_bind_attrs = true,
|
||||
},
|
||||
.probe = xilinx_pcie_probe,
|
||||
.remove = xilinx_pcie_remove,
|
||||
};
|
||||
module_platform_driver(xilinx_pcie_driver);
|
||||
|
||||
MODULE_AUTHOR("Xilinx Inc");
|
||||
MODULE_DESCRIPTION("Xilinx AXI PCIe driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Loading…
Reference in New Issue