irqchip: renesas-intc-irqpin: DT binding for sense bitfield width
Most Renesas irqpin controllers have 4-bit sense fields, however, some have different widths. This patch adds a DT binding to optionally specify such non-standard values. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -0,0 +1,14 @@
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DT bindings for the R-/SH-Mobile irqpin controller
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Required properties:
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- compatible: has to be "renesas,intc-irqpin"
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- #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
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interrupts.txt in this directory
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Optional properties:
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- any properties, listed in interrupts.txt, and any standard resource allocation
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properties
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- sense-bitfield-width: width of a single sense bitfield in the SENSE register,
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if different from the default 4 bits
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@ -18,6 +18,7 @@
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*/
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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@ -349,6 +350,9 @@ static int intc_irqpin_probe(struct platform_device *pdev)
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/* deal with driver instance configuration */
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if (pdata)
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memcpy(&p->config, pdata, sizeof(*pdata));
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else
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of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
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&p->config.sense_bitfield_width);
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if (!p->config.sense_bitfield_width)
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p->config.sense_bitfield_width = 4; /* default to 4 bits */
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