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OMAP3: PM: Wait for SDRC ready iso a blind delay 

This patch improves the wakeup SRAM code polling the SDRC to become ready
instead of just waiting for a fixed amount of time.

Signed-off-by: Peter 'p2' De Schrijver <peter.de-schrijver@nokia.com>
Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Peter 'p2' De Schrijver 2009-01-16 18:53:48 +02:00 committed by Kevin Hilman
parent 867d320b6c
commit 89139dce8a
1 changed files with 36 additions and 12 deletions
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48
arch/arm/mach-omap2/sleep34xx.S
View File

@ -29,6 +29,7 @@
#include <mach/io.h> #include <mach/io.h>
#include <plat/control.h> #include <plat/control.h>
#include "cm.h"
#include "prm.h" #include "prm.h"
#include "sdrc.h" #include "sdrc.h"
@ -38,6 +39,7 @@
#define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \ #define PM_PREPWSTST_MPU_V OMAP34XX_PRM_REGADDR(MPU_MOD, \
OMAP3430_PM_PREPWSTST) OMAP3430_PM_PREPWSTST)
#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL #define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + PM_PWSTCTRL
#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
#define SRAM_BASE_P 0x40200000 #define SRAM_BASE_P 0x40200000
#define CONTROL_STAT 0x480022F0 #define CONTROL_STAT 0x480022F0
#define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is #define SCRATCHPAD_MEM_OFFS 0x310 /* Move this as correct place is
@ -52,6 +54,8 @@
#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1) #define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1) #define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1) #define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
.text .text
/* Function call to get the restore pointer for resume from OFF */ /* Function call to get the restore pointer for resume from OFF */
@ -187,7 +191,7 @@ loop:
nop nop
nop nop
nop nop
bl i_dll_wait bl wait_sdrc_ok
ldmfd sp!, {r0-r12, pc} @ restore regs and return ldmfd sp!, {r0-r12, pc} @ restore regs and return
restore_es3: restore_es3:
@ -539,21 +543,41 @@ skip_l2_inval:
nop nop
nop nop
nop nop
bl i_dll_wait bl wait_sdrc_ok
/* restore regs and return */ /* restore regs and return */
ldmfd sp!, {r0-r12, pc} ldmfd sp!, {r0-r12, pc}
i_dll_wait: /* Make sure SDRC accesses are ok */
ldr r4, clk_stabilize_delay wait_sdrc_ok:
ldr r4, cm_idlest1_core
ldr r5, [r4]
and r5, r5, #0x2
cmp r5, #0
bne wait_sdrc_ok
ldr r4, sdrc_power
ldr r5, [r4]
bic r5, r5, #0x40
str r5, [r4]
wait_dll_lock:
/* Is dll in lock mode? */
ldr r4, sdrc_dlla_ctrl
ldr r5, [r4]
tst r5, #0x4
bxne lr
/* wait till dll locks */
ldr r4, sdrc_dlla_status
ldr r5, [r4]
and r5, r5, #0x4
cmp r5, #0x4
bne wait_dll_lock
bx lr
i_dll_delay: cm_idlest1_core:
subs r4, r4, #0x1 .word CM_IDLEST1_CORE_V
bne i_dll_delay sdrc_dlla_status:
ldr r4, sdrc_power .word SDRC_DLLA_STATUS_V
ldr r5, [r4] sdrc_dlla_ctrl:
bic r5, r5, #0x40 .word SDRC_DLLA_CTRL_V
str r5, [r4]
bx lr
pm_prepwstst_core: pm_prepwstst_core:
.word PM_PREPWSTST_CORE_V .word PM_PREPWSTST_CORE_V
pm_prepwstst_core_p: pm_prepwstst_core_p: