drm/radeon: programm the VCE fw BAR as well
Otherwise the VCE firmware needs to be in the first 256MB of VRAM. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2129,6 +2129,7 @@
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#define VCE_UENC_REG_CLOCK_GATING 0x207c0
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#define VCE_UENC_REG_CLOCK_GATING 0x207c0
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#define VCE_SYS_INT_EN 0x21300
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#define VCE_SYS_INT_EN 0x21300
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# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
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# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
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#define VCE_LMI_VCPU_CACHE_40BIT_BAR 0x2145c
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#define VCE_LMI_CTRL2 0x21474
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#define VCE_LMI_CTRL2 0x21474
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#define VCE_LMI_CTRL 0x21498
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#define VCE_LMI_CTRL 0x21498
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#define VCE_LMI_VM_CTRL 0x214a0
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#define VCE_LMI_VM_CTRL 0x214a0
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@ -156,6 +156,9 @@ int vce_v2_0_resume(struct radeon_device *rdev)
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_SWAP_CNTL1, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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WREG32(VCE_LMI_VM_CTRL, 0);
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WREG32(VCE_LMI_VCPU_CACHE_40BIT_BAR, addr >> 8);
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addr &= 0xff;
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size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
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size = RADEON_GPU_PAGE_ALIGN(rdev->vce_fw->size);
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_OFFSET0, addr & 0x7fffffff);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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WREG32(VCE_VCPU_CACHE_SIZE0, size);
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