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drm/amd/pp: Add rv_read_arg_from_smc to smu backend function table 

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu 2018-03-09 18:57:37 +08:00 committed by Alex Deucher
parent 52911e0356
commit 88c1a70d58
3 changed files with 11 additions and 14 deletions
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12
drivers/gpu/drm/amd/powerplay/hwmgr/rv_hwmgr.c
View File

@ -386,11 +386,11 @@ static int rv_populate_clock_table(struct pp_hwmgr *hwmgr)
ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
rv_read_arg_from_smc(hwmgr, &result);
result = smum_get_argument(hwmgr);
rv_data->gfx_min_freq_limit = result * 100;
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
rv_read_arg_from_smc(hwmgr, &result);
result = smum_get_argument(hwmgr);
rv_data->gfx_max_freq_limit = result * 100;
return 0;
@ -726,7 +726,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
switch (type) {
case PP_SCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
rv_read_arg_from_smc(hwmgr, &now);
now = smum_get_argument(hwmgr);
size += sprintf(buf + size, "0: %uMhz %s\n",
data->gfx_min_freq_limit / 100,
@ -739,7 +739,7 @@ static int rv_print_clock_levels(struct pp_hwmgr *hwmgr,
break;
case PP_MCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
rv_read_arg_from_smc(hwmgr, &now);
now = smum_get_argument(hwmgr);
for (i = 0; i < mclk_table->count; i++)
size += sprintf(buf + size, "%d: %uMhz %s\n",
@ -971,14 +971,14 @@ static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
switch (idx) {
case AMDGPU_PP_SENSOR_GFX_SCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
rv_read_arg_from_smc(hwmgr, &sclk);
sclk = smum_get_argument(hwmgr);
/* in units of 10KHZ */
*((uint32_t *)value) = sclk * 100;
*size = 4;
break;
case AMDGPU_PP_SENSOR_GFX_MCLK:
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
rv_read_arg_from_smc(hwmgr, &mclk);
mclk = smum_get_argument(hwmgr);
/* in units of 10KHZ */
*((uint32_t *)value) = mclk * 100;
*size = 4;

12
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.c
View File

@ -72,16 +72,14 @@ int rv_send_msg_to_smc_without_waiting(struct pp_hwmgr *hwmgr,
return 0;
}
int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg)
static int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr)
{
uint32_t reg;
reg = soc15_get_register_offset(MP1_HWID, 0,
mmMP1_SMN_C2PMSG_82_BASE_IDX, mmMP1_SMN_C2PMSG_82);
*arg = cgs_read_register(hwmgr->device, reg);
return 0;
return cgs_read_register(hwmgr->device, reg);
}
int rv_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
@ -190,8 +188,7 @@ static int rv_verify_smc_interface(struct pp_hwmgr *hwmgr)
rv_send_msg_to_smc(hwmgr,
PPSMC_MSG_GetDriverIfVersion);
rv_read_arg_from_smc(hwmgr,
&smc_driver_if_version);
smc_driver_if_version = rv_read_arg_from_smc(hwmgr);
if (smc_driver_if_version != SMU10_DRIVER_IF_VERSION) {
pr_err("Attempt to read SMC IF Version Number Failed!\n");
@ -253,7 +250,7 @@ static int rv_start_smu(struct pp_hwmgr *hwmgr)
struct cgs_firmware_info info = {0};
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetSmuVersion);
rv_read_arg_from_smc(hwmgr, &hwmgr->smu_version);
hwmgr->smu_version = rv_read_arg_from_smc(hwmgr);
info.version = hwmgr->smu_version >> 8;
cgs_get_firmware_info(hwmgr->device, CGS_UCODE_ID_SMU, &info);
@ -330,6 +327,7 @@ const struct pp_smumgr_func rv_smu_funcs = {
.send_msg_to_smc_with_parameter = &rv_send_msg_to_smc_with_parameter,
.download_pptable_settings = NULL,
.upload_pptable_settings = NULL,
.get_argument = rv_read_arg_from_smc,
};

1
drivers/gpu/drm/amd/powerplay/smumgr/rv_smumgr.h
View File

@ -50,7 +50,6 @@ struct rv_smumgr {
struct smu_table_array smu_tables;
};
int rv_read_arg_from_smc(struct pp_hwmgr *hwmgr, uint32_t *arg);
int rv_copy_table_from_smc(struct pp_hwmgr *hwmgr,
uint8_t *table, int16_t table_id);
int rv_copy_table_to_smc(struct pp_hwmgr *hwmgr,