Merge tag 'drm-intel-fixes-2016-06-30' of git://anongit.freedesktop.org/drm-intel into drm-fixes
here's a batch of i915 fixes for 4.7. * tag 'drm-intel-fixes-2016-06-30' of git://anongit.freedesktop.org/drm-intel: drm/i915: Fix missing unlock on error in i915_ppgtt_info() drm/i915: Removing PCI IDs that are no longer listed as Kabylake. drm/i915: Add more Kabylake PCI IDs. drm/i915: Avoid early timeout during AUX transfers drm/i915/hsw: Avoid early timeout during LCPLL disable/restore drm/i915/lpt: Avoid early timeout during FDI PHY reset drm/i915/bxt: Avoid early timeout during PLL enable drm/i915: Refresh cached DP port register value on resume
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commit
88c087109b
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@ -2365,16 +2365,16 @@ static int i915_ppgtt_info(struct seq_file *m, void *data)
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task = get_pid_task(file->pid, PIDTYPE_PID);
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if (!task) {
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ret = -ESRCH;
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goto out_put;
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goto out_unlock;
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}
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seq_printf(m, "\nproc: %s\n", task->comm);
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put_task_struct(task);
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idr_for_each(&file_priv->context_idr, per_file_ctx,
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(void *)(unsigned long)m);
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}
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out_unlock:
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mutex_unlock(&dev->filelist_mutex);
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out_put:
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intel_runtime_pm_put(dev_priv);
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mutex_unlock(&dev->struct_mutex);
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@ -8447,7 +8447,7 @@ static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
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tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
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I915_WRITE(SOUTH_CHICKEN2, tmp);
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if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
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if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
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FDI_MPHY_IOSFSB_RESET_STATUS, 100))
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DRM_ERROR("FDI mPHY reset assert timeout\n");
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@ -8455,7 +8455,7 @@ static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
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tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
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I915_WRITE(SOUTH_CHICKEN2, tmp);
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if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
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if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
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FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
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DRM_ERROR("FDI mPHY reset de-assert timeout\n");
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}
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@ -9440,7 +9440,7 @@ static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
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val |= LCPLL_CD_SOURCE_FCLK;
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I915_WRITE(LCPLL_CTL, val);
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if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
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if (wait_for_us(I915_READ(LCPLL_CTL) &
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LCPLL_CD_SOURCE_FCLK_DONE, 1))
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DRM_ERROR("Switching to FCLK failed\n");
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@ -9514,7 +9514,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
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val &= ~LCPLL_CD_SOURCE_FCLK;
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I915_WRITE(LCPLL_CTL, val);
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if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
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if (wait_for_us((I915_READ(LCPLL_CTL) &
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LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
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DRM_ERROR("Switching back to LCPLL failed\n");
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}
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@ -663,7 +663,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
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done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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msecs_to_jiffies_timeout(10));
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else
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done = wait_for_atomic(C, 10) == 0;
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done = wait_for(C, 10) == 0;
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if (!done)
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DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
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has_aux_irq);
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@ -4899,13 +4899,15 @@ static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
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void intel_dp_encoder_reset(struct drm_encoder *encoder)
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{
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struct intel_dp *intel_dp;
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struct drm_i915_private *dev_priv = to_i915(encoder->dev);
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struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
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if (!HAS_DDI(dev_priv))
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intel_dp->DP = I915_READ(intel_dp->output_reg);
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if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
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return;
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intel_dp = enc_to_intel_dp(encoder);
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pps_lock(intel_dp);
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/*
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@ -1377,8 +1377,8 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
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I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
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POSTING_READ(BXT_PORT_PLL_ENABLE(port));
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if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
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PORT_PLL_LOCK), 200))
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if (wait_for_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
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200))
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DRM_ERROR("PLL %d not locked\n", port);
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/*
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@ -309,6 +309,7 @@
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INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \
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INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \
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INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \
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INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \
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INTEL_VGA_DEVICE(0x590B, info), /* Halo GT1 */ \
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INTEL_VGA_DEVICE(0x590A, info) /* SRV GT1 */
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@ -322,15 +323,12 @@
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INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */
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#define INTEL_KBL_GT3_IDS(info) \
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INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \
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INTEL_VGA_DEVICE(0x5926, info), /* ULT GT3 */ \
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INTEL_VGA_DEVICE(0x592B, info), /* Halo GT3 */ \
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INTEL_VGA_DEVICE(0x592A, info) /* SRV GT3 */
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INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */
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#define INTEL_KBL_GT4_IDS(info) \
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INTEL_VGA_DEVICE(0x5932, info), /* DT GT4 */ \
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INTEL_VGA_DEVICE(0x593B, info), /* Halo GT4 */ \
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INTEL_VGA_DEVICE(0x593A, info), /* SRV GT4 */ \
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INTEL_VGA_DEVICE(0x593D, info) /* WKS GT4 */
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INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */
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#define INTEL_KBL_IDS(info) \
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INTEL_KBL_GT1_IDS(info), \
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