phy: intel: Add Keem Bay eMMC PHY support
Add support for eMMC PHY on Intel Keem Bay SoC. Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200913235522.4316-4-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Wan Ahmad Zainie
Vinod Koul
parent
9580b22aca
commit
885c4f4d6c
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@ -2,6 +2,18 @@
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#
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# Phy drivers for Intel platforms
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#
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config PHY_INTEL_KEEMBAY_EMMC
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tristate "Intel Keem Bay EMMC PHY driver"
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depends on (OF && ARM64) || COMPILE_TEST
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depends on HAS_IOMEM
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select GENERIC_PHY
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select REGMAP_MMIO
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help
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Choose this option if you have an Intel Keem Bay SoC.
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To compile this driver as a module, choose M here: the module
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will be called phy-keembay-emmc.ko.
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config PHY_INTEL_LGM_COMBO
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bool "Intel Lightning Mountain ComboPHY driver"
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depends on X86 || COMPILE_TEST
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@ -1,3 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_PHY_INTEL_KEEMBAY_EMMC) += phy-intel-keembay-emmc.o
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obj-$(CONFIG_PHY_INTEL_LGM_COMBO) += phy-intel-lgm-combo.o
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obj-$(CONFIG_PHY_INTEL_LGM_EMMC) += phy-intel-lgm-emmc.o
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@ -0,0 +1,307 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Keem Bay eMMC PHY driver
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* Copyright (C) 2020 Intel Corporation
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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/* eMMC/SD/SDIO core/phy configuration registers */
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#define PHY_CFG_0 0x24
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#define SEL_DLY_TXCLK_MASK BIT(29)
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#define OTAP_DLY_ENA_MASK BIT(27)
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#define OTAP_DLY_SEL_MASK GENMASK(26, 23)
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#define DLL_EN_MASK BIT(10)
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#define PWR_DOWN_MASK BIT(0)
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#define PHY_CFG_2 0x2c
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#define SEL_FREQ_MASK GENMASK(12, 10)
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#define PHY_STAT 0x40
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#define CAL_DONE_MASK BIT(6)
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#define IS_CALDONE(x) ((x) & CAL_DONE_MASK)
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#define DLL_RDY_MASK BIT(5)
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#define IS_DLLRDY(x) ((x) & DLL_RDY_MASK)
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/* From ACS_eMMC51_16nFFC_RO1100_Userguide_v1p0.pdf p17 */
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#define FREQSEL_200M_170M 0x0
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#define FREQSEL_170M_140M 0x1
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#define FREQSEL_140M_110M 0x2
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#define FREQSEL_110M_80M 0x3
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#define FREQSEL_80M_50M 0x4
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struct keembay_emmc_phy {
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struct regmap *syscfg;
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struct clk *emmcclk;
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};
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static const struct regmap_config keembay_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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static int keembay_emmc_phy_power(struct phy *phy, bool on_off)
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{
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struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
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unsigned int caldone;
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unsigned int dllrdy;
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unsigned int freqsel;
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unsigned int mhz;
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int ret;
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/*
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* Keep phyctrl_pdb and phyctrl_endll low to allow
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* initialization of CALIO state M/C DFFs
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*/
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
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FIELD_PREP(PWR_DOWN_MASK, 0));
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if (ret) {
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dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
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return ret;
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}
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
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FIELD_PREP(DLL_EN_MASK, 0));
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if (ret) {
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dev_err(&phy->dev, "turn off the dll failed: %d\n", ret);
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return ret;
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}
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/* Already finish power off above */
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if (!on_off)
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return 0;
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mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000);
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if (mhz <= 200 && mhz >= 170)
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freqsel = FREQSEL_200M_170M;
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else if (mhz <= 170 && mhz >= 140)
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freqsel = FREQSEL_170M_140M;
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else if (mhz <= 140 && mhz >= 110)
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freqsel = FREQSEL_140M_110M;
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else if (mhz <= 110 && mhz >= 80)
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freqsel = FREQSEL_110M_80M;
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else if (mhz <= 80 && mhz >= 50)
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freqsel = FREQSEL_80M_50M;
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else
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freqsel = 0x0;
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if (mhz < 50 || mhz > 200)
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dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz);
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/*
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* According to the user manual, calpad calibration
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* cycle takes more than 2us without the minimal recommended
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* value, so we may need a little margin here
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*/
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udelay(5);
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, PWR_DOWN_MASK,
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FIELD_PREP(PWR_DOWN_MASK, 1));
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if (ret) {
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dev_err(&phy->dev, "CALIO power down bar failed: %d\n", ret);
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return ret;
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}
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/*
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* According to the user manual, it asks driver to wait 5us for
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* calpad busy trimming. However it is documented that this value is
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* PVT(A.K.A. process, voltage and temperature) relevant, so some
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* failure cases are found which indicates we should be more tolerant
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* to calpad busy trimming.
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*/
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ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
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caldone, IS_CALDONE(caldone),
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0, 50);
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if (ret) {
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dev_err(&phy->dev, "caldone failed, ret=%d\n", ret);
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return ret;
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}
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/* Set the frequency of the DLL operation */
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_2, SEL_FREQ_MASK,
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FIELD_PREP(SEL_FREQ_MASK, freqsel));
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if (ret) {
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dev_err(&phy->dev, "set the frequency of dll failed:%d\n", ret);
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return ret;
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}
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/* Turn on the DLL */
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, DLL_EN_MASK,
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FIELD_PREP(DLL_EN_MASK, 1));
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if (ret) {
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dev_err(&phy->dev, "turn on the dll failed: %d\n", ret);
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return ret;
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}
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/*
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* We turned on the DLL even though the rate was 0 because we the
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* clock might be turned on later. ...but we can't wait for the DLL
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* to lock when the rate is 0 because it will never lock with no
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* input clock.
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*
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* Technically we should be checking the lock later when the clock
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* is turned on, but for now we won't.
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*/
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if (mhz == 0)
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return 0;
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/*
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* After enabling analog DLL circuits docs say that we need 10.2 us if
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* our source clock is at 50 MHz and that lock time scales linearly
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* with clock speed. If we are powering on the PHY and the card clock
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* is super slow (like 100kHz) this could take as long as 5.1 ms as
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* per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
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* hopefully we won't be running at 100 kHz, but we should still make
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* sure we wait long enough.
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*
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* NOTE: There appear to be corner cases where the DLL seems to take
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* extra long to lock for reasons that aren't understood. In some
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* extreme cases we've seen it take up to over 10ms (!). We'll be
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* generous and give it 50ms.
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*/
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ret = regmap_read_poll_timeout(priv->syscfg, PHY_STAT,
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dllrdy, IS_DLLRDY(dllrdy),
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0, 50 * USEC_PER_MSEC);
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if (ret)
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dev_err(&phy->dev, "dllrdy failed, ret=%d\n", ret);
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return ret;
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}
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static int keembay_emmc_phy_init(struct phy *phy)
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{
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struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
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/*
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* We purposely get the clock here and not in probe to avoid the
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* circular dependency problem. We expect:
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* - PHY driver to probe
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* - SDHCI driver to start probe
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* - SDHCI driver to register it's clock
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* - SDHCI driver to get the PHY
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* - SDHCI driver to init the PHY
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*
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* The clock is optional, so upon any error just return it like
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* any other error to user.
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*/
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priv->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
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return PTR_ERR_OR_ZERO(priv->emmcclk);
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}
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static int keembay_emmc_phy_exit(struct phy *phy)
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{
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struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
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clk_put(priv->emmcclk);
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return 0;
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};
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static int keembay_emmc_phy_power_on(struct phy *phy)
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{
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struct keembay_emmc_phy *priv = phy_get_drvdata(phy);
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int ret;
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/* Delay chain based txclk: enable */
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, SEL_DLY_TXCLK_MASK,
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FIELD_PREP(SEL_DLY_TXCLK_MASK, 1));
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if (ret) {
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dev_err(&phy->dev, "ERROR: delay chain txclk set: %d\n", ret);
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return ret;
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}
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/* Output tap delay: enable */
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_ENA_MASK,
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FIELD_PREP(OTAP_DLY_ENA_MASK, 1));
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if (ret) {
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dev_err(&phy->dev, "ERROR: output tap delay set: %d\n", ret);
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return ret;
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}
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/* Output tap delay */
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ret = regmap_update_bits(priv->syscfg, PHY_CFG_0, OTAP_DLY_SEL_MASK,
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FIELD_PREP(OTAP_DLY_SEL_MASK, 2));
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if (ret) {
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dev_err(&phy->dev, "ERROR: output tap delay select: %d\n", ret);
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return ret;
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}
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/* Power up eMMC phy analog blocks */
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return keembay_emmc_phy_power(phy, true);
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}
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static int keembay_emmc_phy_power_off(struct phy *phy)
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{
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/* Power down eMMC phy analog blocks */
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return keembay_emmc_phy_power(phy, false);
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}
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static const struct phy_ops ops = {
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.init = keembay_emmc_phy_init,
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.exit = keembay_emmc_phy_exit,
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.power_on = keembay_emmc_phy_power_on,
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.power_off = keembay_emmc_phy_power_off,
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.owner = THIS_MODULE,
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};
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static int keembay_emmc_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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struct keembay_emmc_phy *priv;
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struct phy *generic_phy;
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struct phy_provider *phy_provider;
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void __iomem *base;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(base))
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return PTR_ERR(base);
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priv->syscfg = devm_regmap_init_mmio(dev, base, &keembay_regmap_config);
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if (IS_ERR(priv->syscfg))
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return PTR_ERR(priv->syscfg);
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generic_phy = devm_phy_create(dev, np, &ops);
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if (IS_ERR(generic_phy))
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return dev_err_probe(dev, PTR_ERR(generic_phy),
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"failed to create PHY\n");
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phy_set_drvdata(generic_phy, priv);
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phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
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return PTR_ERR_OR_ZERO(phy_provider);
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}
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static const struct of_device_id keembay_emmc_phy_dt_ids[] = {
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{ .compatible = "intel,keembay-emmc-phy" },
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{}
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};
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MODULE_DEVICE_TABLE(of, keembay_emmc_phy_dt_ids);
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static struct platform_driver keembay_emmc_phy_driver = {
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.probe = keembay_emmc_phy_probe,
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.driver = {
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.name = "keembay-emmc-phy",
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.of_match_table = keembay_emmc_phy_dt_ids,
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},
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};
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module_platform_driver(keembay_emmc_phy_driver);
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MODULE_AUTHOR("Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>");
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MODULE_DESCRIPTION("Intel Keem Bay eMMC PHY driver");
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MODULE_LICENSE("GPL v2");
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