m32r: Convert opsput irq chip
Convert the irq chips to the new functions and use proper flow handlers. handle_level_irq is appropriate. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Hirokazu Takata <takata@linux-m32r.org> Cc: Paul Mundt <lethal@linux-sh.org>
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ce1104ce67
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@ -46,39 +46,30 @@ static void enable_opsput_irq(unsigned int irq)
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outl(data, port);
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}
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static void mask_and_ack_opsput(unsigned int irq)
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static void mask_opsput(struct irq_data *data)
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{
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disable_opsput_irq(irq);
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disable_opsput_irq(data->irq);
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}
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static void end_opsput_irq(unsigned int irq)
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static void unmask_opsput(struct irq_data *data)
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{
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enable_opsput_irq(irq);
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enable_opsput_irq(data->irq);
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}
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static unsigned int startup_opsput_irq(unsigned int irq)
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{
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enable_opsput_irq(irq);
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return (0);
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}
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static void shutdown_opsput_irq(unsigned int irq)
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static void shutdown_opsput(struct irq_data *data)
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{
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unsigned long port;
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port = irq2port(irq);
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port = irq2port(data->irq);
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outl(M32R_ICUCR_ILEVEL7, port);
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}
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static struct irq_chip opsput_irq_type =
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{
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.name = "OPSPUT-IRQ",
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.startup = startup_opsput_irq,
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.shutdown = shutdown_opsput_irq,
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.enable = enable_opsput_irq,
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.disable = disable_opsput_irq,
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.ack = mask_and_ack_opsput,
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.end = end_opsput_irq
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.name = "OPSPUT-IRQ",
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.irq_shutdown = shutdown_opsput,
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.irq_mask = mask_opsput,
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.irq_unmask = unmask_opsput,
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};
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/*
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@ -100,7 +91,6 @@ static void disable_opsput_pld_irq(unsigned int irq)
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// disable_opsput_irq(M32R_IRQ_INT1);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
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outw(data, port);
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@ -112,7 +102,6 @@ static void enable_opsput_pld_irq(unsigned int irq)
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unsigned int pldirq;
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pldirq = irq2pldirq(irq);
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// enable_opsput_irq(M32R_IRQ_INT1);
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port = pldirq2port(pldirq);
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data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
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outw(data, port);
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@ -127,7 +116,7 @@ static void mask_and_ack_opsput_pld(unsigned int irq)
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static void end_opsput_pld_irq(unsigned int irq)
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{
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enable_opsput_pld_irq(irq);
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end_opsput_irq(M32R_IRQ_INT1);
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enable_opsput_irq(M32R_IRQ_INT1);
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}
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static unsigned int startup_opsput_pld_irq(unsigned int irq)
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@ -197,7 +186,7 @@ static void mask_and_ack_opsput_lanpld(unsigned int irq)
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static void end_opsput_lanpld_irq(unsigned int irq)
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{
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enable_opsput_lanpld_irq(irq);
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end_opsput_irq(M32R_IRQ_INT0);
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enable_opsput_irq(M32R_IRQ_INT0);
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}
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static unsigned int startup_opsput_lanpld_irq(unsigned int irq)
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@ -266,7 +255,7 @@ static void mask_and_ack_opsput_lcdpld(unsigned int irq)
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static void end_opsput_lcdpld_irq(unsigned int irq)
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{
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enable_opsput_lcdpld_irq(irq);
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end_opsput_irq(M32R_IRQ_INT2);
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enable_opsput_irq(M32R_IRQ_INT2);
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}
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static unsigned int startup_opsput_lcdpld_irq(unsigned int irq)
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@ -306,32 +295,38 @@ void __init init_IRQ(void)
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#endif /* CONFIG_SMC91X */
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/* MFT2 : system timer */
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set_irq_chip(M32R_IRQ_MFT2, &opsput_irq_type);
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set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
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disable_opsput_irq(M32R_IRQ_MFT2);
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/* SIO0 : receive */
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set_irq_chip(M32R_IRQ_SIO0_R, &opsput_irq_type);
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set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO0_R].icucr = 0;
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disable_opsput_irq(M32R_IRQ_SIO0_R);
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/* SIO0 : send */
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set_irq_chip(M32R_IRQ_SIO0_S, &opsput_irq_type);
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set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO0_S].icucr = 0;
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disable_opsput_irq(M32R_IRQ_SIO0_S);
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/* SIO1 : receive */
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set_irq_chip(M32R_IRQ_SIO1_R, &opsput_irq_type);
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set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO1_R].icucr = 0;
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disable_opsput_irq(M32R_IRQ_SIO1_R);
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/* SIO1 : send */
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set_irq_chip(M32R_IRQ_SIO1_S, &opsput_irq_type);
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set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_SIO1_S].icucr = 0;
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disable_opsput_irq(M32R_IRQ_SIO1_S);
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/* DMA1 : */
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set_irq_chip(M32R_IRQ_DMA1, &opsput_irq_type);
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set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_DMA1].icucr = 0;
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disable_opsput_irq(M32R_IRQ_DMA1);
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@ -394,7 +389,8 @@ void __init init_IRQ(void)
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/*
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* INT3# is used for AR
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*/
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set_irq_chip(M32R_IRQ_INT3, &opsput_irq_type);
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set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
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handle_level_irq);
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icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
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disable_opsput_irq(M32R_IRQ_INT3);
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#endif /* CONFIG_VIDEO_M32R_AR */
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