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mvebu dt64 for 5.8 (part 1) 

Armada 3720 based SoC:
 
 + Fix PCIe support allowing to use Compex wifi cards
 
 + Turris MOX board:
   - fix SFP binding
   - forbid SDR104 on SDIO to pass electromagnetic interference certifications
 
 + uDPU board: add i2c recovery support
 
 Armada 8040 based SoC: SolidRun 8040: update phy interface
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Merge tag 'mvebu-dt64-5.8-1' of git://git.infradead.org/linux-mvebu into arm/dt

mvebu dt64 for 5.8 (part 1)

Armada 3720 based SoC:

+ Fix PCIe support allowing to use Compex wifi cards

+ Turris MOX board:
  - fix SFP binding
  - forbid SDR104 on SDIO to pass electromagnetic interference certifications

+ uDPU board: add i2c recovery support

Armada 8040 based SoC: SolidRun 8040: update phy interface

* tag 'mvebu-dt64-5.8-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: armada-3720-turris-mox: fix SFP binding
  arm64: dts: armada-3720-turris-mox: forbid SDR104 on SDIO for FCC purposes
  arm64: dts: add uDPU i2c bus recovery
  arm64: dts: marvell: drop i2c timeout-ms property
  arm64: dts: marvell: armada-37xx: Move PCIe max-link-speed property
  arm64: dts: marvell: armada-37xx: Move PCIe comphy handle property
  arm64: dts: marvell: armada-37xx: Set pcie_reset_pin to gpio function
  arm64: dts: update SolidRun Armada 8040 phy interface types

Link: https://lore.kernel.org/r/878shmeffd.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-05-21 23:10:17 +02:00
parent 65ad1cafe7 c2671acbbb
commit 87b990ab62
9 changed files with 35 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm64/boot/dts/marvell/armada-3720-db.dts
View File

@ -128,6 +128,9 @@
/* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
status = "okay";
};

2
arch/arm64/boot/dts/marvell/armada-3720-espressobin.dtsi
View File

@ -44,9 +44,9 @@
/* J9 */
&pcie0 {
status = "okay";
phys = <&comphy1 0>;
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
};
/* J6 */

10
arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts
View File

@ -95,7 +95,7 @@
};
sfp: sfp {
compatible = "sff,sfp+";
compatible = "sff,sfp";
i2c-bus = <&i2c0>;
los-gpio = <&moxtet_sfp 0 GPIO_ACTIVE_HIGH>;
tx-fault-gpio = <&moxtet_sfp 1 GPIO_ACTIVE_HIGH>;
@ -128,17 +128,11 @@
};
};
&pcie_reset_pins {
function = "gpio";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
status = "okay";
max-link-speed = <2>;
reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
phys = <&comphy1 0>;
/* enabled by U-Boot if PCIe module is present */
status = "disabled";
@ -179,6 +173,8 @@
marvell,pad-type = "sd";
vqmmc-supply = <&vsdio_reg>;
mmc-pwrseq = <&sdhci1_pwrseq>;
/* forbid SDR104 for FCC purposes */
sdhci-caps-mask = <0x2 0x0>;
status = "okay";
};

22
arch/arm64/boot/dts/marvell/armada-3720-uDPU.dts
View File

@ -117,18 +117,36 @@
};
};
&pinctrl_nb {
i2c1_recovery_pins: i2c1-recovery-pins {
groups = "i2c1";
function = "gpio";
};
i2c2_recovery_pins: i2c2-recovery-pins {
groups = "i2c2";
function = "gpio";
};
};
&i2c0 {
status = "okay";
pinctrl-names = "default";
pinctrl-names = "default", "recovery";
pinctrl-0 = <&i2c1_pins>;
pinctrl-1 = <&i2c1_recovery_pins>;
/delete-property/mrvl,i2c-fast-mode;
scl-gpios = <&gpionb 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpionb 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c1 {
status = "okay";
pinctrl-names = "default";
pinctrl-names = "default", "recovery";
pinctrl-0 = <&i2c2_pins>;
pinctrl-1 = <&i2c2_recovery_pins>;
/delete-property/mrvl,i2c-fast-mode;
scl-gpios = <&gpionb 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpionb 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
lm75@48 {
status = "okay";

4
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View File

@ -317,7 +317,7 @@
pcie_reset_pins: pcie-reset-pins {
groups = "pcie1";
function = "pcie";
function = "gpio";
};
pcie_clkreq_pins: pcie-clkreq-pins {
@ -493,6 +493,8 @@
<0 0 0 2 &pcie_intc 1>,
<0 0 0 3 &pcie_intc 2>,
<0 0 0 4 &pcie_intc 3>;
max-link-speed = <2>;
phys = <&comphy1 0>;
pcie_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;

2
arch/arm64/boot/dts/marvell/armada-8040-clearfog-gt-8k.dts
View File

@ -276,7 +276,7 @@
/* SFP */
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phy-mode = "10gbase-r";
managed = "in-band-status";
phys = <&cp0_comphy2 0>;
sfp = <&sfp_cp0_eth0>;

4
arch/arm64/boot/dts/marvell/armada-8040-mcbin-singleshot.dts
View File

@ -16,14 +16,14 @@
&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phy-mode = "10gbase-r";
managed = "in-band-status";
sfp = <&sfp_eth0>;
};
&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
phy-mode = "10gbase-r";
managed = "in-band-status";
sfp = <&sfp_eth1>;
};

4
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
View File

@ -34,12 +34,12 @@
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "10gbase-kr";
phy-mode = "10gbase-r";
};
&cp1_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy8>;
phy-mode = "10gbase-kr";
phy-mode = "10gbase-r";
};

1
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
View File

@ -201,7 +201,6 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
timeout-ms = <1000>;
clocks = <&ap_clk 3>;
status = "disabled";
};