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ARM: dts: rockchip: Add brcm bluetooth for rk3288-veyron 

This enables the Broadcom uart bluetooth driver on uart0 and gives it
ownership of its gpios. In order to use this, you must enable the
following kconfig options:
- CONFIG_BT_HCIUART_BCM
- CONFIG_SERIAL_DEV

This is applicable to rk3288-veyron series boards that use the bcm43540
wifi+bt chips.

As part of this change, also refactor the pinctrl across the various
boards. All the boards using broadcom bluetooth shouldn't touch the
bt_dev_wake pin.

Signed-off-by: Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Link: https://lore.kernel.org/r/20191127223909.253873-2-abhishekpandit@chromium.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Abhishek Pandit-Subedi 2019-11-27 14:39:09 -08:00 committed by Heiko Stuebner
parent e42617b825
commit 8784692d28
11 changed files with 155 additions and 75 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
arch/arm/boot/dts/rk3288-veyron-brain.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Brain";
@ -40,6 +41,14 @@
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
>;
hdmi {
vcc50_hdmi_en: vcc50-hdmi-en {
rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;

22
arch/arm/boot/dts/rk3288-veyron-broadcom-bluetooth.dtsi Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Veyron (and derivatives) fragment for the Broadcom 43450 bluetooth
* chip.
*
* Copyright 2019 Google, Inc
*/
&uart0 {
bluetooth {
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake_l>, <&bt_enable_l>,
<&bt_dev_wake>;
compatible = "brcm,bcm43540-bt";
host-wakeup-gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
shutdown-gpios = <&gpio4 RK_PD5 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
brcm,bt-pcm-int-params = [01 02 00 01 01];
};
};

21
arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi
View File

@ -136,27 +136,6 @@
};
&pinctrl {
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
buttons {
ap_lid_int_l: ap-lid-int-l {
rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;

2
arch/arm/boot/dts/rk3288-veyron-fievel.dts
View File

@ -18,8 +18,6 @@
"google,veyron-fievel-rev0", "google,veyron-fievel",
"google,veyron", "rockchip,rk3288";
/delete-node/ bt-activity;
vccsys: vccsys {
compatible = "regulator-fixed";
regulator-name = "vccsys";

22
arch/arm/boot/dts/rk3288-veyron-jaq.dts
View File

@ -273,6 +273,28 @@
};
&pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;

22
arch/arm/boot/dts/rk3288-veyron-jerry.dts
View File

@ -418,6 +418,28 @@
};
&pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;

9
arch/arm/boot/dts/rk3288-veyron-mickey.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Mickey";
@ -411,6 +412,14 @@
};
&pinctrl {
pinctrl-names = "default";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
>;
hdmi {
power_hdmi_on: power-hdmi-on {
rockchip,pins = <7 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;

21
arch/arm/boot/dts/rk3288-veyron-minnie.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
/ {
model = "Google Minnie";
@ -344,6 +345,26 @@
};
&pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
>;
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;

22
arch/arm/boot/dts/rk3288-veyron-pinky.dts
View File

@ -64,6 +64,28 @@
};
&pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
&bt_dev_wake_sleep
>;
/delete-node/ lcd;
backlight {

21
arch/arm/boot/dts/rk3288-veyron-speedy.dts
View File

@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
#include "rk3288-veyron-broadcom-bluetooth.dtsi"
#include "cros-ec-sbs.dtsi"
/ {
@ -279,6 +280,26 @@
};
&pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&suspend_l_wake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&suspend_l_sleep
>;
buck-5v {
drv_5v: drv-5v {
rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;

59
arch/arm/boot/dts/rk3288-veyron.dtsi
View File

@ -23,30 +23,6 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
bt_activity: bt-activity {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&bt_host_wake>;
/*
* HACK: until we have an LPM driver, we'll use an
* ugly GPIO key to allow Bluetooth to wake from S3.
* This is expected to only be used by BT modules that
* use UART for comms. For BT modules that talk over
* SDIO we should use a wakeup mechanism related to SDIO.
*
* Use KEY_RESERVED here since that will work as a wakeup but
* doesn't get reported to higher levels (so doesn't confuse
* Chrome).
*/
bt-wake {
label = "BT Wakeup";
gpios = <&gpio4 RK_PD7 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_RESERVED>;
wakeup-source;
};
};
power_button: power-button {
compatible = "gpio-keys";
@ -82,22 +58,17 @@
clocks = <&rk808 RK808_CLKOUT1>;
clock-names = "ext_clock";
pinctrl-names = "default";
pinctrl-0 = <&bt_enable_l>, <&wifi_enable_h>;
pinctrl-0 = <&wifi_enable_h>;
/*
* Depending on the actual card populated GPIO4 D4 and D5
* Depending on the actual card populated GPIO4 D4
* correspond to one of these signals on the module:
*
* D4:
* - SDIO_RESET_L_WL_REG_ON
* - PDN (power down when low)
*
* D5:
* - BT_I2S_WS_BT_RFDISABLE_L
* - No connect
*/
reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>,
<&gpio4 RK_PD5 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio4 RK_PD4 GPIO_ACTIVE_LOW>;
};
vcc_5v: vcc-5v {
@ -481,26 +452,6 @@
};
&pinctrl {
pinctrl-names = "default", "sleep";
pinctrl-0 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Wake only */
&bt_dev_wake_awake
>;
pinctrl-1 = <
/* Common for sleep and wake, but no owners */
&ddr0_retention
&ddrio_pwroff
&global_pwroff
/* Sleep only */
&bt_dev_wake_sleep
>;
pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
bias-disable;
drive-strength = <8>;
@ -622,6 +573,10 @@
bt_dev_wake_awake: bt-dev-wake-awake {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;
};
bt_dev_wake: bt-dev-wake {
rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
tpm {