drm/amdgpu: add gc 10.3.6 support
this patch adds gc 10.3.6 support. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yifan Zhang
Alex Deucher
parent
a142606d54
commit
874bfdfa47
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@ -1421,6 +1421,7 @@ static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block);
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@ -1559,6 +1560,7 @@ static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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amdgpu_device_ip_block_add(adev, &mes_v10_1_ip_block);
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break;
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default:
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@ -1765,6 +1767,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 3):
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adev->family = AMDGPU_FAMILY_YC;
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break;
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case IP_VERSION(10, 3, 6):
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adev->family = AMDGPU_FAMILY_GC_10_3_6;
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break;
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case IP_VERSION(10, 3, 7):
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adev->family = AMDGPU_FAMILY_GC_10_3_7;
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break;
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@ -1780,6 +1785,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
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case IP_VERSION(10, 1, 4):
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 7):
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adev->flags |= AMD_IS_APU;
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break;
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@ -106,6 +106,12 @@
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#define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
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#define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
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#define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
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#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
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#define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
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#define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
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#define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
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#define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
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@ -258,6 +264,13 @@ MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
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MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
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MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
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MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
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@ -3415,6 +3428,32 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] =
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
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};
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static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
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{
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
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};
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static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
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SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
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@ -3678,6 +3717,11 @@ static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
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golden_settings_gc_10_0_cyan_skillfish,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
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break;
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case IP_VERSION(10, 3, 6):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3_6,
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(const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
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break;
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case IP_VERSION(10, 3, 7):
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soc15_program_register_sequence(adev,
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golden_settings_gc_10_3_7,
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@ -3871,6 +3915,7 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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adev->gfx.cp_fw_write_wait = true;
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@ -3993,6 +4038,9 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 3):
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chip_name = "yellow_carp";
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break;
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case IP_VERSION(10, 3, 6):
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chip_name = "gc_10_3_6";
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break;
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case IP_VERSION(10, 1, 3):
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case IP_VERSION(10, 1, 4):
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if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2)
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@ -4598,6 +4646,7 @@ static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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adev->gfx.config.max_hw_contexts = 8;
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@ -4736,6 +4785,7 @@ static int gfx_v10_0_sw_init(void *handle)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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adev->gfx.me.num_me = 1;
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@ -4975,7 +5025,8 @@ static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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bitmap = i * adev->gfx.config.max_sh_per_se + j;
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if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
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(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3))) &&
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(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
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(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
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((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
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continue;
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gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
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@ -6249,6 +6300,7 @@ static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
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@ -6387,6 +6439,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
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@ -6402,6 +6455,7 @@ static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
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@ -6501,6 +6555,7 @@ static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
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tmp &= 0xffffff00;
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@ -7231,6 +7286,7 @@ static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
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break;
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 7):
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return true;
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default:
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@ -7266,6 +7322,7 @@ static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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/* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
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@ -7587,6 +7644,7 @@ static int gfx_v10_0_soft_reset(void *handle)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
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grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
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@ -7654,6 +7712,21 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
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preempt_enable();
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clock = clock_lo | (clock_hi << 32ULL);
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break;
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case IP_VERSION(10, 3, 6):
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preempt_disable();
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clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
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clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
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hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
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/* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
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* roughly every 42 seconds.
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*/
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if (hi_check != clock_hi) {
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clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
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clock_hi = hi_check;
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}
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preempt_enable();
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clock = clock_lo | (clock_hi << 32ULL);
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break;
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default:
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preempt_disable();
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clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
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@ -7719,6 +7792,7 @@ static int gfx_v10_0_early_init(void *handle)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
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@ -7781,6 +7855,7 @@ static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
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@ -7817,6 +7892,7 @@ static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
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break;
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@ -8271,6 +8347,7 @@ static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
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switch (adev->ip_versions[GC_HWIP][0]) {
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 6):
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data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
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WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
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break;
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@ -8339,6 +8416,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,
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break;
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 6):
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gfx_v10_cntl_pg(adev, enable);
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amdgpu_gfx_off_ctrl(adev, enable);
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break;
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@ -8365,6 +8443,7 @@ static int gfx_v10_0_set_clockgating_state(void *handle,
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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gfx_v10_0_update_gfx_clock_gating(adev,
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state == AMD_CG_STATE_GATE);
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@ -9478,6 +9557,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
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case IP_VERSION(10, 3, 1):
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case IP_VERSION(10, 3, 4):
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case IP_VERSION(10, 3, 5):
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case IP_VERSION(10, 3, 6):
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case IP_VERSION(10, 3, 3):
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case IP_VERSION(10, 3, 7):
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adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
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@ -9572,8 +9652,9 @@ static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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bitmap = i * adev->gfx.config.max_sh_per_se + j;
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if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
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(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
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(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
|
||||
(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
|
||||
(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
|
||||
(adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
|
||||
((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
|
||||
continue;
|
||||
mask = 1;
|
||||
|
|
|
|||
|
|
@ -1151,6 +1151,7 @@ struct drm_amdgpu_info_video_caps {
|
|||
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
|
||||
#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
|
||||
#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
|
||||
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
|
||||
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
|
|
|
|||
Loading…
Reference in New Issue