mmc: mediatek: tune CMD/DATA together
for MSDC IP which supports both data tune and async fifo, it can tune cmd/data together. which can save the time and make the tune result of CMD more stable as data line are 4bit or 8bit. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -1773,12 +1773,98 @@ skip_fall:
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return final_delay == 0xff ? -EIO : 0;
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}
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/*
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* MSDC IP which supports data tune + async fifo can do CMD/DAT tune
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* together, which can save the tuning time.
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*/
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static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
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{
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struct msdc_host *host = mmc_priv(mmc);
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u32 rise_delay = 0, fall_delay = 0;
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struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
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u8 final_delay, final_maxlen;
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u32 tune_reg = host->dev_comp->pad_tune_reg;
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int i, ret;
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sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
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host->latch_ck);
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_clr_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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for (i = 0 ; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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rise_delay |= (1 << i);
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}
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final_rise_delay = get_best_delay(host, rise_delay);
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/* if rising edge has enough margin, then do not scan falling edge */
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if (final_rise_delay.maxlen >= 12 ||
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(final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
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goto skip_fall;
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_set_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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for (i = 0; i < PAD_DELAY_MAX; i++) {
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_CMDRDLY, i);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, i);
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ret = mmc_send_tuning(mmc, opcode, NULL);
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if (!ret)
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fall_delay |= (1 << i);
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}
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final_fall_delay = get_best_delay(host, fall_delay);
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skip_fall:
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final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
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if (final_maxlen == final_rise_delay.maxlen) {
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sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_clr_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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final_rise_delay.final_phase);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_rise_delay.final_phase);
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final_delay = final_rise_delay.final_phase;
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} else {
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sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
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sdr_set_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
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final_fall_delay.final_phase);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY,
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final_fall_delay.final_phase);
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final_delay = final_fall_delay.final_phase;
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}
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dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
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return final_delay == 0xff ? -EIO : 0;
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}
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static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct msdc_host *host = mmc_priv(mmc);
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int ret;
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u32 tune_reg = host->dev_comp->pad_tune_reg;
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if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
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ret = msdc_tune_together(mmc, opcode);
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if (host->hs400_mode) {
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sdr_clr_bits(host->base + MSDC_IOCON,
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MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
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sdr_set_field(host->base + tune_reg,
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MSDC_PAD_TUNE_DATRRDLY, 0);
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}
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goto tune_done;
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}
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if (host->hs400_mode &&
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host->dev_comp->hs400_tune)
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ret = hs400_tune_response(mmc, opcode);
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@ -1794,6 +1880,7 @@ static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
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dev_err(host->dev, "Tune data fail!\n");
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}
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tune_done:
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host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
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host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
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host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
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