drm: rcar-du: Fix LVDS start sequence on Gen3
According to the latest revision of the datasheet, the LVDS I/O pins must be enabled before starting the PLL. Fix it. Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
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@ -104,7 +104,14 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
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rcar_lvds_write(lvds, LVDPLLCR, pllcr);
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rcar_lvds_write(lvds, LVDPLLCR, pllcr);
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/* Turn the PLL on, set it to LVDS normal mode, wait for the startup
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1,
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LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
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LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
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LVDCR1_CLKSTBY_GEN3);
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/*
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* Turn the PLL on, set it to LVDS normal mode, wait for the startup
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* delay and turn the output on.
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* delay and turn the output on.
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*/
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*/
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lvdcr0 = LVDCR0_PLLON;
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lvdcr0 = LVDCR0_PLLON;
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@ -117,12 +124,6 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds,
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lvdcr0 |= LVDCR0_LVRES;
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lvdcr0 |= LVDCR0_LVRES;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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/* Turn all the channels on. */
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rcar_lvds_write(lvds, LVDCR1,
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LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |
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LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |
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LVDCR1_CLKSTBY_GEN3);
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}
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}
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static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
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