[POWERPC] Cell timebase bug workaround
The Cell CPU timebase has an erratum. When reading the entire 64 bits of the timebase with one mftb instruction, there is a handful of cycles window during which one might read a value with the low order 32 bits already reset to 0x00000000 but the high order bits not yet incremeted by one. This fixes it by reading the timebase again until the low order 32 bits is no longer 0. That might introduce occasional latencies if hitting mftb just at the wrong time, but no more than 70ns on a cell blade, and that was considered acceptable. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Benjamin Herrenschmidt
Paul Mackerras
parent
21c4ff80cb
commit
859deea949
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@ -229,8 +229,10 @@ V_FUNCTION_BEGIN(__do_get_xsec)
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xor r0,r8,r8 /* create dependency */
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add r3,r3,r0
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/* Get TB & offset it */
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mftb r7
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/* Get TB & offset it. We use the MFTB macro which will generate
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* workaround code for Cell.
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*/
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MFTB(r7)
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ld r9,CFG_TB_ORIG_STAMP(r3)
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subf r7,r9,r7
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@ -147,6 +147,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
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#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
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#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
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#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
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#ifndef __ASSEMBLY__
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@ -335,7 +336,7 @@ extern void do_feature_fixups(unsigned long value, void *fixup_start,
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#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
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CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
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#define CPU_FTRS_PA6T (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
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CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
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CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
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@ -30,9 +30,9 @@ BEGIN_FTR_SECTION; \
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mfspr ra,SPRN_PURR; /* get processor util. reg */ \
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END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
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BEGIN_FTR_SECTION; \
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mftb ra; /* or get TB if no PURR */ \
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MFTB(ra); /* or get TB if no PURR */ \
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END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
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ld rb,PACA_STARTPURR(r13); \
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ld rb,PACA_STARTPURR(r13); \
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std ra,PACA_STARTPURR(r13); \
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subf rb,rb,ra; /* subtract start value */ \
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ld ra,PACA_USER_TIME(r13); \
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@ -45,9 +45,9 @@ BEGIN_FTR_SECTION; \
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mfspr ra,SPRN_PURR; /* get processor util. reg */ \
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END_FTR_SECTION_IFSET(CPU_FTR_PURR); \
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BEGIN_FTR_SECTION; \
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mftb ra; /* or get TB if no PURR */ \
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MFTB(ra); /* or get TB if no PURR */ \
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END_FTR_SECTION_IFCLR(CPU_FTR_PURR); \
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ld rb,PACA_STARTPURR(r13); \
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ld rb,PACA_STARTPURR(r13); \
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std ra,PACA_STARTPURR(r13); \
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subf rb,rb,ra; /* subtract start value */ \
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ld ra,PACA_SYSTEM_TIME(r13); \
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@ -274,6 +274,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
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#define ISYNC_601
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#endif
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#ifdef CONFIG_PPC_CELL
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#define MFTB(dest) \
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90: mftb dest; \
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BEGIN_FTR_SECTION_NESTED(96); \
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cmpwi dest,0; \
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beq- 90b; \
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END_FTR_SECTION_NESTED(CPU_FTR_CELL_TB_BUG, CPU_FTR_CELL_TB_BUG, 96)
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#else
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#define MFTB(dest) mftb dest
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#endif
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#ifndef CONFIG_SMP
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#define TLBSYNC
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@ -619,10 +619,35 @@
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: "=r" (rval)); rval;})
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#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
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#ifdef __powerpc64__
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#ifdef CONFIG_PPC_CELL
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#define mftb() ({unsigned long rval; \
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asm volatile( \
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"90: mftb %0;\n" \
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"97: cmpwi %0,0;\n" \
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" beq- 90b;\n" \
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"99:\n" \
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".section __ftr_fixup,\"a\"\n" \
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".align 3\n" \
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"98:\n" \
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" .llong %1\n" \
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" .llong %1\n" \
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" .llong 97b-98b\n" \
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" .llong 99b-98b\n" \
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".previous" \
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: "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
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#else
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#define mftb() ({unsigned long rval; \
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asm volatile("mftb %0" : "=r" (rval)); rval;})
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#endif /* !CONFIG_PPC_CELL */
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#else /* __powerpc64__ */
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#define mftbl() ({unsigned long rval; \
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asm volatile("mftbl %0" : "=r" (rval)); rval;})
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#define mftbu() ({unsigned long rval; \
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asm volatile("mftbu %0" : "=r" (rval)); rval;})
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#endif /* !__powerpc64__ */
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#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
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#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
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@ -82,30 +82,35 @@ struct div_result {
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#define __USE_RTC() 0
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#endif
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/* On ppc64 this gets us the whole timebase; on ppc32 just the lower half */
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#ifdef CONFIG_PPC64
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/* For compatibility, get_tbl() is defined as get_tb() on ppc64 */
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#define get_tbl get_tb
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#else
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static inline unsigned long get_tbl(void)
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{
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unsigned long tbl;
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#if defined(CONFIG_403GCX)
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unsigned long tbl;
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asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
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#else
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asm volatile("mftb %0" : "=r" (tbl));
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#endif
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return tbl;
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#else
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return mftbl();
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#endif
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}
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static inline unsigned int get_tbu(void)
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{
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#ifdef CONFIG_403GCX
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unsigned int tbu;
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#if defined(CONFIG_403GCX)
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asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
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#else
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asm volatile("mftbu %0" : "=r" (tbu));
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#endif
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return tbu;
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#else
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return mftbu();
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#endif
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}
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#endif /* !CONFIG_PPC64 */
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static inline unsigned int get_rtcl(void)
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{
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@ -131,7 +136,7 @@ static inline u64 get_tb(void)
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{
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return mftb();
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}
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#else
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#else /* CONFIG_PPC64 */
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static inline u64 get_tb(void)
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{
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unsigned int tbhi, tblo, tbhi2;
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@ -144,7 +149,7 @@ static inline u64 get_tb(void)
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return ((u64)tbhi << 32) | tblo;
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}
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#endif
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#endif /* !CONFIG_PPC64 */
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static inline void set_tb(unsigned int upper, unsigned int lower)
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{
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@ -8,6 +8,7 @@
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*/
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#include <asm/cputable.h>
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#include <asm/reg.h>
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#define CLOCK_TICK_RATE 1024000 /* Underlying HZ */
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@ -15,13 +16,11 @@ typedef unsigned long cycles_t;
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static inline cycles_t get_cycles(void)
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{
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#ifdef __powerpc64__
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return mftb();
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#else
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cycles_t ret;
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#ifdef __powerpc64__
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__asm__ __volatile__("mftb %0" : "=r" (ret) : );
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#else
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/*
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* For the "cycle" counter we use the timebase lower half.
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* Currently only used on SMP.
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@ -41,9 +40,8 @@ static inline cycles_t get_cycles(void)
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" .long 99b-98b\n"
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".previous"
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: "=r" (ret) : "i" (CPU_FTR_601));
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#endif
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return ret;
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#endif
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}
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#endif /* __KERNEL__ */
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