staging: mt7621-pci: use generic kernel pci subsystem read and write
map_bus callback is called before every .read/.write operation. Implement it and change custom read write operations for the pci subsystem generics. Make the probe function to don't use legacy stuff and request bus resources directly. Get pci register base and ranges from device tree. The driver is not using PCI_LEGACY code anymore and shall use the PCI_DRIVERS_GENERIC option to correct compile it. Add also new Kconfig file for this controller setting there its correct dependencies. Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com> Tested-by: NeilBrown <neil@brown.name> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Sergio Paracuellos
Greg Kroah-Hartman
parent
c5fe50aaa2
commit
8571c62d45
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@ -110,6 +110,8 @@ source "drivers/staging/vboxvideo/Kconfig"
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source "drivers/staging/pi433/Kconfig"
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source "drivers/staging/mt7621-pci/Kconfig"
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source "drivers/staging/mt7621-pinctrl/Kconfig"
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source "drivers/staging/mt7621-spi/Kconfig"
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@ -0,0 +1,7 @@
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config PCI_MT7621
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tristate "MediaTek MT7621 PCI Controller"
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depends on RALINK
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select PCI_DRIVERS_GENERIC
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help
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This selects a driver for the MediaTek MT7621 PCI Controller.
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@ -53,11 +53,16 @@
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <ralink_regs.h>
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#include <mt7621.h>
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#include "../../pci/pci.h"
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/*
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* These functions and structures provide the BIOS scan and mapping of the PCI
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* devices.
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@ -178,6 +183,43 @@ static int pcie_link_status = 0;
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#define PCI_ACCESS_WRITE_2 4
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#define PCI_ACCESS_WRITE_4 5
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/**
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* struct mt7621_pcie_port - PCIe port information
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* @base: IO mapped register base
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* @list: port list
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* @pcie: pointer to PCIe host info
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* @reset: pointer to port reset control
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*/
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struct mt7621_pcie_port {
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void __iomem *base;
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struct list_head list;
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struct mt7621_pcie *pcie;
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struct reset_control *reset;
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};
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/**
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* struct mt7621_pcie - PCIe host information
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* @base: IO Mapped Register Base
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* @io: IO resource
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* @mem: non-prefetchable memory resource
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* @busn: bus range
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* @offset: IO / Memory offset
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* @dev: Pointer to PCIe device
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* @ports: pointer to PCIe port information
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*/
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struct mt7621_pcie {
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void __iomem *base;
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struct device *dev;
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struct resource io;
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struct resource mem;
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struct resource busn;
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struct {
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resource_size_t mem;
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resource_size_t io;
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} offset;
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struct list_head ports;
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};
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static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
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unsigned int func, unsigned int where)
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{
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@ -297,17 +339,22 @@ pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u
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}
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}
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struct pci_ops mt7621_pci_ops = {
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.read = pci_config_read,
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.write = pci_config_write,
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};
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static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct mt7621_pcie *pcie = bus->sysdata;
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u32 address = mt7621_pci_get_cfgaddr(bus->number, PCI_SLOT(devfn),
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PCI_FUNC(devfn), where);
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static struct resource mt7621_res_pci_mem1;
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static struct resource mt7621_res_pci_io1;
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static struct pci_controller mt7621_controller = {
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.pci_ops = &mt7621_pci_ops,
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.mem_resource = &mt7621_res_pci_mem1,
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.io_resource = &mt7621_res_pci_io1,
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writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
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return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
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}
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struct pci_ops mt7621_pci_ops = {
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.map_bus = mt7621_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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static void
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@ -463,9 +510,10 @@ set_phy_for_ssc(void)
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set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
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}
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void setup_cm_memory_region(struct resource *mem_resource)
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static void setup_cm_memory_region(struct resource *mem_resource)
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{
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resource_size_t mask;
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if (mips_cps_numiocu(0)) {
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/* FIXME: hardware doesn't accept mask values with 1s after
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* 0s (e.g. 0xffef), so it would be great to warn if that's
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@ -480,14 +528,142 @@ void setup_cm_memory_region(struct resource *mem_resource)
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}
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}
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static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node;
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struct of_pci_range_parser parser;
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struct of_pci_range range;
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int err;
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if (of_pci_range_parser_init(&parser, node)) {
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dev_err(dev, "missing \"ranges\" property\n");
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return -EINVAL;
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}
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for_each_of_pci_range(&parser, &range) {
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struct resource *res = NULL;
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switch (range.flags & IORESOURCE_TYPE_BITS) {
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case IORESOURCE_IO:
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ioremap(range.cpu_addr, range.size);
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res = &pcie->io;
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pcie->offset.io = 0x00000000UL;
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break;
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case IORESOURCE_MEM:
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res = &pcie->mem;
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pcie->offset.mem = 0x00000000UL;
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break;
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}
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if (res != NULL)
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of_pci_range_to_resource(&range, node, res);
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}
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err = of_pci_parse_bus_range(node, &pcie->busn);
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if (err < 0) {
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dev_err(dev, "failed to parse bus ranges property: %d\n", err);
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pcie->busn.name = node->name;
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pcie->busn.start = 0;
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pcie->busn.end = 0xff;
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pcie->busn.flags = IORESOURCE_BUS;
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}
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return 0;
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}
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static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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struct device_node *node = dev->of_node;
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struct resource regs;
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const char *type;
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int err;
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type = of_get_property(node, "device_type", NULL);
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if (!type || strcmp(type, "pci") != 0) {
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dev_err(dev, "invalid \"device_type\" %s\n", type);
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return -EINVAL;
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}
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err = of_address_to_resource(node, 0, ®s);
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if (err) {
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dev_err(dev, "missing \"reg\" property\n");
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return err;
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}
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pcie->base = devm_ioremap_resource(dev, ®s);
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if (IS_ERR(pcie->base))
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return PTR_ERR(pcie->base);
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return 0;
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}
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static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
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struct list_head *res)
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{
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struct device *dev = pcie->dev;
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int err;
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pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
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pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
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pci_add_resource(res, &pcie->busn);
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err = devm_request_pci_bus_resources(dev, res);
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if (err < 0)
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return err;
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return 0;
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}
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static int mt7621_pcie_register_host(struct pci_host_bridge *host,
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struct list_head *res)
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{
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struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
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list_splice_init(res, &host->windows);
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host->busnr = pcie->busn.start;
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host->dev.parent = pcie->dev;
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host->ops = &mt7621_pci_ops;
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host->map_irq = pcibios_map_irq;
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host->swizzle_irq = pci_common_swizzle;
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host->sysdata = pcie;
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return pci_host_probe(host);
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}
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static int mt7621_pci_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mt7621_pcie *pcie;
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struct pci_host_bridge *bridge;
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int err;
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unsigned long val = 0;
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LIST_HEAD(res);
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if (!dev->of_node)
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return -ENODEV;
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bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
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if (!bridge)
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return -ENODEV;
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pcie = pci_host_bridge_priv(bridge);
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pcie->dev = dev;
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platform_set_drvdata(pdev, pcie);
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INIT_LIST_HEAD(&pcie->ports);
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err = mt7621_pcie_parse_dt(pcie);
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if (err) {
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dev_err(dev, "Parsing DT failed\n");
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return err;
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}
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/* set resources limits */
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iomem_resource.start = 0;
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iomem_resource.end = ~0;
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iomem_resource.end = ~0UL; /* no limit */
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ioport_resource.start = 0;
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ioport_resource.end = ~0;
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ioport_resource.end = ~0UL; /* no limit */
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val = RALINK_PCIE0_RST;
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val |= RALINK_PCIE1_RST;
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@ -665,11 +841,27 @@ pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
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write_config(0, 0, 0, 0x70c, val);
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}
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pci_load_of_ranges(&mt7621_controller, pdev->dev.of_node);
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setup_cm_memory_region(mt7621_controller.mem_resource);
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register_pci_controller(&mt7621_controller);
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return 0;
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err = mt7621_pci_parse_request_of_pci_ranges(pcie);
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if (err) {
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dev_err(dev, "Error requesting pci resources from ranges");
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return err;
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}
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setup_cm_memory_region(&pcie->mem);
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err = mt7621_pcie_request_resources(pcie, &res);
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if (err) {
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dev_err(dev, "Error requesting resources\n");
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return err;
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}
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err = mt7621_pcie_register_host(bridge, &res);
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if (err) {
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dev_err(dev, "Error registering host\n");
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return err;
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}
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return 0;
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}
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int pcibios_plat_dev_init(struct pci_dev *dev)
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