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drm/i915: Don't use link_bw for PLL setup 

Use port_clock instead of link_bw when picking the PLL parameters for
DP. link_bw may be zero with an eDP 1.4 sink that supports
DP_LINK_RATE_SET so we shouldn't use it for anything other than feed it
to the sink appropriately.

v2: Fix typo in commit message (Sivakumar)

Reviewed-by: Sivakumar Thulasimani <sivakumar.thulasimani@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä 2015-08-11 20:21:46 +03:00 committed by Daniel Vetter
parent 0f2a2a756e
commit 840b32b7ed
2 changed files with 26 additions and 29 deletions
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11
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -1579,17 +1579,14 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
wrpll_params.central_freq; wrpll_params.central_freq;
} else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
struct drm_encoder *encoder = &intel_encoder->base; switch (crtc_state->port_clock / 2) {
struct intel_dp *intel_dp = enc_to_intel_dp(encoder); case 81000:
switch (intel_dp->link_bw) {
case DP_LINK_BW_1_62:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
break; break;
case DP_LINK_BW_2_7: case 135000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
break; break;
case DP_LINK_BW_5_4: case 270000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
break; break;
} }

44
drivers/gpu/drm/i915/intel_dp.c
View File

@ -48,28 +48,28 @@
#define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
struct dp_link_dpll { struct dp_link_dpll {
int link_bw; int clock;
struct dpll dpll; struct dpll dpll;
}; };
static const struct dp_link_dpll gen4_dpll[] = { static const struct dp_link_dpll gen4_dpll[] = {
{ DP_LINK_BW_1_62, { 162000,
{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
{ DP_LINK_BW_2_7, { 270000,
{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
}; };
static const struct dp_link_dpll pch_dpll[] = { static const struct dp_link_dpll pch_dpll[] = {
{ DP_LINK_BW_1_62, { 162000,
{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
{ DP_LINK_BW_2_7, { 270000,
{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
}; };
static const struct dp_link_dpll vlv_dpll[] = { static const struct dp_link_dpll vlv_dpll[] = {
{ DP_LINK_BW_1_62, { 162000,
{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
{ DP_LINK_BW_2_7, { 270000,
{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
}; };
@ -83,11 +83,11 @@ static const struct dp_link_dpll chv_dpll[] = {
* m2 is stored in fixed point format using formula below * m2 is stored in fixed point format using formula below
* (m2_int << 22) | m2_fraction * (m2_int << 22) | m2_fraction
*/ */
{ DP_LINK_BW_1_62, /* m2_int = 32, m2_fraction = 1677722 */ { 162000, /* m2_int = 32, m2_fraction = 1677722 */
{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
{ DP_LINK_BW_2_7, /* m2_int = 27, m2_fraction = 0 */ { 270000, /* m2_int = 27, m2_fraction = 0 */
{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
{ DP_LINK_BW_5_4, /* m2_int = 27, m2_fraction = 0 */ { 540000, /* m2_int = 27, m2_fraction = 0 */
{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } } { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
}; };
@ -1133,7 +1133,7 @@ intel_dp_connector_unregister(struct intel_connector *intel_connector)
} }
static void static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock) skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{ {
u32 ctrl1; u32 ctrl1;
@ -1145,7 +1145,7 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
pipe_config->dpll_hw_state.cfgcr2 = 0; pipe_config->dpll_hw_state.cfgcr2 = 0;
ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0); ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
switch (link_clock / 2) { switch (pipe_config->port_clock / 2) {
case 81000: case 81000:
ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
SKL_DPLL0); SKL_DPLL0);
@ -1179,19 +1179,19 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
} }
static void static void
hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
{ {
memset(&pipe_config->dpll_hw_state, 0, memset(&pipe_config->dpll_hw_state, 0,
sizeof(pipe_config->dpll_hw_state)); sizeof(pipe_config->dpll_hw_state));
switch (link_bw) { switch (pipe_config->port_clock / 2) {
case DP_LINK_BW_1_62: case 81000:
pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810; pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
break; break;
case DP_LINK_BW_2_7: case 135000:
pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350; pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
break; break;
case DP_LINK_BW_5_4: case 270000:
pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700; pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
break; break;
} }
@ -1238,7 +1238,7 @@ intel_dp_source_rates(struct drm_device *dev, const int **source_rates)
static void static void
intel_dp_set_clock(struct intel_encoder *encoder, intel_dp_set_clock(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config, int link_bw) struct intel_crtc_state *pipe_config)
{ {
struct drm_device *dev = encoder->base.dev; struct drm_device *dev = encoder->base.dev;
const struct dp_link_dpll *divisor = NULL; const struct dp_link_dpll *divisor = NULL;
@ -1260,7 +1260,7 @@ intel_dp_set_clock(struct intel_encoder *encoder,
if (divisor && count) { if (divisor && count) {
for (i = 0; i < count; i++) { for (i = 0; i < count; i++) {
if (link_bw == divisor[i].link_bw) { if (pipe_config->port_clock == divisor[i].clock) {
pipe_config->dpll = divisor[i].dpll; pipe_config->dpll = divisor[i].dpll;
pipe_config->clock_set = true; pipe_config->clock_set = true;
break; break;
@ -1535,13 +1535,13 @@ found:
} }
if (IS_SKYLAKE(dev) && is_edp(intel_dp)) if (IS_SKYLAKE(dev) && is_edp(intel_dp))
skl_edp_set_pll_config(pipe_config, common_rates[clock]); skl_edp_set_pll_config(pipe_config);
else if (IS_BROXTON(dev)) else if (IS_BROXTON(dev))
/* handled in ddi */; /* handled in ddi */;
else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw); hsw_dp_set_ddi_pll_sel(pipe_config);
else else
intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw); intel_dp_set_clock(encoder, pipe_config);
return true; return true;
} }