ASoC: rsnd: add rsnd_ssi_config_init()
In order to enhance code readability, this patch adds rsnd_ssi_config_init() and moves SSICR register settings to it. This is prepare patch for TDM support Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -253,6 +253,55 @@ static void rsnd_ssi_master_clk_stop(struct rsnd_ssi *ssi,
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rsnd_adg_ssi_clk_stop(mod);
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rsnd_adg_ssi_clk_stop(mod);
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}
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}
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static int rsnd_ssi_config_init(struct rsnd_ssi *ssi,
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struct rsnd_dai_stream *io)
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{
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struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
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struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
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u32 cr_own;
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u32 cr_mode;
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/*
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* always use 32bit system word.
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* see also rsnd_ssi_master_clk_enable()
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*/
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cr_own = FORCE | SWL_32 | PDTA;
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if (rdai->bit_clk_inv)
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cr_own |= SCKP;
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if (rdai->frm_clk_inv)
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cr_own |= SWSP;
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if (rdai->data_alignment)
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cr_own |= SDTA;
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if (rdai->sys_delay)
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cr_own |= DEL;
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if (rsnd_io_is_play(io))
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cr_own |= TRMD;
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switch (runtime->sample_bits) {
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case 16:
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cr_own |= DWL_16;
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break;
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case 32:
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cr_own |= DWL_24;
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break;
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default:
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return -EINVAL;
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}
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if (rsnd_ssi_is_dma_mode(rsnd_mod_get(ssi))) {
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cr_mode = UIEN | OIEN | /* over/under run */
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DMEN; /* DMA : enable DMA */
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} else {
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cr_mode = DIEN; /* PIO : enable Data interrupt */
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}
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ssi->cr_own = cr_own;
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ssi->cr_mode = cr_mode;
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return 0;
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}
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/*
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/*
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* SSI mod common functions
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* SSI mod common functions
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*/
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*/
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@ -261,9 +310,6 @@ static int rsnd_ssi_init(struct rsnd_mod *mod,
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struct rsnd_priv *priv)
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struct rsnd_priv *priv)
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{
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{
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struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
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struct rsnd_ssi *ssi = rsnd_mod_to_ssi(mod);
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struct rsnd_dai *rdai = rsnd_io_to_rdai(io);
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struct snd_pcm_runtime *runtime = rsnd_io_to_runtime(io);
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u32 cr;
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int ret;
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int ret;
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ssi->usrcnt++;
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ssi->usrcnt++;
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@ -277,49 +323,9 @@ static int rsnd_ssi_init(struct rsnd_mod *mod,
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if (rsnd_ssi_is_parent(mod, io))
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if (rsnd_ssi_is_parent(mod, io))
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return 0;
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return 0;
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cr = FORCE | PDTA;
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ret = rsnd_ssi_config_init(ssi, io);
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if (ret < 0)
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/*
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return ret;
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* always use 32bit system word for easy clock calculation.
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* see also rsnd_ssi_master_clk_enable()
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*/
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cr |= SWL_32;
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/*
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* init clock settings for SSICR
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*/
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switch (runtime->sample_bits) {
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case 16:
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cr |= DWL_16;
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break;
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case 32:
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cr |= DWL_24;
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break;
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default:
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return -EIO;
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}
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if (rdai->bit_clk_inv)
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cr |= SCKP;
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if (rdai->frm_clk_inv)
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cr |= SWSP;
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if (rdai->data_alignment)
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cr |= SDTA;
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if (rdai->sys_delay)
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cr |= DEL;
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if (rsnd_io_is_play(io))
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cr |= TRMD;
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ssi->cr_own = cr;
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if (rsnd_ssi_is_dma_mode(mod)) {
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cr = UIEN | OIEN | /* over/under run */
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DMEN; /* DMA : enable DMA */
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} else {
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cr = DIEN; /* PIO : enable Data interrupt */
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}
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ssi->cr_mode = cr;
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ssi->err = -1; /* ignore 1st error */
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ssi->err = -1; /* ignore 1st error */
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