MIPS: Alchemy: prom_putchar is board dependent
This patch replaces the general alchemy prom_putchar() implementation in favor of board-specific versions: The UART where the output of prom_putchar is directed to really depends on the board, the current implementation hardcodes this on a per-SoC basis which is just wrong. So a generic uart tx function is provided in the alchemy headers, and the boards can provide their own prom_putchar with custom destination uart, and all in-kernel alchemy boards support early printk. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
963accbc82
commit
8402a1588a
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@ -20,12 +20,14 @@ config MIPS_MTX1
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select HW_HAS_PCI
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select SOC_AU1500
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_BOSPORUS
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bool "Alchemy Bosporus board"
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select SOC_AU1500
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select DMA_NONCOHERENT
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_DB1000
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bool "Alchemy DB1000 board"
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@ -33,12 +35,14 @@ config MIPS_DB1000
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_DB1100
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bool "Alchemy DB1100 board"
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select SOC_AU1100
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select DMA_NONCOHERENT
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_DB1200
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bool "Alchemy DB1200 board"
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@ -46,6 +50,7 @@ config MIPS_DB1200
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select DMA_COHERENT
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select MIPS_DISABLE_OBSOLETE_IDE
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_DB1500
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bool "Alchemy DB1500 board"
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@ -55,6 +60,7 @@ config MIPS_DB1500
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select MIPS_DISABLE_OBSOLETE_IDE
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select SYS_SUPPORTS_BIG_ENDIAN
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_DB1550
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bool "Alchemy DB1550 board"
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@ -63,12 +69,14 @@ config MIPS_DB1550
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select DMA_NONCOHERENT
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select MIPS_DISABLE_OBSOLETE_IDE
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_MIRAGE
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bool "Alchemy Mirage board"
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select DMA_NONCOHERENT
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select SOC_AU1500
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_PB1000
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bool "Alchemy PB1000 board"
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@ -77,6 +85,7 @@ config MIPS_PB1000
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select HW_HAS_PCI
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select SWAP_IO_SPACE
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_PB1100
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bool "Alchemy PB1100 board"
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@ -85,6 +94,7 @@ config MIPS_PB1100
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select HW_HAS_PCI
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select SWAP_IO_SPACE
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_PB1200
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bool "Alchemy PB1200 board"
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@ -92,6 +102,7 @@ config MIPS_PB1200
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select DMA_NONCOHERENT
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select MIPS_DISABLE_OBSOLETE_IDE
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_PB1500
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bool "Alchemy PB1500 board"
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@ -99,6 +110,7 @@ config MIPS_PB1500
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select DMA_NONCOHERENT
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select HW_HAS_PCI
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_PB1550
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bool "Alchemy PB1550 board"
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@ -107,12 +119,14 @@ config MIPS_PB1550
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select HW_HAS_PCI
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select MIPS_DISABLE_OBSOLETE_IDE
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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config MIPS_XXS1500
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bool "MyCable XXS1500 board"
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select DMA_NONCOHERENT
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select SOC_AU1500
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select SYS_SUPPORTS_LITTLE_ENDIAN
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select SYS_HAS_EARLY_PRINTK
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endchoice
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@ -5,7 +5,7 @@
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# Makefile for the Alchemy Au1xx0 CPUs, generic files.
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#
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obj-y += prom.o irq.o puts.o time.o reset.o \
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obj-y += prom.o irq.o time.o reset.o \
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clocks.o platform.o power.o setup.o \
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sleeper.o dma.o dbdma.o
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@ -1,68 +0,0 @@
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/*
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*
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* BRIEF MODULE DESCRIPTION
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* Low level UART routines to directly access Alchemy UART.
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*
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* Copyright 2001, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <asm/mach-au1x00/au1000.h>
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#define SERIAL_BASE UART_BASE
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#define SER_CMD 0x7
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#define SER_DATA 0x1
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#define TX_BUSY 0x20
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#define TIMEOUT 0xffffff
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#define SLOW_DOWN
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static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
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#ifdef SLOW_DOWN
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static inline void slow_down(void)
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{
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int k;
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for (k = 0; k < 10000; k++);
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}
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#else
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#define slow_down()
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#endif
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void
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prom_putchar(const unsigned char c)
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{
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unsigned char ch;
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int i = 0;
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do {
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ch = com1[SER_CMD];
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slow_down();
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i++;
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if (i > TIMEOUT)
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break;
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} while (0 == (ch & TX_BUSY));
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com1[SER_DATA] = c;
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}
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@ -60,3 +60,8 @@ void __init prom_init(void)
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strict_strtoul(memsize_str, 0, &memsize);
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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}
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void prom_putchar(unsigned char c)
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{
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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}
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@ -32,6 +32,7 @@
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#include <linux/init.h>
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#include <asm/bootinfo.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <prom.h>
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@ -58,3 +59,8 @@ void __init prom_init(void)
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strict_strtoul(memsize_str, 0, &memsize);
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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}
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void prom_putchar(unsigned char c)
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{
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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}
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@ -30,6 +30,7 @@
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#include <linux/kernel.h>
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#include <asm/bootinfo.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <prom.h>
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@ -56,3 +57,8 @@ void __init prom_init(void)
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strict_strtoul(memsize_str, 0, &memsize);
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add_memory_region(0, memsize, BOOT_MEM_RAM);
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}
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void prom_putchar(unsigned char c)
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{
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alchemy_uart_putchar(UART0_PHYS_ADDR, c);
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}
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@ -161,6 +161,25 @@ static inline int alchemy_get_cputype(void)
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return ALCHEMY_CPU_UNKNOWN;
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}
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static inline void alchemy_uart_putchar(u32 uart_phys, u8 c)
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{
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void __iomem *base = (void __iomem *)KSEG1ADDR(uart_phys);
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int timeout, i;
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/* check LSR TX_EMPTY bit */
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timeout = 0xffffff;
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do {
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if (__raw_readl(base + 0x1c) & 0x20)
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break;
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/* slow down */
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for (i = 10000; i; i--)
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asm volatile ("nop");
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} while (--timeout);
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__raw_writel(c, base + 0x04); /* tx */
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wmb();
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}
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/* arch/mips/au1000/common/clocks.c */
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extern void set_au1x00_speed(unsigned int new_freq);
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extern unsigned int get_au1x00_speed(void);
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