drivers:pci: pcie RC driver support NV gt710
drivers:pci: pcie RC driver suppoer NV gt710 Signed-off-by: fengchun.li <fengchun.li@sophgo.com>
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9f60e3de64
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836460bf75
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@ -31,6 +31,10 @@
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<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
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<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
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dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
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//INTA
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 64 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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@ -60,6 +64,10 @@
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<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
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<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
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dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
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//INTA
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 65 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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@ -89,6 +97,10 @@
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<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
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<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
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dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
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//INTA
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 73 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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@ -118,6 +130,10 @@
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<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
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<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
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dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
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//INTA
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 74 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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@ -147,6 +163,10 @@
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<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
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<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
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dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
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//INTA
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0x7>;
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interrupt-map = <0 0 0 1 &intc 125 IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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@ -263,7 +263,11 @@
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<848 IRQ_TYPE_LEVEL_HIGH>, <849 IRQ_TYPE_LEVEL_HIGH>,
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<850 IRQ_TYPE_LEVEL_HIGH>, <851 IRQ_TYPE_LEVEL_HIGH>,
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<852 IRQ_TYPE_LEVEL_HIGH>, <853 IRQ_TYPE_LEVEL_HIGH>,
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<854 IRQ_TYPE_LEVEL_HIGH>, <855 IRQ_TYPE_LEVEL_HIGH>;
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<854 IRQ_TYPE_LEVEL_HIGH>, <855 IRQ_TYPE_LEVEL_HIGH>,
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<856 IRQ_TYPE_LEVEL_HIGH>, <857 IRQ_TYPE_LEVEL_HIGH>,
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<858 IRQ_TYPE_LEVEL_HIGH>, <859 IRQ_TYPE_LEVEL_HIGH>,
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<860 IRQ_TYPE_LEVEL_HIGH>, <861 IRQ_TYPE_LEVEL_HIGH>,
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<862 IRQ_TYPE_LEVEL_HIGH>, <863 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7",
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"msi8", "msi9", "msi10", "msi11",
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@ -389,7 +393,8 @@
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"msi488", "msi489", "msi490", "msi491",
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"msi492", "msi493", "msi494", "msi495",
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"msi496", "msi497", "msi498", "msi499",
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"msi500", "msi501", "msi502", "msi503";
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"msi500", "msi501", "msi502", "msi503",
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"msi504", "msi505", "msi506", "msi507",
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"msi508", "msi509", "msi510", "msi511";
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};
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};
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@ -756,13 +756,6 @@ static void sophgo_dw_pcie_iatu_detect(struct sophgo_dw_pcie *pcie)
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pcie->region_align / SZ_1K, (pcie->region_limit + 1) / SZ_1G);
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}
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int sophgo_dw_pcie_parse_irq_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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return 0; /* Proper return code 0 == NO_IRQ */
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}
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static int pcie_config_eq(struct sophgo_dw_pcie *pcie)
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{
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uint32_t val = 0;
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@ -1291,7 +1284,7 @@ int sophgo_dw_pcie_probe(struct platform_device *pdev)
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bridge->sysdata = pp;
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bridge->dev.parent = dev;
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bridge->ops = &sophgo_dw_pcie_ops;
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bridge->map_irq = sophgo_dw_pcie_parse_irq_and_map_pci;
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bridge->map_irq = of_irq_parse_and_map_pci;
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bridge->swizzle_irq = pci_common_swizzle;
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ret = pci_host_probe(bridge);
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@ -125,21 +125,21 @@ struct sophgo_dw_pcie {
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uint64_t cdma_pa_start;
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uint64_t cdma_size;
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uint32_t c2c_pcie_rc;
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size_t atu_size;
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uint32_t pcie_card;
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uint32_t pcie_route_config;
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u32 num_ib_windows;
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u32 num_ob_windows;
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u32 region_align;
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u64 region_limit;
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size_t atu_size;
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uint32_t pcie_card;
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uint32_t pcie_route_config;
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u32 num_ib_windows;
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u32 num_ob_windows;
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u32 region_align;
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u64 region_limit;
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struct dw_pcie_rp pp;
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const struct dw_pcie_ops *ops;
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u32 version;
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u32 type;
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u32 version;
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u32 type;
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unsigned long caps;
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int num_lanes;
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int link_gen;
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u8 n_fts[2];
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int num_lanes;
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int link_gen;
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u8 n_fts[2];
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struct dw_edma_chip edma;
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struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
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struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS];
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@ -257,4 +257,4 @@ struct sophgo_dw_pcie {
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};
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#endif
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#endif
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#endif
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