drivers:pci: pcie RC driver support NV gt710

drivers:pci: pcie RC driver suppoer NV gt710

Signed-off-by: fengchun.li <fengchun.li@sophgo.com>
This commit is contained in:
fengchun.li 2024-10-28 21:18:35 +08:00 committed by xingxg2022
parent 9f60e3de64
commit 836460bf75
4 changed files with 42 additions and 24 deletions

View File

@ -31,6 +31,10 @@
<0x43000000 0x42 0x00000000 0x42 0x00000000 0x2 0x00000000>,
<0x03000000 0x41 0x00000000 0x41 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
//INTA
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 64 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
@ -60,6 +64,10 @@
<0x43000000 0x4a 0x00000000 0x4a 0x00000000 0x2 0x00000000>,
<0x03000000 0x49 0x00000000 0x49 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
//INTA
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 65 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
@ -89,6 +97,10 @@
<0x43000000 0x52 0x00000000 0x52 0x00000000 0x2 0x00000000>,
<0x03000000 0x51 0x00000000 0x51 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
//INTA
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 73 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
@ -118,6 +130,10 @@
<0x43000000 0x5a 0x00000000 0x5a 0x00000000 0x2 0x00000000>,
<0x03000000 0x59 0x00000000 0x59 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
//INTA
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 74 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
@ -147,6 +163,10 @@
<0x43000000 0x62 0x00000000 0x62 0x00000000 0x2 0x00000000>,
<0x03000000 0x61 0x00000000 0x61 0x00000000 0x1 0x00000000>;
dma-ranges = <0x03000000 0x0 0x0 0x0 0x0 0x40 0x0>;
//INTA
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 125 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};

View File

@ -263,7 +263,11 @@
<848 IRQ_TYPE_LEVEL_HIGH>, <849 IRQ_TYPE_LEVEL_HIGH>,
<850 IRQ_TYPE_LEVEL_HIGH>, <851 IRQ_TYPE_LEVEL_HIGH>,
<852 IRQ_TYPE_LEVEL_HIGH>, <853 IRQ_TYPE_LEVEL_HIGH>,
<854 IRQ_TYPE_LEVEL_HIGH>, <855 IRQ_TYPE_LEVEL_HIGH>;
<854 IRQ_TYPE_LEVEL_HIGH>, <855 IRQ_TYPE_LEVEL_HIGH>,
<856 IRQ_TYPE_LEVEL_HIGH>, <857 IRQ_TYPE_LEVEL_HIGH>,
<858 IRQ_TYPE_LEVEL_HIGH>, <859 IRQ_TYPE_LEVEL_HIGH>,
<860 IRQ_TYPE_LEVEL_HIGH>, <861 IRQ_TYPE_LEVEL_HIGH>,
<862 IRQ_TYPE_LEVEL_HIGH>, <863 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
@ -389,7 +393,8 @@
"msi488", "msi489", "msi490", "msi491",
"msi492", "msi493", "msi494", "msi495",
"msi496", "msi497", "msi498", "msi499",
"msi500", "msi501", "msi502", "msi503";
"msi500", "msi501", "msi502", "msi503",
"msi504", "msi505", "msi506", "msi507",
"msi508", "msi509", "msi510", "msi511";
};
};

View File

@ -756,13 +756,6 @@ static void sophgo_dw_pcie_iatu_detect(struct sophgo_dw_pcie *pcie)
pcie->region_align / SZ_1K, (pcie->region_limit + 1) / SZ_1G);
}
int sophgo_dw_pcie_parse_irq_and_map_pci(const struct pci_dev *dev, u8 slot, u8 pin)
{
return 0; /* Proper return code 0 == NO_IRQ */
}
static int pcie_config_eq(struct sophgo_dw_pcie *pcie)
{
uint32_t val = 0;
@ -1291,7 +1284,7 @@ int sophgo_dw_pcie_probe(struct platform_device *pdev)
bridge->sysdata = pp;
bridge->dev.parent = dev;
bridge->ops = &sophgo_dw_pcie_ops;
bridge->map_irq = sophgo_dw_pcie_parse_irq_and_map_pci;
bridge->map_irq = of_irq_parse_and_map_pci;
bridge->swizzle_irq = pci_common_swizzle;
ret = pci_host_probe(bridge);

View File

@ -125,21 +125,21 @@ struct sophgo_dw_pcie {
uint64_t cdma_pa_start;
uint64_t cdma_size;
uint32_t c2c_pcie_rc;
size_t atu_size;
uint32_t pcie_card;
uint32_t pcie_route_config;
u32 num_ib_windows;
u32 num_ob_windows;
u32 region_align;
u64 region_limit;
size_t atu_size;
uint32_t pcie_card;
uint32_t pcie_route_config;
u32 num_ib_windows;
u32 num_ob_windows;
u32 region_align;
u64 region_limit;
struct dw_pcie_rp pp;
const struct dw_pcie_ops *ops;
u32 version;
u32 type;
u32 version;
u32 type;
unsigned long caps;
int num_lanes;
int link_gen;
u8 n_fts[2];
int num_lanes;
int link_gen;
u8 n_fts[2];
struct dw_edma_chip edma;
struct clk_bulk_data app_clks[DW_PCIE_NUM_APP_CLKS];
struct clk_bulk_data core_clks[DW_PCIE_NUM_CORE_CLKS];
@ -257,4 +257,4 @@ struct sophgo_dw_pcie {
};
#endif
#endif
#endif