pinctrl: armada-37xx: Correct mpp definitions
This is a cleanup and fix of the patch by Ken Ma <make@marvell.com>. Fix the mpp definitions according to newest revision of the specification: - northbridge: fix pmic1 gpio number to 7 fix pmic0 gpio number to 6 - southbridge split pcie1 group bit mask to BIT(5) and BIT(9) fix ptp group bit mask to BIT(11) | BIT(12) | BIT(13) add smi group with bit mask BIT(4) [gregory: split the pcie group in 2, as at hardware level they can be configured separately] Signed-off-by: Marek Behún <marek.behun@nic.cz> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -58,11 +58,11 @@ group pwm3
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- functions pwm, gpio
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group pmic1
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- pin 17
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- pin 7
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- functions pmic, gpio
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group pmic0
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- pin 16
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- pin 6
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- functions pmic, gpio
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group i2c2
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@ -112,17 +112,25 @@ group usb2_drvvbus1
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- functions drvbus, gpio
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group sdio_sb
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- pins 60-64
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- pins 60-65
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- functions sdio, gpio
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group rgmii
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- pins 42-55
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- pins 42-53
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- functions mii, gpio
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group pcie1
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- pins 39-40
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- pins 39
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- functions pcie, gpio
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group pcie1_clkreq
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- pins 40
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- functions pcie, gpio
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group smi
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- pins 54-55
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- functions smi, gpio
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group ptp
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- pins 56-58
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- functions ptp, gpio
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@ -170,8 +170,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
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PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
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PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
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PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
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PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
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PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
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PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
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PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
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PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
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PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
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PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
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@ -195,8 +195,10 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
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PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
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PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
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PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
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PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
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PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
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PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
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PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
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PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
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PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
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PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
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PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
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PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
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