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PCI: Wait up to 60 seconds for device to become ready after FLR 

Sporadic reset issues have been observed with an Intel 750 NVMe drive while
assigning the physical function to the guest machine.  The sequence of
events observed is as follows:

  - perform a Function Level Reset (FLR)
  - sleep up to 1000ms total
  - read ~0 from PCI_COMMAND (CRS completion for config read)
  - warn that the device didn't return from FLR
  - touch the device before it's ready
  - device drops config writes when we restore register settings (there's
    no mechanism for software to learn about CRS completions for writes)
  - incomplete register restore leaves device in inconsistent state
  - device probe fails because device is in inconsistent state

After reset, an endpoint may respond to config requests with Configuration
Request Retry Status (CRS) to indicate that it is not ready to accept new
requests. See PCIe r3.1, sec 2.3.1 and 6.6.2.

Increase the timeout value from 1 second to 60 seconds to cover the period
where device responds with CRS and also report polling progress.

Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
[bhelgaas: include the mandatory 100ms in the delays we print]
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This commit is contained in:
Sinan Kaya 2017-08-29 14:45:45 -05:00 committed by Bjorn Helgaas
parent 6a802ef0af
commit 821cdad5c4
1 changed files with 38 additions and 16 deletions
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54
drivers/pci/pci.c
View File

@ -3820,27 +3820,49 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)
} }
EXPORT_SYMBOL(pci_wait_for_pending_transaction); EXPORT_SYMBOL(pci_wait_for_pending_transaction);
/*
* We should only need to wait 100ms after FLR, but some devices take longer.
* Wait for up to 1000ms for config space to return something other than -1.
* Intel IGD requires this when an LCD panel is attached. We read the 2nd
* dword because VFs don't implement the 1st dword.
*/
static void pci_flr_wait(struct pci_dev *dev) static void pci_flr_wait(struct pci_dev *dev)
{ {
int i = 0; int delay = 1, timeout = 60000;
u32 id; u32 id;
do { /*
msleep(100); * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
pci_read_config_dword(dev, PCI_COMMAND, &id); * 100ms, but may silently discard requests while the FLR is in
} while (i++ < 10 && id == ~0); * progress. Wait 100ms before trying to access the device.
*/
msleep(100);
if (id == ~0) /*
dev_warn(&dev->dev, "Failed to return from FLR\n"); * After 100ms, the device should not silently discard config
else if (i > 1) * requests, but it may still indicate that it needs more time by
dev_info(&dev->dev, "Required additional %dms to return from FLR\n", * responding to them with CRS completions. The Root Port will
(i - 1) * 100); * generally synthesize ~0 data to complete the read (except when
* CRS SV is enabled and the read was for the Vendor ID; in that
* case it synthesizes 0x0001 data).
*
* Wait for the device to return a non-CRS completion. Read the
* Command register instead of Vendor ID so we don't have to
* contend with the CRS SV value.
*/
pci_read_config_dword(dev, PCI_COMMAND, &id);
while (id == ~0) {
if (delay > timeout) {
dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
100 + delay - 1);
return;
}
if (delay > 1000)
dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
100 + delay - 1);
msleep(delay);
delay *= 2;
pci_read_config_dword(dev, PCI_COMMAND, &id);
}
if (delay > 1000)
dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
} }
/** /**