Reset controller changes for v4.15
- add ARC AX10x support, merged from a separate branch that is also included in the ARC tree - add Stratix10 support via socfpga - unify socfpga, stm32, sunxi, and zx2967 into simple-reset driver - add Meson GX reset level control and remove an unneeded check - add Uniphier PXs3 and ethernet reset controls - add MT7622 reset control dt-bindings header -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEBsBxhV1FaKwXuCOBUMKIHHCeYOsFAlnoTaAXHHAuemFiZWxA cGVuZ3V0cm9uaXguZGUACgkQUMKIHHCeYOvJsxAA6HRkj+khhPeIlIzI2eB35Ak5 VsoGXEp6epQTqtdlN9UFQ4sVXsZAtbTZ38uNbK+ShvM84ArWvHNf7wnk/dA6eZqP U2TfxoXPjj7LVOBb4H/aYJXuuJgoYvvD0iKBfMXe563Xp8CIHUc/aDJ89QWMjDB+ m3LT4oVX+OQ9Xmc5KAfkCfJdklVGwas9ecaMNJHV6hj0x+ZsEu+E6iwA1lSHcjKJ x2rCXb4YDA6XSqB7UBgtZQ4BEE1HzRqAnsJDY6PyWav7EvZ8fA/8Igt2KTAseEhA jVVQyuxcPhFXAX36O9S5QrBkDEYdgzNO0H2VvAToPTffrIReffFAzAdg0og/ODje aIghP3iI/2MeYN3H1V8ujWdZNpiKJEj1kdAJjZW7+Oe9V8IZF6lsBdtLbUpOlrwQ AUY5kURaQhz5Mf9l0Q+wGOXMNojfR93XSQt+vqzxXnvhuJgWgcOL0WvaXF8lP3fp z1Z+E3O/VuPoJh7/hwxX8TG287II5k0k5KrS2FUlm+6McNRQIt+mOZ4XaX/XqZTx V1hEELu9yPoiSpUxGomblv+eh8bFYgAHuukIWx2ZbZwKwDrrQmz77YH6RmwzjZMN rOIqgQRUkRDUaIl1C8qK/aNo36lDbGAYthVtrKMuYkcOzJRZImr+z7sJtOJIpQA0 7SS+55nh+ja69nrpYYU= =yCoy -----END PGP SIGNATURE----- Merge tag 'reset-for-4.15' of git://git.pengutronix.de/git/pza/linux into next/drivers Pull "Reset controller changes for v4.15" from Philipp Zabel: - add ARC AX10x support, merged from a separate branch that is also included in the ARC tree - add Stratix10 support via socfpga - unify socfpga, stm32, sunxi, and zx2967 into simple-reset driver - add Meson GX reset level control and remove an unneeded check - add Uniphier PXs3 and ethernet reset controls - add MT7622 reset control dt-bindings header * tag 'reset-for-4.15' of git://git.pengutronix.de/git/pza/linux: reset: zx2967: use the reset-simple driver reset: stm32: use the reset-simple driver reset: socfpga: use the reset-simple driver reset: sunxi: use reset-simple driver reset: add reset-simple to unify socfpga, stm32, sunxi, and zx2967 reset: meson: remove unneeded check in meson_reset_reset reset: meson: add level reset support for GX SoC family reset: uniphier: add PXs3 reset data reset: mediatek: add reset controller dt-bindings required header for MT7622 SoC reset: socfpga: build the reset-socfpga for Stratix10 SOC reset: uniphier: add ethernet reset control support reset: socfpga: fix for 64-bit compilation ARC: reset: introduce AXS10x reset driver
This commit is contained in:
Arnd Bergmann
commit
8193d9ae37
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@ -0,0 +1,33 @@
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Binding for the AXS10x reset controller
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This binding describes the ARC AXS10x boards custom IP-block which allows
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to control reset signals of selected peripherals. For example DW GMAC, etc...
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This block is controlled via memory-mapped register (AKA CREG) which
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represents up-to 32 reset lines.
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As of today only the following lines are used:
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- DW GMAC - line 5
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This binding uses the common reset binding[1].
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[1] Documentation/devicetree/bindings/reset/reset.txt
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Required properties:
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- compatible: should be "snps,axs10x-reset".
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- reg: should always contain pair address - length: for creg reset
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bits register.
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- #reset-cells: from common reset binding; Should always be set to 1.
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Example:
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reset: reset-controller@11220 {
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compatible = "snps,axs10x-reset";
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#reset-cells = <1>;
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reg = <0x11220 0x4>;
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};
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Specifying reset lines connected to IP modules:
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ethernet@.... {
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....
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resets = <&reset 5>;
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....
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};
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@ -13,6 +13,7 @@ Required properties:
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"socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
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"socionext,uniphier-ld11-reset" - for LD11 SoC
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"socionext,uniphier-ld20-reset" - for LD20 SoC
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"socionext,uniphier-pxs3-reset" - for PXs3 SoC
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- #reset-cells: should be 1.
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Example:
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@ -44,6 +45,7 @@ Required properties:
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"socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
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"socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD)
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"socionext,uniphier-ld20-sd-reset" - for LD20 SoC
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"socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC
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- #reset-cells: should be 1.
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Example:
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@ -74,6 +76,7 @@ Required properties:
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"socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
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"socionext,uniphier-ld11-peri-reset" - for LD11 SoC
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"socionext,uniphier-ld20-peri-reset" - for LD20 SoC
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"socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
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- #reset-cells: should be 1.
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Example:
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@ -2136,7 +2136,6 @@ F: drivers/gpio/gpio-zx.c
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F: drivers/i2c/busses/i2c-zx2967.c
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F: drivers/mmc/host/dw_mmc-zx.*
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F: drivers/pinctrl/zte/
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F: drivers/reset/reset-zx2967.c
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F: drivers/soc/zte/
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F: drivers/thermal/zx2967_thermal.c
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F: drivers/watchdog/zx2967_wdt.c
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@ -12914,6 +12913,12 @@ F: arch/arc/plat-axs10x
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F: arch/arc/boot/dts/ax*
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F: Documentation/devicetree/bindings/arc/axs10*
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SYNOPSYS AXS10x RESET CONTROLLER DRIVER
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M: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
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S: Supported
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F: drivers/reset/reset-axs10x.c
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F: Documentation/devicetree/bindings/reset/snps,axs10x-reset.txt
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SYNOPSYS DESIGNWARE DMAC DRIVER
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M: Viresh Kumar <vireshk@kernel.org>
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M: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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@ -28,6 +28,12 @@ config RESET_ATH79
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This enables the ATH79 reset controller driver that supports the
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AR71xx SoC reset controller.
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config RESET_AXS10X
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bool "AXS10x Reset Driver" if COMPILE_TEST
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default ARC_PLAT_AXS10X
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help
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This enables the reset controller driver for AXS10x.
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config RESET_BERLIN
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bool "Berlin Reset Driver" if COMPILE_TEST
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default ARCH_BERLIN
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@ -75,21 +81,21 @@ config RESET_PISTACHIO
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help
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This enables the reset driver for ImgTec Pistachio SoCs.
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config RESET_SOCFPGA
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bool "SoCFPGA Reset Driver" if COMPILE_TEST
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default ARCH_SOCFPGA
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config RESET_SIMPLE
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bool "Simple Reset Controller Driver" if COMPILE_TEST
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default ARCH_SOCFPGA || ARCH_STM32 || ARCH_STRATIX10 || ARCH_SUNXI || ARCH_ZX
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help
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This enables the reset controller driver for Altera SoCFPGAs.
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This enables a simple reset controller driver for reset lines that
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that can be asserted and deasserted by toggling bits in a contiguous,
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exclusive register space.
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config RESET_STM32
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bool "STM32 Reset Driver" if COMPILE_TEST
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default ARCH_STM32
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help
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This enables the RCC reset controller driver for STM32 MCUs.
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Currently this driver supports Altera SoCFPGAs, the RCC reset
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controller in STM32 MCUs, Allwinner SoCs, and ZTE's zx2967 family.
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config RESET_SUNXI
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bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
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default ARCH_SUNXI
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select RESET_SIMPLE
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help
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This enables the reset driver for Allwinner SoCs.
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@ -121,12 +127,6 @@ config RESET_UNIPHIER
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Say Y if you want to control reset signals provided by System Control
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block, Media I/O block, Peripheral Block.
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config RESET_ZX2967
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bool "ZTE ZX2967 Reset Driver"
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depends on ARCH_ZX || COMPILE_TEST
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help
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This enables the reset controller driver for ZTE's zx2967 family.
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config RESET_ZYNQ
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bool "ZYNQ Reset Driver" if COMPILE_TEST
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default ARCH_ZYNQ
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@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_STI) += sti/
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obj-$(CONFIG_ARCH_TEGRA) += tegra/
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obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
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obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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obj-$(CONFIG_RESET_AXS10X) += reset-axs10x.o
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obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
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obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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@ -12,12 +13,10 @@ obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
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obj-$(CONFIG_RESET_MESON) += reset-meson.o
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obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
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obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
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obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
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obj-$(CONFIG_RESET_STM32) += reset-stm32.o
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obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
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obj-$(CONFIG_RESET_TI_SYSCON) += reset-ti-syscon.o
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obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
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obj-$(CONFIG_RESET_ZX2967) += reset-zx2967.o
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obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
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@ -0,0 +1,83 @@
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/*
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* Copyright (C) 2017 Synopsys.
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*
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* Synopsys AXS10x reset driver.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/reset-controller.h>
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#define to_axs10x_rst(p) container_of((p), struct axs10x_rst, rcdev)
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#define AXS10X_MAX_RESETS 32
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struct axs10x_rst {
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void __iomem *regs_rst;
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spinlock_t lock;
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struct reset_controller_dev rcdev;
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};
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static int axs10x_reset_reset(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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struct axs10x_rst *rst = to_axs10x_rst(rcdev);
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unsigned long flags;
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spin_lock_irqsave(&rst->lock, flags);
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writel(BIT(id), rst->regs_rst);
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spin_unlock_irqrestore(&rst->lock, flags);
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return 0;
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}
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static const struct reset_control_ops axs10x_reset_ops = {
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.reset = axs10x_reset_reset,
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};
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static int axs10x_reset_probe(struct platform_device *pdev)
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{
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struct axs10x_rst *rst;
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struct resource *mem;
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rst = devm_kzalloc(&pdev->dev, sizeof(*rst), GFP_KERNEL);
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if (!rst)
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return -ENOMEM;
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mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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rst->regs_rst = devm_ioremap_resource(&pdev->dev, mem);
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if (IS_ERR(rst->regs_rst))
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return PTR_ERR(rst->regs_rst);
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spin_lock_init(&rst->lock);
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rst->rcdev.owner = THIS_MODULE;
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rst->rcdev.ops = &axs10x_reset_ops;
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rst->rcdev.of_node = pdev->dev.of_node;
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rst->rcdev.nr_resets = AXS10X_MAX_RESETS;
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return devm_reset_controller_register(&pdev->dev, &rst->rcdev);
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}
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static const struct of_device_id axs10x_reset_dt_match[] = {
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{ .compatible = "snps,axs10x-reset" },
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{ },
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};
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static struct platform_driver axs10x_reset_driver = {
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.probe = axs10x_reset_probe,
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.driver = {
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.name = "axs10x-reset",
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.of_match_table = axs10x_reset_dt_match,
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},
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};
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builtin_platform_driver(axs10x_reset_driver);
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MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>");
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MODULE_DESCRIPTION("Synopsys AXS10x reset driver");
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MODULE_LICENSE("GPL v2");
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@ -62,13 +62,16 @@
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#include <linux/reset-controller.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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#include <linux/of_device.h>
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#define REG_COUNT 8
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#define BITS_PER_REG 32
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#define LEVEL_OFFSET 0x7c
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struct meson_reset {
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void __iomem *reg_base;
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struct reset_controller_dev rcdev;
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spinlock_t lock;
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};
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static int meson_reset_reset(struct reset_controller_dev *rcdev,
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@ -80,26 +83,68 @@ static int meson_reset_reset(struct reset_controller_dev *rcdev,
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unsigned int offset = id % BITS_PER_REG;
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void __iomem *reg_addr = data->reg_base + (bank << 2);
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if (bank >= REG_COUNT)
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return -EINVAL;
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writel(BIT(offset), reg_addr);
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return 0;
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}
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static const struct reset_control_ops meson_reset_ops = {
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static int meson_reset_level(struct reset_controller_dev *rcdev,
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unsigned long id, bool assert)
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{
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struct meson_reset *data =
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container_of(rcdev, struct meson_reset, rcdev);
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unsigned int bank = id / BITS_PER_REG;
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unsigned int offset = id % BITS_PER_REG;
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void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
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unsigned long flags;
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u32 reg;
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spin_lock_irqsave(&data->lock, flags);
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reg = readl(reg_addr);
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if (assert)
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writel(reg & ~BIT(offset), reg_addr);
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else
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writel(reg | BIT(offset), reg_addr);
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spin_unlock_irqrestore(&data->lock, flags);
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return 0;
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}
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static int meson_reset_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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return meson_reset_level(rcdev, id, true);
|
||||
}
|
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|
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static int meson_reset_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
|
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return meson_reset_level(rcdev, id, false);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops meson_reset_meson8_ops = {
|
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.reset = meson_reset_reset,
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};
|
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|
||||
static const struct reset_control_ops meson_reset_gx_ops = {
|
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.reset = meson_reset_reset,
|
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.assert = meson_reset_assert,
|
||||
.deassert = meson_reset_deassert,
|
||||
};
|
||||
|
||||
static const struct of_device_id meson_reset_dt_ids[] = {
|
||||
{ .compatible = "amlogic,meson8b-reset", },
|
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{ .compatible = "amlogic,meson-gxbb-reset", },
|
||||
{ .compatible = "amlogic,meson8b-reset",
|
||||
.data = &meson_reset_meson8_ops, },
|
||||
{ .compatible = "amlogic,meson-gxbb-reset",
|
||||
.data = &meson_reset_gx_ops, },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int meson_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct reset_control_ops *ops;
|
||||
struct meson_reset *data;
|
||||
struct resource *res;
|
||||
|
||||
|
|
@ -107,6 +152,10 @@ static int meson_reset_probe(struct platform_device *pdev)
|
|||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
ops = of_device_get_match_data(&pdev->dev);
|
||||
if (!ops)
|
||||
return -EINVAL;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
data->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(data->reg_base))
|
||||
|
|
@ -114,9 +163,11 @@ static int meson_reset_probe(struct platform_device *pdev)
|
|||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
|
||||
data->rcdev.ops = &meson_reset_ops;
|
||||
data->rcdev.ops = ops;
|
||||
data->rcdev.of_node = pdev->dev.of_node;
|
||||
|
||||
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,186 @@
|
|||
/*
|
||||
* Simple Reset Controller Driver
|
||||
*
|
||||
* Copyright (C) 2017 Pengutronix, Philipp Zabel <kernel@pengutronix.de>
|
||||
*
|
||||
* Based on Allwinner SoCs Reset Controller driver
|
||||
*
|
||||
* Copyright 2013 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
#include "reset-simple.h"
|
||||
|
||||
static inline struct reset_simple_data *
|
||||
to_reset_simple_data(struct reset_controller_dev *rcdev)
|
||||
{
|
||||
return container_of(rcdev, struct reset_simple_data, rcdev);
|
||||
}
|
||||
|
||||
static int reset_simple_update(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct reset_simple_data *data = to_reset_simple_data(rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
if (assert ^ data->active_low)
|
||||
reg |= BIT(offset);
|
||||
else
|
||||
reg &= ~BIT(offset);
|
||||
writel(reg, data->membase + (bank * reg_width));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int reset_simple_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return reset_simple_update(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int reset_simple_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return reset_simple_update(rcdev, id, false);
|
||||
}
|
||||
|
||||
static int reset_simple_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct reset_simple_data *data = to_reset_simple_data(rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
u32 reg;
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
|
||||
return !(reg & BIT(offset)) ^ !data->status_active_low;
|
||||
}
|
||||
|
||||
const struct reset_control_ops reset_simple_ops = {
|
||||
.assert = reset_simple_assert,
|
||||
.deassert = reset_simple_deassert,
|
||||
.status = reset_simple_status,
|
||||
};
|
||||
|
||||
/**
|
||||
* struct reset_simple_devdata - simple reset controller properties
|
||||
* @reg_offset: offset between base address and first reset register.
|
||||
* @nr_resets: number of resets. If not set, default to resource size in bits.
|
||||
* @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
|
||||
* are set to assert the reset.
|
||||
* @status_active_low: if true, bits read back as cleared while the reset is
|
||||
* asserted. Otherwise, bits read back as set while the
|
||||
* reset is asserted.
|
||||
*/
|
||||
struct reset_simple_devdata {
|
||||
u32 reg_offset;
|
||||
u32 nr_resets;
|
||||
bool active_low;
|
||||
bool status_active_low;
|
||||
};
|
||||
|
||||
#define SOCFPGA_NR_BANKS 8
|
||||
|
||||
static const struct reset_simple_devdata reset_simple_socfpga = {
|
||||
.reg_offset = 0x10,
|
||||
.nr_resets = SOCFPGA_NR_BANKS * 32,
|
||||
.status_active_low = true,
|
||||
};
|
||||
|
||||
static const struct reset_simple_devdata reset_simple_active_low = {
|
||||
.active_low = true,
|
||||
.status_active_low = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id reset_simple_dt_ids[] = {
|
||||
{ .compatible = "altr,rst-mgr", .data = &reset_simple_socfpga },
|
||||
{ .compatible = "st,stm32-rcc", },
|
||||
{ .compatible = "allwinner,sun6i-a31-clock-reset",
|
||||
.data = &reset_simple_active_low },
|
||||
{ .compatible = "zte,zx296718-reset",
|
||||
.data = &reset_simple_active_low },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int reset_simple_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
const struct reset_simple_devdata *devdata;
|
||||
struct reset_simple_data *data;
|
||||
void __iomem *membase;
|
||||
struct resource *res;
|
||||
u32 reg_offset = 0;
|
||||
|
||||
devdata = of_device_get_match_data(dev);
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
membase = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(membase))
|
||||
return PTR_ERR(membase);
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
data->membase = membase;
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = resource_size(res) * BITS_PER_BYTE;
|
||||
data->rcdev.ops = &reset_simple_ops;
|
||||
data->rcdev.of_node = dev->of_node;
|
||||
|
||||
if (devdata) {
|
||||
reg_offset = devdata->reg_offset;
|
||||
if (devdata->nr_resets)
|
||||
data->rcdev.nr_resets = devdata->nr_resets;
|
||||
data->active_low = devdata->active_low;
|
||||
data->status_active_low = devdata->status_active_low;
|
||||
}
|
||||
|
||||
if (of_device_is_compatible(dev->of_node, "altr,rst-mgr") &&
|
||||
of_property_read_u32(dev->of_node, "altr,modrst-offset",
|
||||
®_offset)) {
|
||||
dev_warn(dev,
|
||||
"missing altr,modrst-offset property, assuming 0x%x!\n",
|
||||
reg_offset);
|
||||
}
|
||||
|
||||
data->membase += reg_offset;
|
||||
|
||||
return devm_reset_controller_register(dev, &data->rcdev);
|
||||
}
|
||||
|
||||
static struct platform_driver reset_simple_driver = {
|
||||
.probe = reset_simple_probe,
|
||||
.driver = {
|
||||
.name = "simple-reset",
|
||||
.of_match_table = reset_simple_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(reset_simple_driver);
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/*
|
||||
* Simple Reset Controller ops
|
||||
*
|
||||
* Based on Allwinner SoCs Reset Controller driver
|
||||
*
|
||||
* Copyright 2013 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __RESET_SIMPLE_H__
|
||||
#define __RESET_SIMPLE_H__
|
||||
|
||||
#include <linux/io.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
/**
|
||||
* struct reset_simple_data - driver data for simple reset controllers
|
||||
* @lock: spinlock to protect registers during read-modify-write cycles
|
||||
* @membase: memory mapped I/O register range
|
||||
* @rcdev: reset controller device base structure
|
||||
* @active_low: if true, bits are cleared to assert the reset. Otherwise, bits
|
||||
* are set to assert the reset. Note that this says nothing about
|
||||
* the voltage level of the actual reset line.
|
||||
* @status_active_low: if true, bits read back as cleared while the reset is
|
||||
* asserted. Otherwise, bits read back as set while the
|
||||
* reset is asserted.
|
||||
*/
|
||||
struct reset_simple_data {
|
||||
spinlock_t lock;
|
||||
void __iomem *membase;
|
||||
struct reset_controller_dev rcdev;
|
||||
bool active_low;
|
||||
bool status_active_low;
|
||||
};
|
||||
|
||||
extern const struct reset_control_ops reset_simple_ops;
|
||||
|
||||
#endif /* __RESET_SIMPLE_H__ */
|
||||
|
|
@ -1,154 +0,0 @@
|
|||
/*
|
||||
* Socfpga Reset Controller Driver
|
||||
*
|
||||
* Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
|
||||
*
|
||||
* based on
|
||||
* Allwinner SoCs Reset Controller driver
|
||||
*
|
||||
* Copyright 2013 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#define BANK_INCREMENT 4
|
||||
#define NR_BANKS 8
|
||||
|
||||
struct socfpga_reset_data {
|
||||
spinlock_t lock;
|
||||
void __iomem *membase;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct socfpga_reset_data *data = container_of(rcdev,
|
||||
struct socfpga_reset_data,
|
||||
rcdev);
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * BANK_INCREMENT));
|
||||
writel(reg | BIT(offset), data->membase + (bank * BANK_INCREMENT));
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct socfpga_reset_data *data = container_of(rcdev,
|
||||
struct socfpga_reset_data,
|
||||
rcdev);
|
||||
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * BANK_INCREMENT));
|
||||
writel(reg & ~BIT(offset), data->membase + (bank * BANK_INCREMENT));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int socfpga_reset_status(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct socfpga_reset_data *data = container_of(rcdev,
|
||||
struct socfpga_reset_data, rcdev);
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
u32 reg;
|
||||
|
||||
reg = readl(data->membase + (bank * BANK_INCREMENT));
|
||||
|
||||
return !(reg & BIT(offset));
|
||||
}
|
||||
|
||||
static const struct reset_control_ops socfpga_reset_ops = {
|
||||
.assert = socfpga_reset_assert,
|
||||
.deassert = socfpga_reset_deassert,
|
||||
.status = socfpga_reset_status,
|
||||
};
|
||||
|
||||
static int socfpga_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct socfpga_reset_data *data;
|
||||
struct resource *res;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct device_node *np = dev->of_node;
|
||||
u32 modrst_offset;
|
||||
|
||||
/*
|
||||
* The binding was mainlined without the required property.
|
||||
* Do not continue, when we encounter an old DT.
|
||||
*/
|
||||
if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
|
||||
dev_err(&pdev->dev, "%pOF missing #reset-cells property\n",
|
||||
pdev->dev.of_node);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
data->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(data->membase))
|
||||
return PTR_ERR(data->membase);
|
||||
|
||||
if (of_property_read_u32(np, "altr,modrst-offset", &modrst_offset)) {
|
||||
dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
|
||||
modrst_offset = 0x10;
|
||||
}
|
||||
data->membase += modrst_offset;
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
|
||||
data->rcdev.ops = &socfpga_reset_ops;
|
||||
data->rcdev.of_node = pdev->dev.of_node;
|
||||
|
||||
return devm_reset_controller_register(dev, &data->rcdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id socfpga_reset_dt_ids[] = {
|
||||
{ .compatible = "altr,rst-mgr", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static struct platform_driver socfpga_reset_driver = {
|
||||
.probe = socfpga_reset_probe,
|
||||
.driver = {
|
||||
.name = "socfpga-reset",
|
||||
.of_match_table = socfpga_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(socfpga_reset_driver);
|
||||
|
|
@ -1,108 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) Maxime Coquelin 2015
|
||||
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
|
||||
* License terms: GNU General Public License (GPL), version 2
|
||||
*
|
||||
* Heavily based on sunxi driver from Maxime Ripard.
|
||||
*/
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct stm32_reset_data {
|
||||
spinlock_t lock;
|
||||
void __iomem *membase;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
static int stm32_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct stm32_reset_data *data = container_of(rcdev,
|
||||
struct stm32_reset_data,
|
||||
rcdev);
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * 4));
|
||||
writel(reg | BIT(offset), data->membase + (bank * 4));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct stm32_reset_data *data = container_of(rcdev,
|
||||
struct stm32_reset_data,
|
||||
rcdev);
|
||||
int bank = id / BITS_PER_LONG;
|
||||
int offset = id % BITS_PER_LONG;
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * 4));
|
||||
writel(reg & ~BIT(offset), data->membase + (bank * 4));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct reset_control_ops stm32_reset_ops = {
|
||||
.assert = stm32_reset_assert,
|
||||
.deassert = stm32_reset_deassert,
|
||||
};
|
||||
|
||||
static const struct of_device_id stm32_reset_dt_ids[] = {
|
||||
{ .compatible = "st,stm32-rcc", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int stm32_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct stm32_reset_data *data;
|
||||
struct resource *res;
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
data->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(data->membase))
|
||||
return PTR_ERR(data->membase);
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = resource_size(res) * 8;
|
||||
data->rcdev.ops = &stm32_reset_ops;
|
||||
data->rcdev.of_node = pdev->dev.of_node;
|
||||
|
||||
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
|
||||
}
|
||||
|
||||
static struct platform_driver stm32_reset_driver = {
|
||||
.probe = stm32_reset_probe,
|
||||
.driver = {
|
||||
.name = "stm32-rcc-reset",
|
||||
.of_match_table = stm32_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(stm32_reset_driver);
|
||||
|
|
@ -22,64 +22,11 @@
|
|||
#include <linux/spinlock.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
struct sunxi_reset_data {
|
||||
spinlock_t lock;
|
||||
void __iomem *membase;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
static int sunxi_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct sunxi_reset_data *data = container_of(rcdev,
|
||||
struct sunxi_reset_data,
|
||||
rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
writel(reg & ~BIT(offset), data->membase + (bank * reg_width));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sunxi_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
struct sunxi_reset_data *data = container_of(rcdev,
|
||||
struct sunxi_reset_data,
|
||||
rcdev);
|
||||
int reg_width = sizeof(u32);
|
||||
int bank = id / (reg_width * BITS_PER_BYTE);
|
||||
int offset = id % (reg_width * BITS_PER_BYTE);
|
||||
unsigned long flags;
|
||||
u32 reg;
|
||||
|
||||
spin_lock_irqsave(&data->lock, flags);
|
||||
|
||||
reg = readl(data->membase + (bank * reg_width));
|
||||
writel(reg | BIT(offset), data->membase + (bank * reg_width));
|
||||
|
||||
spin_unlock_irqrestore(&data->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct reset_control_ops sunxi_reset_ops = {
|
||||
.assert = sunxi_reset_assert,
|
||||
.deassert = sunxi_reset_deassert,
|
||||
};
|
||||
#include "reset-simple.h"
|
||||
|
||||
static int sunxi_reset_init(struct device_node *np)
|
||||
{
|
||||
struct sunxi_reset_data *data;
|
||||
struct reset_simple_data *data;
|
||||
struct resource res;
|
||||
resource_size_t size;
|
||||
int ret;
|
||||
|
|
@ -108,8 +55,9 @@ static int sunxi_reset_init(struct device_node *np)
|
|||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = size * 8;
|
||||
data->rcdev.ops = &sunxi_reset_ops;
|
||||
data->rcdev.ops = &reset_simple_ops;
|
||||
data->rcdev.of_node = np;
|
||||
data->active_low = true;
|
||||
|
||||
return reset_controller_register(&data->rcdev);
|
||||
|
||||
|
|
@ -122,6 +70,8 @@ err_alloc:
|
|||
* These are the reset controller we need to initialize early on in
|
||||
* our system, before we can even think of using a regular device
|
||||
* driver for it.
|
||||
* The controllers that we can register through the regular device
|
||||
* model are handled by the simple reset driver directly.
|
||||
*/
|
||||
static const struct of_device_id sunxi_early_reset_dt_ids[] __initconst = {
|
||||
{ .compatible = "allwinner,sun6i-a31-ahb1-reset", },
|
||||
|
|
@ -135,45 +85,3 @@ void __init sun6i_reset_init(void)
|
|||
for_each_matching_node(np, sunxi_early_reset_dt_ids)
|
||||
sunxi_reset_init(np);
|
||||
}
|
||||
|
||||
/*
|
||||
* And these are the controllers we can register through the regular
|
||||
* device model.
|
||||
*/
|
||||
static const struct of_device_id sunxi_reset_dt_ids[] = {
|
||||
{ .compatible = "allwinner,sun6i-a31-clock-reset", },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
|
||||
static int sunxi_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct sunxi_reset_data *data;
|
||||
struct resource *res;
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
data->membase = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(data->membase))
|
||||
return PTR_ERR(data->membase);
|
||||
|
||||
spin_lock_init(&data->lock);
|
||||
|
||||
data->rcdev.owner = THIS_MODULE;
|
||||
data->rcdev.nr_resets = resource_size(res) * 8;
|
||||
data->rcdev.ops = &sunxi_reset_ops;
|
||||
data->rcdev.of_node = pdev->dev.of_node;
|
||||
|
||||
return devm_reset_controller_register(&pdev->dev, &data->rcdev);
|
||||
}
|
||||
|
||||
static struct platform_driver sunxi_reset_driver = {
|
||||
.probe = sunxi_reset_probe,
|
||||
.driver = {
|
||||
.name = "sunxi-reset",
|
||||
.of_match_table = sunxi_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(sunxi_reset_driver);
|
||||
|
|
|
|||
|
|
@ -58,6 +58,7 @@ static const struct uniphier_reset_data uniphier_ld4_sys_reset_data[] = {
|
|||
|
||||
static const struct uniphier_reset_data uniphier_pro4_sys_reset_data[] = {
|
||||
UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
|
||||
UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
|
||||
UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, MIO, RLE) */
|
||||
UNIPHIER_RESETX(12, 0x2000, 6), /* GIO (Ether, SATA, USB3) */
|
||||
UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
|
||||
|
|
@ -76,6 +77,7 @@ static const struct uniphier_reset_data uniphier_pro5_sys_reset_data[] = {
|
|||
|
||||
static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
|
||||
UNIPHIER_RESETX(2, 0x2000, 2), /* NAND */
|
||||
UNIPHIER_RESETX(6, 0x2000, 12), /* Ether */
|
||||
UNIPHIER_RESETX(8, 0x2000, 10), /* STDMAC (HSC, RLE) */
|
||||
UNIPHIER_RESETX(14, 0x2000, 17), /* USB30 */
|
||||
UNIPHIER_RESETX(15, 0x2004, 17), /* USB31 */
|
||||
|
|
@ -92,6 +94,7 @@ static const struct uniphier_reset_data uniphier_pxs2_sys_reset_data[] = {
|
|||
static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
|
||||
UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
|
||||
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
|
||||
UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
|
||||
UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC, MIO) */
|
||||
UNIPHIER_RESETX(40, 0x2008, 0), /* AIO */
|
||||
UNIPHIER_RESETX(41, 0x2008, 1), /* EVEA */
|
||||
|
|
@ -102,6 +105,7 @@ static const struct uniphier_reset_data uniphier_ld11_sys_reset_data[] = {
|
|||
static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
|
||||
UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
|
||||
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
|
||||
UNIPHIER_RESETX(6, 0x200c, 6), /* Ether */
|
||||
UNIPHIER_RESETX(8, 0x200c, 8), /* STDMAC (HSC) */
|
||||
UNIPHIER_RESETX(12, 0x200c, 5), /* GIO (PCIe, USB3) */
|
||||
UNIPHIER_RESETX(16, 0x200c, 12), /* USB30-PHY0 */
|
||||
|
|
@ -114,6 +118,20 @@ static const struct uniphier_reset_data uniphier_ld20_sys_reset_data[] = {
|
|||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
static const struct uniphier_reset_data uniphier_pxs3_sys_reset_data[] = {
|
||||
UNIPHIER_RESETX(2, 0x200c, 0), /* NAND */
|
||||
UNIPHIER_RESETX(4, 0x200c, 2), /* eMMC */
|
||||
UNIPHIER_RESETX(8, 0x200c, 12), /* STDMAC */
|
||||
UNIPHIER_RESETX(12, 0x200c, 4), /* USB30 link (GIO0) */
|
||||
UNIPHIER_RESETX(13, 0x200c, 5), /* USB31 link (GIO1) */
|
||||
UNIPHIER_RESETX(16, 0x200c, 16), /* USB30-PHY0 */
|
||||
UNIPHIER_RESETX(17, 0x200c, 18), /* USB30-PHY1 */
|
||||
UNIPHIER_RESETX(18, 0x200c, 20), /* USB30-PHY2 */
|
||||
UNIPHIER_RESETX(20, 0x200c, 17), /* USB31-PHY0 */
|
||||
UNIPHIER_RESETX(21, 0x200c, 19), /* USB31-PHY1 */
|
||||
UNIPHIER_RESET_END,
|
||||
};
|
||||
|
||||
/* Media I/O reset data */
|
||||
#define UNIPHIER_MIO_RESET_SD(id, ch) \
|
||||
UNIPHIER_RESETX((id), 0x110 + 0x200 * (ch), 0)
|
||||
|
|
@ -359,6 +377,10 @@ static const struct of_device_id uniphier_reset_match[] = {
|
|||
.compatible = "socionext,uniphier-ld20-reset",
|
||||
.data = uniphier_ld20_sys_reset_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,uniphier-pxs3-reset",
|
||||
.data = uniphier_pxs3_sys_reset_data,
|
||||
},
|
||||
/* Media I/O reset, SD reset */
|
||||
{
|
||||
.compatible = "socionext,uniphier-ld4-mio-reset",
|
||||
|
|
@ -392,6 +414,10 @@ static const struct of_device_id uniphier_reset_match[] = {
|
|||
.compatible = "socionext,uniphier-ld20-sd-reset",
|
||||
.data = uniphier_pro5_sd_reset_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,uniphier-pxs3-sd-reset",
|
||||
.data = uniphier_pro5_sd_reset_data,
|
||||
},
|
||||
/* Peripheral reset */
|
||||
{
|
||||
.compatible = "socionext,uniphier-ld4-peri-reset",
|
||||
|
|
@ -421,6 +447,10 @@ static const struct of_device_id uniphier_reset_match[] = {
|
|||
.compatible = "socionext,uniphier-ld20-peri-reset",
|
||||
.data = uniphier_pro4_peri_reset_data,
|
||||
},
|
||||
{
|
||||
.compatible = "socionext,uniphier-pxs3-peri-reset",
|
||||
.data = uniphier_pro4_peri_reset_data,
|
||||
},
|
||||
/* Analog signal amplifiers reset */
|
||||
{
|
||||
.compatible = "socionext,uniphier-ld11-adamv-reset",
|
||||
|
|
|
|||
|
|
@ -1,99 +0,0 @@
|
|||
/*
|
||||
* ZTE's zx2967 family reset controller driver
|
||||
*
|
||||
* Copyright (C) 2017 ZTE Ltd.
|
||||
*
|
||||
* Author: Baoyou Xie <baoyou.xie@linaro.org>
|
||||
*
|
||||
* License terms: GNU General Public License (GPL) version 2
|
||||
*/
|
||||
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/reset-controller.h>
|
||||
|
||||
struct zx2967_reset {
|
||||
void __iomem *reg_base;
|
||||
spinlock_t lock;
|
||||
struct reset_controller_dev rcdev;
|
||||
};
|
||||
|
||||
static int zx2967_reset_act(struct reset_controller_dev *rcdev,
|
||||
unsigned long id, bool assert)
|
||||
{
|
||||
struct zx2967_reset *reset = NULL;
|
||||
int bank = id / 32;
|
||||
int offset = id % 32;
|
||||
u32 reg;
|
||||
unsigned long flags;
|
||||
|
||||
reset = container_of(rcdev, struct zx2967_reset, rcdev);
|
||||
|
||||
spin_lock_irqsave(&reset->lock, flags);
|
||||
|
||||
reg = readl_relaxed(reset->reg_base + (bank * 4));
|
||||
if (assert)
|
||||
reg &= ~BIT(offset);
|
||||
else
|
||||
reg |= BIT(offset);
|
||||
writel_relaxed(reg, reset->reg_base + (bank * 4));
|
||||
|
||||
spin_unlock_irqrestore(&reset->lock, flags);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int zx2967_reset_assert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return zx2967_reset_act(rcdev, id, true);
|
||||
}
|
||||
|
||||
static int zx2967_reset_deassert(struct reset_controller_dev *rcdev,
|
||||
unsigned long id)
|
||||
{
|
||||
return zx2967_reset_act(rcdev, id, false);
|
||||
}
|
||||
|
||||
static const struct reset_control_ops zx2967_reset_ops = {
|
||||
.assert = zx2967_reset_assert,
|
||||
.deassert = zx2967_reset_deassert,
|
||||
};
|
||||
|
||||
static int zx2967_reset_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct zx2967_reset *reset;
|
||||
struct resource *res;
|
||||
|
||||
reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
|
||||
if (!reset)
|
||||
return -ENOMEM;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
reset->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
||||
if (IS_ERR(reset->reg_base))
|
||||
return PTR_ERR(reset->reg_base);
|
||||
|
||||
spin_lock_init(&reset->lock);
|
||||
|
||||
reset->rcdev.owner = THIS_MODULE;
|
||||
reset->rcdev.nr_resets = resource_size(res) * 8;
|
||||
reset->rcdev.ops = &zx2967_reset_ops;
|
||||
reset->rcdev.of_node = pdev->dev.of_node;
|
||||
|
||||
return devm_reset_controller_register(&pdev->dev, &reset->rcdev);
|
||||
}
|
||||
|
||||
static const struct of_device_id zx2967_reset_dt_ids[] = {
|
||||
{ .compatible = "zte,zx296718-reset", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver zx2967_reset_driver = {
|
||||
.probe = zx2967_reset_probe,
|
||||
.driver = {
|
||||
.name = "zx2967-reset",
|
||||
.of_match_table = zx2967_reset_dt_ids,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(zx2967_reset_driver);
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
/*
|
||||
* Copyright (c) 2017 MediaTek Inc.
|
||||
* Author: Sean Wang <sean.wang@mediatek.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
|
||||
#define _DT_BINDINGS_RESET_CONTROLLER_MT7622
|
||||
|
||||
/* INFRACFG resets */
|
||||
#define MT7622_INFRA_EMI_REG_RST 0
|
||||
#define MT7622_INFRA_DRAMC0_A0_RST 1
|
||||
#define MT7622_INFRA_APCIRQ_EINT_RST 3
|
||||
#define MT7622_INFRA_APXGPT_RST 4
|
||||
#define MT7622_INFRA_SCPSYS_RST 5
|
||||
#define MT7622_INFRA_PMIC_WRAP_RST 7
|
||||
#define MT7622_INFRA_IRRX_RST 9
|
||||
#define MT7622_INFRA_EMI_RST 16
|
||||
#define MT7622_INFRA_WED0_RST 17
|
||||
#define MT7622_INFRA_DRAMC_RST 18
|
||||
#define MT7622_INFRA_CCI_INTF_RST 19
|
||||
#define MT7622_INFRA_TRNG_RST 21
|
||||
#define MT7622_INFRA_SYSIRQ_RST 22
|
||||
#define MT7622_INFRA_WED1_RST 25
|
||||
|
||||
/* PERICFG Subsystem resets */
|
||||
#define MT7622_PERI_UART0_SW_RST 0
|
||||
#define MT7622_PERI_UART1_SW_RST 1
|
||||
#define MT7622_PERI_UART2_SW_RST 2
|
||||
#define MT7622_PERI_UART3_SW_RST 3
|
||||
#define MT7622_PERI_UART4_SW_RST 4
|
||||
#define MT7622_PERI_BTIF_SW_RST 6
|
||||
#define MT7622_PERI_PWM_SW_RST 8
|
||||
#define MT7622_PERI_AUXADC_SW_RST 10
|
||||
#define MT7622_PERI_DMA_SW_RST 11
|
||||
#define MT7622_PERI_IRTX_SW_RST 13
|
||||
#define MT7622_PERI_NFI_SW_RST 14
|
||||
#define MT7622_PERI_THERM_SW_RST 16
|
||||
#define MT7622_PERI_MSDC0_SW_RST 19
|
||||
#define MT7622_PERI_MSDC1_SW_RST 20
|
||||
#define MT7622_PERI_I2C0_SW_RST 22
|
||||
#define MT7622_PERI_I2C1_SW_RST 23
|
||||
#define MT7622_PERI_I2C2_SW_RST 24
|
||||
#define MT7622_PERI_SPI0_SW_RST 33
|
||||
#define MT7622_PERI_SPI1_SW_RST 34
|
||||
#define MT7622_PERI_FLASHIF_SW_RST 36
|
||||
|
||||
/* TOPRGU resets */
|
||||
#define MT7622_TOPRGU_INFRA_RST 0
|
||||
#define MT7622_TOPRGU_ETHDMA_RST 1
|
||||
#define MT7622_TOPRGU_DDRPHY_RST 6
|
||||
#define MT7622_TOPRGU_INFRA_AO_RST 8
|
||||
#define MT7622_TOPRGU_CONN_RST 9
|
||||
#define MT7622_TOPRGU_APMIXED_RST 10
|
||||
#define MT7622_TOPRGU_CONN_MCU_RST 12
|
||||
|
||||
/* PCIe/SATA Subsystem resets */
|
||||
#define MT7622_SATA_PHY_REG_RST 12
|
||||
#define MT7622_SATA_PHY_SW_RST 13
|
||||
#define MT7622_SATA_AXI_BUS_RST 15
|
||||
#define MT7622_PCIE1_CORE_RST 19
|
||||
#define MT7622_PCIE1_MMIO_RST 20
|
||||
#define MT7622_PCIE1_HRST 21
|
||||
#define MT7622_PCIE1_USER_RST 22
|
||||
#define MT7622_PCIE1_PIPE_RST 23
|
||||
#define MT7622_PCIE0_CORE_RST 27
|
||||
#define MT7622_PCIE0_MMIO_RST 28
|
||||
#define MT7622_PCIE0_HRST 29
|
||||
#define MT7622_PCIE0_USER_RST 30
|
||||
#define MT7622_PCIE0_PIPE_RST 31
|
||||
|
||||
/* SSUSB Subsystem resets */
|
||||
#define MT7622_SSUSB_PHY_PWR_RST 3
|
||||
#define MT7622_SSUSB_MAC_PWR_RST 4
|
||||
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/* ETHSYS Subsystem resets */
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#define MT7622_ETHSYS_SYS_RST 0
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#define MT7622_ETHSYS_MCM_RST 2
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#define MT7622_ETHSYS_HSDMA_RST 5
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#define MT7622_ETHSYS_FE_RST 6
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#define MT7622_ETHSYS_GMAC_RST 23
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#define MT7622_ETHSYS_EPHY_RST 24
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#define MT7622_ETHSYS_CRYPTO_RST 29
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#define MT7622_ETHSYS_PPE_RST 31
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||||
|
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#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */
|
||||
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Reference in New Issue