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Merge branch 'i2c-for-2630-rc5' of git://aeryn.fluff.org.uk/bjdooks/linux 

* 'i2c-for-2630-rc5' of git://aeryn.fluff.org.uk/bjdooks/linux:
  i2c-cpm: Pass dev ptr to dma_*_coherent rather than NULL
  i2c: Enable i2c-s3c2410 for S3C64XX too
  i2c-mpc: bug fix for MPC52xx clock setting and printout
  i2c-pxa.c: timeouts off by 1
This commit is contained in:
Linus Torvalds 2009-05-12 11:21:51 -07:00
parent 3b4334e200 36521c271e
commit 816dc3c82b
4 changed files with 32 additions and 26 deletions
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2
drivers/i2c/busses/Kconfig
View File

@ -467,7 +467,7 @@ config I2C_PXA_SLAVE
config I2C_S3C2410 config I2C_S3C2410
tristate "S3C2410 I2C Driver" tristate "S3C2410 I2C Driver"
depends on ARCH_S3C2410 depends on ARCH_S3C2410 || ARCH_S3C64XX
help help
Say Y here to include support for I2C controller in the Say Y here to include support for I2C controller in the
Samsung S3C2410 based System-on-Chip devices. Samsung S3C2410 based System-on-Chip devices.

16
drivers/i2c/busses/i2c-cpm.c
View File

@ -531,16 +531,16 @@ static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm)
rbdf = cpm->rbase; rbdf = cpm->rbase;
for (i = 0; i < CPM_MAXBD; i++) { for (i = 0; i < CPM_MAXBD; i++) {
cpm->rxbuf[i] = dma_alloc_coherent( cpm->rxbuf[i] = dma_alloc_coherent(&cpm->ofdev->dev,
NULL, CPM_MAX_READ + 1, &cpm->rxdma[i], GFP_KERNEL); CPM_MAX_READ + 1,
&cpm->rxdma[i], GFP_KERNEL);
if (!cpm->rxbuf[i]) { if (!cpm->rxbuf[i]) {
ret = -ENOMEM; ret = -ENOMEM;
goto out_muram; goto out_muram;
} }
out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1)); out_be32(&rbdf[i].cbd_bufaddr, ((cpm->rxdma[i] + 1) & ~1));
cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent( cpm->txbuf[i] = (unsigned char *)dma_alloc_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
NULL, CPM_MAX_READ + 1, &cpm->txdma[i], GFP_KERNEL);
if (!cpm->txbuf[i]) { if (!cpm->txbuf[i]) {
ret = -ENOMEM; ret = -ENOMEM;
goto out_muram; goto out_muram;
@ -585,10 +585,10 @@ static int __devinit cpm_i2c_setup(struct cpm_i2c *cpm)
out_muram: out_muram:
for (i = 0; i < CPM_MAXBD; i++) { for (i = 0; i < CPM_MAXBD; i++) {
if (cpm->rxbuf[i]) if (cpm->rxbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1, dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
cpm->rxbuf[i], cpm->rxdma[i]); cpm->rxbuf[i], cpm->rxdma[i]);
if (cpm->txbuf[i]) if (cpm->txbuf[i])
dma_free_coherent(NULL, CPM_MAX_READ + 1, dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
cpm->txbuf[i], cpm->txdma[i]); cpm->txbuf[i], cpm->txdma[i]);
} }
cpm_muram_free(cpm->dp_addr); cpm_muram_free(cpm->dp_addr);
@ -619,9 +619,9 @@ static void cpm_i2c_shutdown(struct cpm_i2c *cpm)
/* Free all memory */ /* Free all memory */
for (i = 0; i < CPM_MAXBD; i++) { for (i = 0; i < CPM_MAXBD; i++) {
dma_free_coherent(NULL, CPM_MAX_READ + 1, dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
cpm->rxbuf[i], cpm->rxdma[i]); cpm->rxbuf[i], cpm->rxdma[i]);
dma_free_coherent(NULL, CPM_MAX_READ + 1, dma_free_coherent(&cpm->ofdev->dev, CPM_MAX_READ + 1,
cpm->txbuf[i], cpm->txdma[i]); cpm->txbuf[i], cpm->txdma[i]);
} }

34
drivers/i2c/busses/i2c-mpc.c
View File

@ -164,7 +164,7 @@ static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
return 0; return 0;
} }
#ifdef CONFIG_PPC_52xx #ifdef CONFIG_PPC_MPC52xx
static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = { static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
{20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23}, {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
{28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02}, {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
@ -188,7 +188,7 @@ static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler) int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
{ {
const struct mpc52xx_i2c_divider *div = NULL; const struct mpc_i2c_divider *div = NULL;
unsigned int pvr = mfspr(SPRN_PVR); unsigned int pvr = mfspr(SPRN_PVR);
u32 divider; u32 divider;
int i; int i;
@ -203,7 +203,7 @@ int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, int prescaler)
* We want to choose an FDR/DFSR that generates an I2C bus speed that * We want to choose an FDR/DFSR that generates an I2C bus speed that
* is equal to or lower than the requested speed. * is equal to or lower than the requested speed.
*/ */
for (i = 0; i < ARRAY_SIZE(mpc52xx_i2c_dividers); i++) { for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
div = &mpc_i2c_dividers_52xx[i]; div = &mpc_i2c_dividers_52xx[i];
/* Old MPC5200 rev A CPUs do not support the high bits */ /* Old MPC5200 rev A CPUs do not support the high bits */
if (div->fdr & 0xc0 && pvr == 0x80822011) if (div->fdr & 0xc0 && pvr == 0x80822011)
@ -219,20 +219,23 @@ static void mpc_i2c_setclock_52xx(struct device_node *node,
struct mpc_i2c *i2c, struct mpc_i2c *i2c,
u32 clock, u32 prescaler) u32 clock, u32 prescaler)
{ {
int fdr = mpc52xx_i2c_get_fdr(node, clock, prescaler); int ret, fdr;
ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
if (fdr < 0)
fdr = 0x3f; /* backward compatibility */
writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
if (ret >= 0)
dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
} }
#else /* !CONFIG_PPC_52xx */ #else /* !CONFIG_PPC_MPC52xx */
static void mpc_i2c_setclock_52xx(struct device_node *node, static void mpc_i2c_setclock_52xx(struct device_node *node,
struct mpc_i2c *i2c, struct mpc_i2c *i2c,
u32 clock, u32 prescaler) u32 clock, u32 prescaler)
{ {
} }
#endif /* CONFIG_PPC_52xx*/ #endif /* CONFIG_PPC_MPC52xx*/
#ifdef CONFIG_FSL_SOC #ifdef CONFIG_FSL_SOC
static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = { static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
@ -321,14 +324,17 @@ static void mpc_i2c_setclock_8xxx(struct device_node *node,
struct mpc_i2c *i2c, struct mpc_i2c *i2c,
u32 clock, u32 prescaler) u32 clock, u32 prescaler)
{ {
int fdr = mpc_i2c_get_fdr_8xxx(node, clock, prescaler); int ret, fdr;
ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
if (fdr < 0)
fdr = 0x1031; /* backward compatibility */
writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR); writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR); writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
clock, fdr >> 8, fdr & 0xff); if (ret >= 0)
dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
clock, fdr >> 8, fdr & 0xff);
} }
#else /* !CONFIG_FSL_SOC */ #else /* !CONFIG_FSL_SOC */

6
drivers/i2c/busses/i2c-pxa.c
View File

@ -265,10 +265,10 @@ static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
show_state(i2c); show_state(i2c);
} }
if (timeout <= 0) if (timeout < 0)
show_state(i2c); show_state(i2c);
return timeout <= 0 ? I2C_RETRY : 0; return timeout < 0 ? I2C_RETRY : 0;
} }
static int i2c_pxa_wait_master(struct pxa_i2c *i2c) static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
@ -612,7 +612,7 @@ static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
show_state(i2c); show_state(i2c);
} }
if (timeout <= 0) { if (timeout < 0) {
show_state(i2c); show_state(i2c);
dev_err(&i2c->adap.dev, dev_err(&i2c->adap.dev,
"i2c_pxa: timeout waiting for bus free\n"); "i2c_pxa: timeout waiting for bus free\n");