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MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores 

Ingenic uses the CCA:1 bit to achieve write-combine memory writes.

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7401/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras 2014-07-18 10:51:31 +01:00 committed by Ralf Baechle
parent fb02035083
commit 80bc94d104
1 changed files with 5 additions and 0 deletions
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5
arch/mips/include/asm/pgtable-bits.h
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@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
#elif defined(CONFIG_MACH_JZ4740)
/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)
#endif
#ifndef _CACHE_CACHABLE_NO_WA