hollalinux
/
linux-sg2042
mirror of https://github.com/sophgo/linux-riscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'devel-stable' into devel

This commit is contained in:
Russell King 2010-10-19 22:06:36 +01:00
parent a0a55682b8 79a94c3538
commit 809b4e00ba
685 changed files with 21768 additions and 5928 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
CREDITS
View File

@ -3554,12 +3554,12 @@ E: cvance@nai.com
D: portions of the Linux Security Module (LSM) framework and security modules
N: Petr Vandrovec
E: vandrove@vc.cvut.cz
E: petr@vandrovec.name
D: Small contributions to ncpfs
D: Matrox framebuffer driver
S: Chudenicka 8
S: 10200 Prague 10, Hostivar
S: Czech Republic
S: 21513 Conradia Ct
S: Cupertino, CA 95014
S: USA
N: Thibaut Varene
E: T-Bone@parisc-linux.org

2
Documentation/arm/00-INDEX
View File

@ -6,6 +6,8 @@ Interrupts
- ARM Interrupt subsystem documentation
IXP2000
- Release Notes for Linux on Intel's IXP2000 Network Processor
msm
- MSM specific documentation
Netwinder
- Netwinder specific documentation
Porting

176
Documentation/arm/msm/gpiomux.txt Normal file
View File

@ -0,0 +1,176 @@
This document provides an overview of the msm_gpiomux interface, which
is used to provide gpio pin multiplexing and configuration on mach-msm
targets.
History
=======
The first-generation API for gpio configuration & multiplexing on msm
is the function gpio_tlmm_config(). This function has a few notable
shortcomings, which led to its deprecation and replacement by gpiomux:
The 'disable' parameter: Setting the second parameter to
gpio_tlmm_config to GPIO_CFG_DISABLE tells the peripheral
processor in charge of the subsystem to perform a look-up into a
low-power table and apply the low-power/sleep setting for the pin.
As the msm family evolved this became problematic. Not all pins
have sleep settings, not all peripheral processors will accept requests
to apply said sleep settings, and not all msm targets have their gpio
subsystems managed by a peripheral processor. In order to get consistent
behavior on all targets, drivers are forced to ignore this parameter,
rendering it useless.
The 'direction' flag: for all mux-settings other than raw-gpio (0),
the output-enable bit of a gpio is hard-wired to a known
input (usually VDD or ground). For those settings, the direction flag
is meaningless at best, and deceptive at worst. In addition, using the
direction flag to change output-enable (OE) directly can cause trouble in
gpiolib, which has no visibility into gpio direction changes made
in this way. Direction control in gpio mode should be made through gpiolib.
Key Features of gpiomux
=======================
- A consistent interface across all generations of msm. Drivers can expect
the same results on every target.
- gpiomux plays nicely with gpiolib. Functions that should belong to gpiolib
are left to gpiolib and not duplicated here. gpiomux is written with the
intent that gpio_chips will call gpiomux reference-counting methods
from their request() and free() hooks, providing full integration.
- Tabular configuration. Instead of having to call gpio_tlmm_config
hundreds of times, gpio configuration is placed in a single table.
- Per-gpio sleep. Each gpio is individually reference counted, allowing only
those lines which are in use to be put in high-power states.
- 0 means 'do nothing': all flags are designed so that the default memset-zero
equates to a sensible default of 'no configuration', preventing users
from having to provide hundreds of 'no-op' configs for unused or
unwanted lines.
Usage
=====
To use gpiomux, provide configuration information for relevant gpio lines
in the msm_gpiomux_configs table. Since a 0 equates to "unconfigured",
only those lines to be managed by gpiomux need to be specified. Here
is a completely fictional example:
struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
[12] = {
.active = GPIOMUX_VALID | GPIOMUX_DRV_8MA | GPIOMUX_FUNC_1,
.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
},
[34] = {
.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
},
};
To indicate that a gpio is in use, call msm_gpiomux_get() to increase
its reference count. To decrease the reference count, call msm_gpiomux_put().
The effect of this configuration is as follows:
When the system boots, gpios 12 and 34 will be initialized with their
'suspended' configurations. All other gpios, which were left unconfigured,
will not be touched.
When msm_gpiomux_get() is called on gpio 12 to raise its reference count
above 0, its active configuration will be applied. Since no other gpio
line has a valid active configuration, msm_gpiomux_get() will have no
effect on any other line.
When msm_gpiomux_put() is called on gpio 12 or 34 to drop their reference
count to 0, their suspended configurations will be applied.
Since no other gpio line has a valid suspended configuration, no other
gpio line will be effected by msm_gpiomux_put(). Since gpio 34 has no valid
active configuration, this is effectively a no-op for gpio 34 as well,
with one small caveat, see the section "About Output-Enable Settings".
All of the GPIOMUX_VALID flags may seem like unnecessary overhead, but
they address some important issues. As unused entries (all those
except 12 and 34) are zero-filled, gpiomux needs a way to distinguish
the used fields from the unused. In addition, the all-zero pattern
is a valid configuration! Therefore, gpiomux defines an additional bit
which is used to indicate when a field is used. This has the pleasant
side-effect of allowing calls to msm_gpiomux_write to use '0' to indicate
that a value should not be changed:
msm_gpiomux_write(0, GPIOMUX_VALID, 0);
replaces the active configuration of gpio 0 with an all-zero configuration,
but leaves the suspended configuration as it was.
Static Configurations
=====================
To install a static configuration, which is applied at boot and does
not change after that, install a configuration with a suspended component
but no active component, as in the previous example:
[34] = {
.suspended = GPIOMUX_VALID | GPIOMUX_PULL_DOWN,
},
The suspended setting is applied during boot, and the lack of any valid
active setting prevents any other setting from being applied at runtime.
If other subsystems attempting to access the line is a concern, one could
*really* anchor the configuration down by calling msm_gpiomux_get on the
line at initialization to move the line into active mode. With the line
held, it will never be re-suspended, and with no valid active configuration,
no new configurations will be applied.
But then, if having other subsystems grabbing for the line is truly a concern,
it should be reserved with gpio_request instead, which carries an implicit
msm_gpiomux_get.
gpiomux and gpiolib
===================
It is expected that msm gpio_chips will call msm_gpiomux_get() and
msm_gpiomux_put() from their request and free hooks, like this fictional
example:
static int request(struct gpio_chip *chip, unsigned offset)
{
return msm_gpiomux_get(chip->base + offset);
}
static void free(struct gpio_chip *chip, unsigned offset)
{
msm_gpiomux_put(chip->base + offset);
}
...somewhere in a gpio_chip declaration...
.request = request,
.free = free,
This provides important functionality:
- It guarantees that a gpio line will have its 'active' config applied
when the line is requested, and will not be suspended while the line
remains requested; and
- It guarantees that gpio-direction settings from gpiolib behave sensibly.
See "About Output-Enable Settings."
This mechanism allows for "auto-request" of gpiomux lines via gpiolib
when it is suitable. Drivers wishing more exact control are, of course,
free to also use msm_gpiomux_set and msm_gpiomux_get.
About Output-Enable Settings
============================
Some msm targets do not have the ability to query the current gpio
configuration setting. This means that changes made to the output-enable
(OE) bit by gpiolib cannot be consistently detected and preserved by gpiomux.
Therefore, when gpiomux applies a configuration setting, any direction
settings which may have been applied by gpiolib are lost and the default
input settings are re-applied.
For this reason, drivers should not assume that gpio direction settings
continue to hold if they free and then re-request a gpio. This seems like
common sense - after all, anybody could have obtained the line in the
meantime - but it needs saying.
This also means that calls to msm_gpiomux_write will reset the OE bit,
which means that if the gpio line is held by a client of gpiolib and
msm_gpiomux_write is called, the direction setting has been lost and
gpiolib's internal state has been broken.
Release gpio lines before reconfiguring them.

373
Documentation/networking/e1000.txt
View File

@ -1,82 +1,35 @@
Linux* Base Driver for the Intel(R) PRO/1000 Family of Adapters
===============================================================
September 26, 2006
Intel Gigabit Linux driver.
Copyright(c) 1999 - 2010 Intel Corporation.
Contents
========
- In This Release
- Identifying Your Adapter
- Building and Installation
- Command Line Parameters
- Speed and Duplex Configuration
- Additional Configurations
- Known Issues
- Support
In This Release
===============
This file describes the Linux* Base Driver for the Intel(R) PRO/1000 Family
of Adapters. This driver includes support for Itanium(R)2-based systems.
For questions related to hardware requirements, refer to the documentation
supplied with your Intel PRO/1000 adapter. All hardware requirements listed
apply to use with Linux.
The following features are now available in supported kernels:
- Native VLANs
- Channel Bonding (teaming)
- SNMP
Channel Bonding documentation can be found in the Linux kernel source:
/Documentation/networking/bonding.txt
The driver information previously displayed in the /proc filesystem is not
supported in this release. Alternatively, you can use ethtool (version 1.6
or later), lspci, and ifconfig to obtain the same information.
Instructions on updating ethtool can be found in the section "Additional
Configurations" later in this document.
NOTE: The Intel(R) 82562v 10/100 Network Connection only provides 10/100
support.
Identifying Your Adapter
========================
For more information on how to identify your adapter, go to the Adapter &
Driver ID Guide at:
http://support.intel.com/support/network/adapter/pro100/21397.htm
http://support.intel.com/support/go/network/adapter/idguide.htm
For the latest Intel network drivers for Linux, refer to the following
website. In the search field, enter your adapter name or type, or use the
networking link on the left to search for your adapter:
http://downloadfinder.intel.com/scripts-df/support_intel.asp
http://support.intel.com/support/go/network/adapter/home.htm
Command Line Parameters
=======================
If the driver is built as a module, the following optional parameters
are used by entering them on the command line with the modprobe command
using this syntax:
modprobe e1000 [<option>=<VAL1>,<VAL2>,...]
For example, with two PRO/1000 PCI adapters, entering:
modprobe e1000 TxDescriptors=80,128
loads the e1000 driver with 80 TX descriptors for the first adapter and
128 TX descriptors for the second adapter.
The default value for each parameter is generally the recommended setting,
unless otherwise noted.
@ -89,10 +42,6 @@ NOTES: For more information about the AutoNeg, Duplex, and Speed
parameters, see the application note at:
http://www.intel.com/design/network/applnots/ap450.htm
A descriptor describes a data buffer and attributes related to
the data buffer. This information is accessed by the hardware.
AutoNeg
-------
(Supported only on adapters with copper connections)
@ -106,7 +55,6 @@ Duplex parameters must not be specified.
NOTE: Refer to the Speed and Duplex section of this readme for more
information on the AutoNeg parameter.
Duplex
------
(Supported only on adapters with copper connections)
@ -119,7 +67,6 @@ set to auto-negotiate, the board auto-detects the correct duplex. If the
link partner is forced (either full or half), Duplex defaults to half-
duplex.
FlowControl
-----------
Valid Range: 0-3 (0=none, 1=Rx only, 2=Tx only, 3=Rx&Tx)
@ -128,16 +75,16 @@ Default Value: Reads flow control settings from the EEPROM
This parameter controls the automatic generation(Tx) and response(Rx)
to Ethernet PAUSE frames.
InterruptThrottleRate
---------------------
(not supported on Intel(R) 82542, 82543 or 82544-based adapters)
Valid Range: 0,1,3,100-100000 (0=off, 1=dynamic, 3=dynamic conservative)
Valid Range: 0,1,3,4,100-100000 (0=off, 1=dynamic, 3=dynamic conservative,
4=simplified balancing)
Default Value: 3
The driver can limit the amount of interrupts per second that the adapter
will generate for incoming packets. It does this by writing a value to the
adapter that is based on the maximum amount of interrupts that the adapter
will generate for incoming packets. It does this by writing a value to the
adapter that is based on the maximum amount of interrupts that the adapter
will generate per second.
Setting InterruptThrottleRate to a value greater or equal to 100
@ -146,37 +93,43 @@ per second, even if more packets have come in. This reduces interrupt
load on the system and can lower CPU utilization under heavy load,
but will increase latency as packets are not processed as quickly.
The default behaviour of the driver previously assumed a static
InterruptThrottleRate value of 8000, providing a good fallback value for
all traffic types,but lacking in small packet performance and latency.
The hardware can handle many more small packets per second however, and
The default behaviour of the driver previously assumed a static
InterruptThrottleRate value of 8000, providing a good fallback value for
all traffic types,but lacking in small packet performance and latency.
The hardware can handle many more small packets per second however, and
for this reason an adaptive interrupt moderation algorithm was implemented.
Since 7.3.x, the driver has two adaptive modes (setting 1 or 3) in which
it dynamically adjusts the InterruptThrottleRate value based on the traffic
it dynamically adjusts the InterruptThrottleRate value based on the traffic
that it receives. After determining the type of incoming traffic in the last
timeframe, it will adjust the InterruptThrottleRate to an appropriate value
timeframe, it will adjust the InterruptThrottleRate to an appropriate value
for that traffic.
The algorithm classifies the incoming traffic every interval into
classes. Once the class is determined, the InterruptThrottleRate value is
adjusted to suit that traffic type the best. There are three classes defined:
classes. Once the class is determined, the InterruptThrottleRate value is
adjusted to suit that traffic type the best. There are three classes defined:
"Bulk traffic", for large amounts of packets of normal size; "Low latency",
for small amounts of traffic and/or a significant percentage of small
packets; and "Lowest latency", for almost completely small packets or
packets; and "Lowest latency", for almost completely small packets or
minimal traffic.
In dynamic conservative mode, the InterruptThrottleRate value is set to 4000
for traffic that falls in class "Bulk traffic". If traffic falls in the "Low
latency" or "Lowest latency" class, the InterruptThrottleRate is increased
In dynamic conservative mode, the InterruptThrottleRate value is set to 4000
for traffic that falls in class "Bulk traffic". If traffic falls in the "Low
latency" or "Lowest latency" class, the InterruptThrottleRate is increased
stepwise to 20000. This default mode is suitable for most applications.
For situations where low latency is vital such as cluster or
grid computing, the algorithm can reduce latency even more when
InterruptThrottleRate is set to mode 1. In this mode, which operates
the same as mode 3, the InterruptThrottleRate will be increased stepwise to
the same as mode 3, the InterruptThrottleRate will be increased stepwise to
70000 for traffic in class "Lowest latency".
In simplified mode the interrupt rate is based on the ratio of Tx and
Rx traffic. If the bytes per second rate is approximately equal, the
interrupt rate will drop as low as 2000 interrupts per second. If the
traffic is mostly transmit or mostly receive, the interrupt rate could
be as high as 8000.
Setting InterruptThrottleRate to 0 turns off any interrupt moderation
and may improve small packet latency, but is generally not suitable
for bulk throughput traffic.
@ -212,8 +165,6 @@ NOTE: When e1000 is loaded with default settings and multiple adapters
be platform-specific. If CPU utilization is not a concern, use
RX_POLLING (NAPI) and default driver settings.
RxDescriptors
-------------
Valid Range: 80-256 for 82542 and 82543-based adapters
@ -225,15 +176,14 @@ by the driver. Increasing this value allows the driver to buffer more
incoming packets, at the expense of increased system memory utilization.
Each descriptor is 16 bytes. A receive buffer is also allocated for each
descriptor and can be either 2048, 4096, 8192, or 16384 bytes, depending
descriptor and can be either 2048, 4096, 8192, or 16384 bytes, depending
on the MTU setting. The maximum MTU size is 16110.
NOTE: MTU designates the frame size. It only needs to be set for Jumbo
Frames. Depending on the available system resources, the request
for a higher number of receive descriptors may be denied. In this
NOTE: MTU designates the frame size. It only needs to be set for Jumbo
Frames. Depending on the available system resources, the request
for a higher number of receive descriptors may be denied. In this
case, use a lower number.
RxIntDelay
----------
Valid Range: 0-65535 (0=off)
@ -254,7 +204,6 @@ CAUTION: When setting RxIntDelay to a value other than 0, adapters may
restoring the network connection. To eliminate the potential
for the hang ensure that RxIntDelay is set to 0.
RxAbsIntDelay
-------------
(This parameter is supported only on 82540, 82545 and later adapters.)
@ -268,7 +217,6 @@ packet is received within the set amount of time. Proper tuning,
along with RxIntDelay, may improve traffic throughput in specific network
conditions.
Speed
-----
(This parameter is supported only on adapters with copper connections.)
@ -280,7 +228,6 @@ Speed forces the line speed to the specified value in megabits per second
partner is set to auto-negotiate, the board will auto-detect the correct
speed. Duplex should also be set when Speed is set to either 10 or 100.
TxDescriptors
-------------
Valid Range: 80-256 for 82542 and 82543-based adapters
@ -295,6 +242,36 @@ NOTE: Depending on the available system resources, the request for a
higher number of transmit descriptors may be denied. In this case,
use a lower number.
TxDescriptorStep
----------------
Valid Range: 1 (use every Tx Descriptor)
4 (use every 4th Tx Descriptor)
Default Value: 1 (use every Tx Descriptor)
On certain non-Intel architectures, it has been observed that intense TX
traffic bursts of short packets may result in an improper descriptor
writeback. If this occurs, the driver will report a "TX Timeout" and reset
the adapter, after which the transmit flow will restart, though data may
have stalled for as much as 10 seconds before it resumes.
The improper writeback does not occur on the first descriptor in a system
memory cache-line, which is typically 32 bytes, or 4 descriptors long.
Setting TxDescriptorStep to a value of 4 will ensure that all TX descriptors
are aligned to the start of a system memory cache line, and so this problem
will not occur.
NOTES: Setting TxDescriptorStep to 4 effectively reduces the number of
TxDescriptors available for transmits to 1/4 of the normal allocation.
This has a possible negative performance impact, which may be
compensated for by allocating more descriptors using the TxDescriptors
module parameter.
There are other conditions which may result in "TX Timeout", which will
not be resolved by the use of the TxDescriptorStep parameter. As the
issue addressed by this parameter has never been observed on Intel
Architecture platforms, it should not be used on Intel platforms.
TxIntDelay
----------
@ -307,7 +284,6 @@ efficiency if properly tuned for specific network traffic. If the
system is reporting dropped transmits, this value may be set too high
causing the driver to run out of available transmit descriptors.
TxAbsIntDelay
-------------
(This parameter is supported only on 82540, 82545 and later adapters.)
@ -330,6 +306,35 @@ Default Value: 1
A value of '1' indicates that the driver should enable IP checksum
offload for received packets (both UDP and TCP) to the adapter hardware.
Copybreak
---------
Valid Range: 0-xxxxxxx (0=off)
Default Value: 256
Usage: insmod e1000.ko copybreak=128
Driver copies all packets below or equaling this size to a fresh Rx
buffer before handing it up the stack.
This parameter is different than other parameters, in that it is a
single (not 1,1,1 etc.) parameter applied to all driver instances and
it is also available during runtime at
/sys/module/e1000/parameters/copybreak
SmartPowerDownEnable
--------------------
Valid Range: 0-1
Default Value: 0 (disabled)
Allows PHY to turn off in lower power states. The user can turn off
this parameter in supported chipsets.
KumeranLockLoss
---------------
Valid Range: 0-1
Default Value: 1 (enabled)
This workaround skips resetting the PHY at shutdown for the initial
silicon releases of ICH8 systems.
Speed and Duplex Configuration
==============================
@ -385,40 +390,9 @@ If the link partner is forced to a specific speed and duplex, then this
parameter should not be used. Instead, use the Speed and Duplex parameters
previously mentioned to force the adapter to the same speed and duplex.
Additional Configurations
=========================
Configuring the Driver on Different Distributions
-------------------------------------------------
Configuring a network driver to load properly when the system is started
is distribution dependent. Typically, the configuration process involves
adding an alias line to /etc/modules.conf or /etc/modprobe.conf as well
as editing other system startup scripts and/or configuration files. Many
popular Linux distributions ship with tools to make these changes for you.
To learn the proper way to configure a network device for your system,
refer to your distribution documentation. If during this process you are
asked for the driver or module name, the name for the Linux Base Driver
for the Intel(R) PRO/1000 Family of Adapters is e1000.
As an example, if you install the e1000 driver for two PRO/1000 adapters
(eth0 and eth1) and set the speed and duplex to 10full and 100half, add
the following to modules.conf or or modprobe.conf:
alias eth0 e1000
alias eth1 e1000
options e1000 Speed=10,100 Duplex=2,1
Viewing Link Messages
---------------------
Link messages will not be displayed to the console if the distribution is
restricting system messages. In order to see network driver link messages
on your console, set dmesg to eight by entering the following:
dmesg -n 8
NOTE: This setting is not saved across reboots.
Jumbo Frames
------------
Jumbo Frames support is enabled by changing the MTU to a value larger than
@ -437,9 +411,11 @@ Additional Configurations
setting in a different location.
Notes:
- To enable Jumbo Frames, increase the MTU size on the interface beyond
1500.
Degradation in throughput performance may be observed in some Jumbo frames
environments. If this is observed, increasing the application's socket buffer
size and/or increasing the /proc/sys/net/ipv4/tcp_*mem entry values may help.
See the specific application manual and /usr/src/linux*/Documentation/
networking/ip-sysctl.txt for more details.
- The maximum MTU setting for Jumbo Frames is 16110. This value coincides
with the maximum Jumbo Frames size of 16128.
@ -447,40 +423,11 @@ Additional Configurations
- Using Jumbo Frames at 10 or 100 Mbps may result in poor performance or
loss of link.
- Some Intel gigabit adapters that support Jumbo Frames have a frame size
limit of 9238 bytes, with a corresponding MTU size limit of 9216 bytes.
The adapters with this limitation are based on the Intel(R) 82571EB,
82572EI, 82573L and 80003ES2LAN controller. These correspond to the
following product names:
Intel(R) PRO/1000 PT Server Adapter
Intel(R) PRO/1000 PT Desktop Adapter
Intel(R) PRO/1000 PT Network Connection
Intel(R) PRO/1000 PT Dual Port Server Adapter
Intel(R) PRO/1000 PT Dual Port Network Connection
Intel(R) PRO/1000 PF Server Adapter
Intel(R) PRO/1000 PF Network Connection
Intel(R) PRO/1000 PF Dual Port Server Adapter
Intel(R) PRO/1000 PB Server Connection
Intel(R) PRO/1000 PL Network Connection
Intel(R) PRO/1000 EB Network Connection with I/O Acceleration
Intel(R) PRO/1000 EB Backplane Connection with I/O Acceleration
Intel(R) PRO/1000 PT Quad Port Server Adapter
- Adapters based on the Intel(R) 82542 and 82573V/E controller do not
support Jumbo Frames. These correspond to the following product names:
Intel(R) PRO/1000 Gigabit Server Adapter
Intel(R) PRO/1000 PM Network Connection
- The following adapters do not support Jumbo Frames:
Intel(R) 82562V 10/100 Network Connection
Intel(R) 82566DM Gigabit Network Connection
Intel(R) 82566DC Gigabit Network Connection
Intel(R) 82566MM Gigabit Network Connection
Intel(R) 82566MC Gigabit Network Connection
Intel(R) 82562GT 10/100 Network Connection
Intel(R) 82562G 10/100 Network Connection
Ethtool
-------
The driver utilizes the ethtool interface for driver configuration and
@ -490,142 +437,14 @@ Additional Configurations
The latest release of ethtool can be found from
http://sourceforge.net/projects/gkernel.
NOTE: Ethtool 1.6 only supports a limited set of ethtool options. Support
for a more complete ethtool feature set can be enabled by upgrading
ethtool to ethtool-1.8.1.
Enabling Wake on LAN* (WoL)
---------------------------
WoL is configured through the Ethtool* utility. Ethtool is included with
all versions of Red Hat after Red Hat 7.2. For other Linux distributions,
download and install Ethtool from the following website:
http://sourceforge.net/projects/gkernel.
For instructions on enabling WoL with Ethtool, refer to the website listed
above.
WoL is configured through the Ethtool* utility.
WoL will be enabled on the system during the next shut down or reboot.
For this driver version, in order to enable WoL, the e1000 driver must be
loaded when shutting down or rebooting the system.
Wake On LAN is only supported on port A for the following devices:
Intel(R) PRO/1000 PT Dual Port Network Connection
Intel(R) PRO/1000 PT Dual Port Server Connection
Intel(R) PRO/1000 PT Dual Port Server Adapter
Intel(R) PRO/1000 PF Dual Port Server Adapter
Intel(R) PRO/1000 PT Quad Port Server Adapter
NAPI
----
NAPI (Rx polling mode) is enabled in the e1000 driver.
See www.cyberus.ca/~hadi/usenix-paper.tgz for more information on NAPI.
Known Issues
============
Dropped Receive Packets on Half-duplex 10/100 Networks
------------------------------------------------------
If you have an Intel PCI Express adapter running at 10mbps or 100mbps, half-
duplex, you may observe occasional dropped receive packets. There are no
workarounds for this problem in this network configuration. The network must
be updated to operate in full-duplex, and/or 1000mbps only.
Jumbo Frames System Requirement
-------------------------------
Memory allocation failures have been observed on Linux systems with 64 MB
of RAM or less that are running Jumbo Frames. If you are using Jumbo
Frames, your system may require more than the advertised minimum
requirement of 64 MB of system memory.
Performance Degradation with Jumbo Frames
-----------------------------------------
Degradation in throughput performance may be observed in some Jumbo frames
environments. If this is observed, increasing the application's socket
buffer size and/or increasing the /proc/sys/net/ipv4/tcp_*mem entry values
may help. See the specific application manual and
/usr/src/linux*/Documentation/
networking/ip-sysctl.txt for more details.
Jumbo Frames on Foundry BigIron 8000 switch
-------------------------------------------
There is a known issue using Jumbo frames when connected to a Foundry
BigIron 8000 switch. This is a 3rd party limitation. If you experience
loss of packets, lower the MTU size.
Allocating Rx Buffers when Using Jumbo Frames
---------------------------------------------
Allocating Rx buffers when using Jumbo Frames on 2.6.x kernels may fail if
the available memory is heavily fragmented. This issue may be seen with PCI-X
adapters or with packet split disabled. This can be reduced or eliminated
by changing the amount of available memory for receive buffer allocation, by
increasing /proc/sys/vm/min_free_kbytes.
Multiple Interfaces on Same Ethernet Broadcast Network
------------------------------------------------------
Due to the default ARP behavior on Linux, it is not possible to have
one system on two IP networks in the same Ethernet broadcast domain
(non-partitioned switch) behave as expected. All Ethernet interfaces
will respond to IP traffic for any IP address assigned to the system.
This results in unbalanced receive traffic.
If you have multiple interfaces in a server, either turn on ARP
filtering by entering:
echo 1 > /proc/sys/net/ipv4/conf/all/arp_filter
(this only works if your kernel's version is higher than 2.4.5),
NOTE: This setting is not saved across reboots. The configuration
change can be made permanent by adding the line:
net.ipv4.conf.all.arp_filter = 1
to the file /etc/sysctl.conf
or,
install the interfaces in separate broadcast domains (either in
different switches or in a switch partitioned to VLANs).
82541/82547 can't link or are slow to link with some link partners
-----------------------------------------------------------------
There is a known compatibility issue with 82541/82547 and some
low-end switches where the link will not be established, or will
be slow to establish. In particular, these switches are known to
be incompatible with 82541/82547:
Planex FXG-08TE
I-O Data ETG-SH8
To workaround this issue, the driver can be compiled with an override
of the PHY's master/slave setting. Forcing master or forcing slave
mode will improve time-to-link.
# make CFLAGS_EXTRA=-DE1000_MASTER_SLAVE=<n>
Where <n> is:
0 = Hardware default
1 = Master mode
2 = Slave mode
3 = Auto master/slave
Disable rx flow control with ethtool
------------------------------------
In order to disable receive flow control using ethtool, you must turn
off auto-negotiation on the same command line.
For example:
ethtool -A eth? autoneg off rx off
Unplugging network cable while ethtool -p is running
----------------------------------------------------
In kernel versions 2.5.50 and later (including 2.6 kernel), unplugging
the network cable while ethtool -p is running will cause the system to
become unresponsive to keyboard commands, except for control-alt-delete.
Restarting the system appears to be the only remedy.
Support
=======

302
Documentation/networking/e1000e.txt Normal file
View File

@ -0,0 +1,302 @@
Linux* Driver for Intel(R) Network Connection
===============================================================
Intel Gigabit Linux driver.
Copyright(c) 1999 - 2010 Intel Corporation.
Contents
========
- Identifying Your Adapter
- Command Line Parameters
- Additional Configurations
- Support
Identifying Your Adapter
========================
The e1000e driver supports all PCI Express Intel(R) Gigabit Network
Connections, except those that are 82575, 82576 and 82580-based*.
* NOTE: The Intel(R) PRO/1000 P Dual Port Server Adapter is supported by
the e1000 driver, not the e1000e driver due to the 82546 part being used
behind a PCI Express bridge.
For more information on how to identify your adapter, go to the Adapter &
Driver ID Guide at:
http://support.intel.com/support/go/network/adapter/idguide.htm
For the latest Intel network drivers for Linux, refer to the following
website. In the search field, enter your adapter name or type, or use the
networking link on the left to search for your adapter:
http://support.intel.com/support/go/network/adapter/home.htm
Command Line Parameters
=======================
The default value for each parameter is generally the recommended setting,
unless otherwise noted.
NOTES: For more information about the InterruptThrottleRate,
RxIntDelay, TxIntDelay, RxAbsIntDelay, and TxAbsIntDelay
parameters, see the application note at:
http://www.intel.com/design/network/applnots/ap450.htm
InterruptThrottleRate
---------------------
Valid Range: 0,1,3,4,100-100000 (0=off, 1=dynamic, 3=dynamic conservative,
4=simplified balancing)
Default Value: 3
The driver can limit the amount of interrupts per second that the adapter
will generate for incoming packets. It does this by writing a value to the
adapter that is based on the maximum amount of interrupts that the adapter
will generate per second.
Setting InterruptThrottleRate to a value greater or equal to 100
will program the adapter to send out a maximum of that many interrupts
per second, even if more packets have come in. This reduces interrupt
load on the system and can lower CPU utilization under heavy load,
but will increase latency as packets are not processed as quickly.
The driver has two adaptive modes (setting 1 or 3) in which
it dynamically adjusts the InterruptThrottleRate value based on the traffic
that it receives. After determining the type of incoming traffic in the last
timeframe, it will adjust the InterruptThrottleRate to an appropriate value
for that traffic.
The algorithm classifies the incoming traffic every interval into
classes. Once the class is determined, the InterruptThrottleRate value is
adjusted to suit that traffic type the best. There are three classes defined:
"Bulk traffic", for large amounts of packets of normal size; "Low latency",
for small amounts of traffic and/or a significant percentage of small
packets; and "Lowest latency", for almost completely small packets or
minimal traffic.
In dynamic conservative mode, the InterruptThrottleRate value is set to 4000
for traffic that falls in class "Bulk traffic". If traffic falls in the "Low
latency" or "Lowest latency" class, the InterruptThrottleRate is increased
stepwise to 20000. This default mode is suitable for most applications.
For situations where low latency is vital such as cluster or
grid computing, the algorithm can reduce latency even more when
InterruptThrottleRate is set to mode 1. In this mode, which operates
the same as mode 3, the InterruptThrottleRate will be increased stepwise to
70000 for traffic in class "Lowest latency".
In simplified mode the interrupt rate is based on the ratio of Tx and
Rx traffic. If the bytes per second rate is approximately equal the
interrupt rate will drop as low as 2000 interrupts per second. If the
traffic is mostly transmit or mostly receive, the interrupt rate could
be as high as 8000.
Setting InterruptThrottleRate to 0 turns off any interrupt moderation
and may improve small packet latency, but is generally not suitable
for bulk throughput traffic.
NOTE: InterruptThrottleRate takes precedence over the TxAbsIntDelay and
RxAbsIntDelay parameters. In other words, minimizing the receive
and/or transmit absolute delays does not force the controller to
generate more interrupts than what the Interrupt Throttle Rate
allows.
NOTE: When e1000e is loaded with default settings and multiple adapters
are in use simultaneously, the CPU utilization may increase non-
linearly. In order to limit the CPU utilization without impacting
the overall throughput, we recommend that you load the driver as
follows:
modprobe e1000e InterruptThrottleRate=3000,3000,3000
This sets the InterruptThrottleRate to 3000 interrupts/sec for
the first, second, and third instances of the driver. The range
of 2000 to 3000 interrupts per second works on a majority of
systems and is a good starting point, but the optimal value will
be platform-specific. If CPU utilization is not a concern, use
RX_POLLING (NAPI) and default driver settings.
RxIntDelay
----------
Valid Range: 0-65535 (0=off)
Default Value: 0
This value delays the generation of receive interrupts in units of 1.024
microseconds. Receive interrupt reduction can improve CPU efficiency if
properly tuned for specific network traffic. Increasing this value adds
extra latency to frame reception and can end up decreasing the throughput
of TCP traffic. If the system is reporting dropped receives, this value
may be set too high, causing the driver to run out of available receive
descriptors.
CAUTION: When setting RxIntDelay to a value other than 0, adapters may
hang (stop transmitting) under certain network conditions. If
this occurs a NETDEV WATCHDOG message is logged in the system
event log. In addition, the controller is automatically reset,
restoring the network connection. To eliminate the potential
for the hang ensure that RxIntDelay is set to 0.
RxAbsIntDelay
-------------
Valid Range: 0-65535 (0=off)
Default Value: 8
This value, in units of 1.024 microseconds, limits the delay in which a
receive interrupt is generated. Useful only if RxIntDelay is non-zero,
this value ensures that an interrupt is generated after the initial
packet is received within the set amount of time. Proper tuning,
along with RxIntDelay, may improve traffic throughput in specific network
conditions.
TxIntDelay
----------
Valid Range: 0-65535 (0=off)
Default Value: 8
This value delays the generation of transmit interrupts in units of
1.024 microseconds. Transmit interrupt reduction can improve CPU
efficiency if properly tuned for specific network traffic. If the
system is reporting dropped transmits, this value may be set too high
causing the driver to run out of available transmit descriptors.
TxAbsIntDelay
-------------
Valid Range: 0-65535 (0=off)
Default Value: 32
This value, in units of 1.024 microseconds, limits the delay in which a
transmit interrupt is generated. Useful only if TxIntDelay is non-zero,
this value ensures that an interrupt is generated after the initial
packet is sent on the wire within the set amount of time. Proper tuning,
along with TxIntDelay, may improve traffic throughput in specific
network conditions.
Copybreak
---------
Valid Range: 0-xxxxxxx (0=off)
Default Value: 256
Driver copies all packets below or equaling this size to a fresh Rx
buffer before handing it up the stack.
This parameter is different than other parameters, in that it is a
single (not 1,1,1 etc.) parameter applied to all driver instances and
it is also available during runtime at
/sys/module/e1000e/parameters/copybreak
SmartPowerDownEnable
--------------------
Valid Range: 0-1
Default Value: 0 (disabled)
Allows PHY to turn off in lower power states. The user can set this parameter
in supported chipsets.
KumeranLockLoss
---------------
Valid Range: 0-1
Default Value: 1 (enabled)
This workaround skips resetting the PHY at shutdown for the initial
silicon releases of ICH8 systems.
IntMode
-------
Valid Range: 0-2 (0=legacy, 1=MSI, 2=MSI-X)
Default Value: 2
Allows changing the interrupt mode at module load time, without requiring a
recompile. If the driver load fails to enable a specific interrupt mode, the
driver will try other interrupt modes, from least to most compatible. The
interrupt order is MSI-X, MSI, Legacy. If specifying MSI (IntMode=1)
interrupts, only MSI and Legacy will be attempted.
CrcStripping
------------
Valid Range: 0-1
Default Value: 1 (enabled)
Strip the CRC from received packets before sending up the network stack. If
you have a machine with a BMC enabled but cannot receive IPMI traffic after
loading or enabling the driver, try disabling this feature.
WriteProtectNVM
---------------
Valid Range: 0-1
Default Value: 1 (enabled)
Set the hardware to ignore all write/erase cycles to the GbE region in the
ICHx NVM (non-volatile memory). This feature can be disabled by the
WriteProtectNVM module parameter (enabled by default) only after a hardware
reset, but the machine must be power cycled before trying to enable writes.
Note: the kernel boot option iomem=relaxed may need to be set if the kernel
config option CONFIG_STRICT_DEVMEM=y, if the root user wants to write the
NVM from user space via ethtool.
Additional Configurations
=========================
Jumbo Frames
------------
Jumbo Frames support is enabled by changing the MTU to a value larger than
the default of 1500. Use the ifconfig command to increase the MTU size.
For example:
ifconfig eth<x> mtu 9000 up
This setting is not saved across reboots.
Notes:
- The maximum MTU setting for Jumbo Frames is 9216. This value coincides
with the maximum Jumbo Frames size of 9234 bytes.
- Using Jumbo Frames at 10 or 100 Mbps is not supported and may result in
poor performance or loss of link.
- Some adapters limit Jumbo Frames sized packets to a maximum of
4096 bytes and some adapters do not support Jumbo Frames.
Ethtool
-------
The driver utilizes the ethtool interface for driver configuration and
diagnostics, as well as displaying statistical information. We
strongly recommend downloading the latest version of Ethtool at:
http://sourceforge.net/projects/gkernel.
Speed and Duplex
----------------
Speed and Duplex are configured through the Ethtool* utility. For
instructions, refer to the Ethtool man page.
Enabling Wake on LAN* (WoL)
---------------------------
WoL is configured through the Ethtool* utility. For instructions on
enabling WoL with Ethtool, refer to the Ethtool man page.
WoL will be enabled on the system during the next shut down or reboot.
For this driver version, in order to enable WoL, the e1000e driver must be
loaded when shutting down or rebooting the system.
In most cases Wake On LAN is only supported on port A for multiple port
adapters. To verify if a port supports Wake on LAN run ethtool eth<X>.
Support
=======
For general information, go to the Intel support website at:
www.intel.com/support/
or the Intel Wired Networking project hosted by Sourceforge at:
http://sourceforge.net/projects/e1000
If an issue is identified with the released source code on the supported
kernel with a supported adapter, email the specific information related
to the issue to e1000-devel@lists.sf.net

40
Documentation/networking/ixgbevf.txt Executable file → Normal file
View File

@ -1,19 +1,16 @@
Linux* Base Driver for Intel(R) Network Connection
==================================================
November 24, 2009
Intel Gigabit Linux driver.
Copyright(c) 1999 - 2010 Intel Corporation.
Contents
========
- In This Release
- Identifying Your Adapter
- Known Issues/Troubleshooting
- Support
In This Release
===============
This file describes the ixgbevf Linux* Base Driver for Intel Network
Connection.
@ -33,7 +30,7 @@ Identifying Your Adapter
For more information on how to identify your adapter, go to the Adapter &
Driver ID Guide at:
http://support.intel.com/support/network/sb/CS-008441.htm
http://support.intel.com/support/go/network/adapter/idguide.htm
Known Issues/Troubleshooting
============================
@ -57,34 +54,3 @@ or the Intel Wired Networking project hosted by Sourceforge at:
If an issue is identified with the released source code on the supported
kernel with a supported adapter, email the specific information related
to the issue to e1000-devel@lists.sf.net
License
=======
Intel 10 Gigabit Linux driver.
Copyright(c) 1999 - 2009 Intel Corporation.
This program is free software; you can redistribute it and/or modify it
under the terms and conditions of the GNU General Public License,
version 2, as published by the Free Software Foundation.
This program is distributed in the hope it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc.,
51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
The full GNU General Public License is included in this distribution in
the file called "COPYING".
Trademarks
==========
Intel, Itanium, and Pentium are trademarks or registered trademarks of
Intel Corporation or its subsidiaries in the United States and other
countries.
* Other names and brands may be claimed as the property of others.

2
Documentation/vm/page-types.c
View File

@ -478,7 +478,7 @@ static void prepare_hwpoison_fd(void)
}
if (opt_unpoison && !hwpoison_forget_fd) {
sprintf(buf, "%s/renew-pfn", hwpoison_debug_fs);
sprintf(buf, "%s/unpoison-pfn", hwpoison_debug_fs);
hwpoison_forget_fd = checked_open(buf, O_WRONLY);
}
}

64
MAINTAINERS
View File

@ -962,6 +962,23 @@ W: http://www.fluff.org/ben/linux/
S: Maintained
F: arch/arm/mach-s3c6410/
ARM/S5P ARM ARCHITECTURES
M: Kukjin Kim <kgene.kim@samsung.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/mach-s5p*/
ARM/SAMSUNG S5P SERIES FIMC SUPPORT
M: Kyungmin Park <kyungmin.park@samsung.com>
M: Sylwester Nawrocki <s.nawrocki@samsung.com>
L: linux-arm-kernel@lists.infradead.org
L: linux-media@vger.kernel.org
S: Maintained
F: arch/arm/plat-s5p/dev-fimc*
F: arch/arm/plat-samsung/include/plat/*fimc*
F: drivers/media/video/s5p-fimc/
ARM/SHMOBILE ARM ARCHITECTURE
M: Paul Mundt <lethal@linux-sh.org>
M: Magnus Damm <magnus.damm@gmail.com>
@ -973,11 +990,23 @@ S: Supported
F: arch/arm/mach-shmobile/
F: drivers/sh/
ARM/TELECHIPS ARM ARCHITECTURE
M: "Hans J. Koch" <hjk@linutronix.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/plat-tcc/
F: arch/arm/mach-tcc8k/
ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/TETON BGA MACHINE SUPPORT
M: Mark F. Brown <mark.brown314@gmail.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/THECUS N2100 MACHINE SUPPORT
M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
@ -2528,7 +2557,7 @@ S: Supported
F: drivers/scsi/gdt*
GENERIC GPIO I2C DRIVER
M: Haavard Skinnemoen <hskinnemoen@atmel.com>
M: Haavard Skinnemoen <hskinnemoen@gmail.com>
S: Supported
F: drivers/i2c/busses/i2c-gpio.c
F: include/linux/i2c-gpio.h
@ -3056,16 +3085,27 @@ L: netdev@vger.kernel.org
S: Maintained
F: drivers/net/ixp2000/
INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/igbvf/ixgb/ixgbe)
INTEL ETHERNET DRIVERS (e100/e1000/e1000e/igb/igbvf/ixgb/ixgbe/ixgbevf)
M: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
M: Jesse Brandeburg <jesse.brandeburg@intel.com>
M: Bruce Allan <bruce.w.allan@intel.com>
M: Alex Duyck <alexander.h.duyck@intel.com>
M: Carolyn Wyborny <carolyn.wyborny@intel.com>
M: Don Skidmore <donald.c.skidmore@intel.com>
M: Greg Rose <gregory.v.rose@intel.com>
M: PJ Waskiewicz <peter.p.waskiewicz.jr@intel.com>
M: Alex Duyck <alexander.h.duyck@intel.com>
M: John Ronciak <john.ronciak@intel.com>
L: e1000-devel@lists.sourceforge.net
W: http://e1000.sourceforge.net/
S: Supported
F: Documentation/networking/e100.txt
F: Documentation/networking/e1000.txt
F: Documentation/networking/e1000e.txt
F: Documentation/networking/igb.txt
F: Documentation/networking/igbvf.txt
F: Documentation/networking/ixgb.txt
F: Documentation/networking/ixgbe.txt
F: Documentation/networking/ixgbevf.txt
F: drivers/net/e100.c
F: drivers/net/e1000/
F: drivers/net/e1000e/
@ -3073,6 +3113,7 @@ F: drivers/net/igb/
F: drivers/net/igbvf/
F: drivers/net/ixgb/
F: drivers/net/ixgbe/
F: drivers/net/ixgbevf/
INTEL PRO/WIRELESS 2100 NETWORK CONNECTION SUPPORT
L: linux-wireless@vger.kernel.org
@ -3781,9 +3822,8 @@ W: http://www.syskonnect.com
S: Supported
MATROX FRAMEBUFFER DRIVER
M: Petr Vandrovec <vandrove@vc.cvut.cz>
L: linux-fbdev@vger.kernel.org
S: Maintained
S: Orphan
F: drivers/video/matrox/matroxfb_*
F: include/linux/matroxfb.h
@ -3970,8 +4010,8 @@ S: Maintained
F: drivers/net/natsemi.c
NCP FILESYSTEM
M: Petr Vandrovec <vandrove@vc.cvut.cz>
S: Maintained
M: Petr Vandrovec <petr@vandrovec.name>
S: Odd Fixes
F: fs/ncpfs/
NCR DUAL 700 SCSI DRIVER (MICROCHANNEL)
@ -5002,6 +5042,12 @@ F: drivers/media/common/saa7146*
F: drivers/media/video/*7146*
F: include/media/*7146*
SAMSUNG AUDIO (ASoC) DRIVERS
M: Jassi Brar <jassi.brar@samsung.com>
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
S: Supported
F: sound/soc/s3c24xx
TLG2300 VIDEO4LINUX-2 DRIVER
M: Huang Shijie <shijie8@gmail.com>
M: Kang Yong <kangyong@telegent.com>
@ -6444,8 +6490,10 @@ F: include/linux/wm97xx.h
WOLFSON MICROELECTRONICS DRIVERS
M: Mark Brown <broonie@opensource.wolfsonmicro.com>
M: Ian Lartey <ian@opensource.wolfsonmicro.com>
M: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
T: git git://opensource.wolfsonmicro.com/linux-2.6-asoc
T: git git://opensource.wolfsonmicro.com/linux-2.6-audioplus
W: http://opensource.wolfsonmicro.com/node/8
W: http://opensource.wolfsonmicro.com/content/linux-drivers-wolfson-devices
S: Supported
F: Documentation/hwmon/wm83??
F: drivers/leds/leds-wm83*.c

4
Makefile
View File

@ -1,8 +1,8 @@
VERSION = 2
PATCHLEVEL = 6
SUBLEVEL = 36
EXTRAVERSION = -rc6
NAME = Sheep on Meth
EXTRAVERSION = -rc8
NAME = Flesh-Eating Bats with Fangs
# *DOCUMENTATION*
# To see a list of typical targets execute "make help"

2
arch/alpha/kernel/signal.c
View File

@ -48,7 +48,7 @@ SYSCALL_DEFINE2(osf_sigprocmask, int, how, unsigned long, newmask)
sigset_t mask;
unsigned long res;
siginitset(&mask, newmask & ~_BLOCKABLE);
siginitset(&mask, newmask & _BLOCKABLE);
res = sigprocmask(how, &mask, &oldmask);
if (!res) {
force_successful_syscall_return();

52
arch/arm/Kconfig
View File

@ -516,6 +516,7 @@ config ARCH_MMP
select GENERIC_CLOCKEVENTS
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
help
Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
@ -593,6 +594,7 @@ config ARCH_PXA
select GENERIC_CLOCKEVENTS
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
@ -684,8 +686,8 @@ config ARCH_S3C64XX
help
Samsung S3C64XX series based systems
config ARCH_S5P6440
bool "Samsung S5P6440"
config ARCH_S5P64X0
bool "Samsung S5P6440 S5P6450"
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
@ -694,7 +696,8 @@ config ARCH_S5P6440
select HAVE_S3C2410_I2C
select HAVE_S3C_RTC
help
Samsung S5P6440 CPU based systems
Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
SMDK6450.
config ARCH_S5P6442
bool "Samsung S5P6442"
@ -753,6 +756,15 @@ config ARCH_SHARK
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).
config ARCH_TCC_926
bool "Telechips TCC ARM926-based systems"
select CPU_ARM926T
select HAVE_CLK
select COMMON_CLKDEV
select GENERIC_CLOCKEVENTS
help
Support for Telechips TCC ARM926-based systems.
config ARCH_LH7A40X
bool "Sharp LH7A40X"
select CPU_ARM922T
@ -921,6 +933,8 @@ source "arch/arm/plat-s5p/Kconfig"
source "arch/arm/plat-spear/Kconfig"
source "arch/arm/plat-tcc/Kconfig"
if ARCH_S3C2410
source "arch/arm/mach-s3c2400/Kconfig"
source "arch/arm/mach-s3c2410/Kconfig"
@ -934,7 +948,7 @@ if ARCH_S3C64XX
source "arch/arm/mach-s3c64xx/Kconfig"
endif
source "arch/arm/mach-s5p6440/Kconfig"
source "arch/arm/mach-s5p64x0/Kconfig"
source "arch/arm/mach-s5p6442/Kconfig"
@ -1107,6 +1121,20 @@ config ARM_ERRATA_720789
invalidated are not, resulting in an incoherency in the system page
tables. The workaround changes the TLB flushing routines to invalidate
entries regardless of the ASID.
config ARM_ERRATA_743622
bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
depends on CPU_V7
help
This option enables the workaround for the 743622 Cortex-A9
(r2p0..r2p2) erratum. Under very rare conditions, a faulty
optimisation in the Cortex-A9 Store Buffer may lead to data
corruption. This workaround sets a specific bit in the diagnostic
register of the Cortex-A9 which disables the Store Buffer
optimisation, preventing the defect from occurring. This has no
visible impact on the overall performance or power consumption of the
processor.
endmenu
source "arch/arm/common/Kconfig"
@ -1273,7 +1301,7 @@ source kernel/Kconfig.preempt
config HZ
int
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \
default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
default AT91_TIMER_HZ if ARCH_AT91
@ -1479,6 +1507,20 @@ config UACCESS_WITH_MEMCPY
However, if the CPU data cache is using a write-allocate mode,
this option is unlikely to provide any performance gain.
config SECCOMP
bool
prompt "Enable seccomp to safely compute untrusted bytecode"
---help---
This kernel feature is useful for number crunching applications
that may need to compute untrusted bytecode during their
execution. By using pipes or other transports made available to
the process as file descriptors supporting the read/write
syscalls, it's possible to isolate those applications in
their own address space using seccomp. Once seccomp is
enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
and the task is only allowed to execute a few safe syscalls
defined by each seccomp mode.
config CC_STACKPROTECTOR
bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
help

14
arch/arm/Kconfig.debug
View File

@ -2,6 +2,20 @@ menu "Kernel hacking"
source "lib/Kconfig.debug"
config STRICT_DEVMEM
bool "Filter access to /dev/mem"
depends on MMU
---help---
If this option is disabled, you allow userspace (root) access to all
of memory, including kernel and userspace memory. Accidental
access to this is obviously disastrous, but specific access can
be used by people debugging the kernel.
If this option is switched on, the /dev/mem file only allows
userspace access to memory mapped peripherals.
If in doubt, say Y.
# RMK wants arm kernels compiled with frame pointers or stack unwinding.
# If you know what you are doing and are willing to live without stack
# traces, you can get a slightly smaller kernel by setting this option to

11
arch/arm/Makefile
View File

@ -173,7 +173,7 @@ machine-$(CONFIG_ARCH_RPC) := rpc
machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P6440) := s5p6440
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5P6442) := s5p6442
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210
@ -183,6 +183,7 @@ machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
machine-$(CONFIG_ARCH_STMP378X) := stmp378x
machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
machine-$(CONFIG_ARCH_TCC8K) := tcc8k
machine-$(CONFIG_ARCH_TEGRA) := tegra
machine-$(CONFIG_ARCH_U300) := u300
machine-$(CONFIG_ARCH_U8500) := ux500
@ -202,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC) := mxc
plat-$(CONFIG_ARCH_OMAP) := omap
plat-$(CONFIG_ARCH_S3C64XX) := samsung
plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
plat-$(CONFIG_ARCH_TCC_926) := tcc
plat-$(CONFIG_PLAT_IOP) := iop
plat-$(CONFIG_PLAT_NOMADIK) := nomadik
plat-$(CONFIG_PLAT_ORION) := orion
@ -245,13 +247,14 @@ ifeq ($(FASTFPE),$(wildcard $(FASTFPE)))
FASTFPE_OBJ :=$(FASTFPE)/
endif
# If we have a machine-specific directory, then include it in the build.
core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
core-y += $(machdirs) $(platdirs)
core-$(CONFIG_FPE_NWFPE) += arch/arm/nwfpe/
core-$(CONFIG_FPE_FASTFPE) += $(FASTFPE_OBJ)
core-$(CONFIG_VFP) += arch/arm/vfp/
# If we have a machine-specific directory, then include it in the build.
core-y += arch/arm/kernel/ arch/arm/mm/ arch/arm/common/
core-y += $(machdirs) $(platdirs)
drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
libs-y := arch/arm/lib/ $(libs-y)

14
arch/arm/common/gic.c
View File

@ -67,25 +67,11 @@ static inline unsigned int gic_irq(unsigned int irq)
/*
* Routines to acknowledge, disable and enable interrupts
*
* Linux assumes that when we're done with an interrupt we need to
* unmask it, in the same way we need to unmask an interrupt when
* we first enable it.
*
* The GIC has a separate notion of "end of interrupt" to re-enable
* an interrupt after handling, in order to support hardware
* prioritisation.
*
* We can make the GIC behave in the way that Linux expects by making
* our "acknowledge" routine disable the interrupt, then mark it as
* complete.
*/
static void gic_ack_irq(unsigned int irq)
{
u32 mask = 1 << (irq % 32);
spin_lock(&irq_controller_lock);
writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
spin_unlock(&irq_controller_lock);
}

1
arch/arm/configs/at91sam9g20ek_defconfig
View File

@ -13,6 +13,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_ARCH_AT91=y
CONFIG_ARCH_AT91SAM9G20=y
CONFIG_MACH_AT91SAM9G20EK=y
CONFIG_MACH_AT91SAM9G20EK_2MMC=y
CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
# CONFIG_ARM_THUMB is not set
CONFIG_AEABI=y

1
arch/arm/configs/kirkwood_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_MACH_MV88F6281GTW_GE=y
CONFIG_MACH_SHEEVAPLUG=y
CONFIG_MACH_ESATA_SHEEVAPLUG=y
CONFIG_MACH_GURUPLUG=y
CONFIG_MACH_DOCKSTAR=y
CONFIG_MACH_TS219=y
CONFIG_MACH_TS41X=y
CONFIG_MACH_OPENRD_BASE=y

15
arch/arm/configs/mx27_defconfig
View File

@ -21,8 +21,14 @@ CONFIG_ARCH_MX2=y
CONFIG_MACH_MX27=y
CONFIG_MACH_MX27ADS=y
CONFIG_MACH_PCM038=y
CONFIG_MACH_CPUIMX27=y
CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2=y
CONFIG_MACH_EUKREA_CPUIMX27_USEUART4=y
CONFIG_MACH_MX27_3DS=y
CONFIG_MACH_IMX27_VISSTRIM_M10=y
CONFIG_MACH_IMX27LITE=y
CONFIG_MACH_PCA100=y
CONFIG_MACH_MXT_TD60=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
@ -76,7 +82,9 @@ CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_TOUCHSCREEN_ADS7846=m
# CONFIG_SERIO is not set
CONFIG_SERIAL_8250=m
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
@ -85,19 +93,20 @@ CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_IMX=y
CONFIG_SPI=y
CONFIG_SPI_BITBANG=y
CONFIG_SPI_IMX=y
CONFIG_W1=y
CONFIG_W1_MASTER_MXC=y
CONFIG_W1_SLAVE_THERM=y
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_FB_IMX=y
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FONTS=y
CONFIG_FONT_8x8=y
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
CONFIG_USB=m
# CONFIG_USB_DEVICE_CLASS is not set
CONFIG_USB_ULPI=y
CONFIG_MMC=y
CONFIG_MMC_MXC=y
CONFIG_RTC_CLASS=y

44
arch/arm/configs/mx31pdk_defconfig
View File

@ -1,44 +0,0 @@
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
# CONFIG_COMPAT_BRK is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MXC=y
# CONFIG_MACH_MX31ADS is not set
CONFIG_MACH_MX31_3DS=y
CONFIG_AEABI=y
CONFIG_NET=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_NET_KEY=y
CONFIG_INET=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_LRO is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
# CONFIG_FIRMWARE_IN_KERNEL is not set
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_NETDEVICES=y
CONFIG_NET_ETHERNET=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_SERIO is not set
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_DNOTIFY is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRC32 is not set

2
arch/arm/configs/mx3_defconfig
View File

@ -24,6 +24,7 @@ CONFIG_MACH_PCM043=y
CONFIG_MACH_ARMADILLO5X0=y
CONFIG_MACH_MX35_3DS=y
CONFIG_MACH_KZM_ARM11_01=y
CONFIG_MACH_EUKREA_CPUIMX35=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_MXC_PWM=y
CONFIG_NO_HZ=y
@ -108,7 +109,6 @@ CONFIG_MMC=y
CONFIG_MMC_MXC=y
CONFIG_DMADEVICES=y
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_TMPFS=y
CONFIG_JFFS2_FS=y
CONFIG_UBIFS_FS=y

9
arch/arm/configs/mx51_defconfig
View File

@ -15,6 +15,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
CONFIG_ARCH_MXC=y
CONFIG_ARCH_MX5=y
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT_VOLUNTARY=y
@ -69,7 +71,6 @@ CONFIG_REALTEK_PHY=y
CONFIG_NATIONAL_PHY=y
CONFIG_STE10XP=y
CONFIG_LSI_ET1011C_PHY=y
CONFIG_FIXED_PHY=y
CONFIG_MDIO_BITBANG=y
CONFIG_MDIO_GPIO=y
CONFIG_NET_ETHERNET=y
@ -100,7 +101,6 @@ CONFIG_I2C_ALGOPCF=m
CONFIG_I2C_ALGOPCA=m
CONFIG_GPIO_SYSFS=y
# CONFIG_HWMON is not set
# CONFIG_VGA_CONSOLE is not set
# CONFIG_HID_SUPPORT is not set
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
@ -117,13 +117,11 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
CONFIG_EXT2_FS_SECURITY=y
CONFIG_EXT3_FS=y
CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
CONFIG_EXT3_FS_POSIX_ACL=y
CONFIG_EXT3_FS_SECURITY=y
CONFIG_EXT4_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_EXT4_FS_SECURITY=y
CONFIG_INOTIFY=y
CONFIG_QUOTA=y
CONFIG_QUOTA_NETLINK_INTERFACE=y
# CONFIG_PRINT_QUOTA_WARNING is not set
@ -136,6 +134,7 @@ CONFIG_ZISOFS=y
CONFIG_UDF_FS=m
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=y
CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=m
CONFIG_NFS_FS=y
CONFIG_NFS_V3=y
@ -151,7 +150,6 @@ CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
@ -159,7 +157,6 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_ARM_UNWIND is not set
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
CONFIG_KEYS=y
CONFIG_SECURITYFS=y
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y

3
arch/arm/configs/s5p6440_defconfig → arch/arm/configs/s5p64x0_defconfig
View File

@ -5,10 +5,11 @@ CONFIG_KALLSYMS_ALL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_S5P6440=y
CONFIG_ARCH_S5P64X0=y
CONFIG_S3C_BOOT_ERROR_RESET=y
CONFIG_S3C_LOWLEVEL_UART_PORT=1
CONFIG_MACH_SMDK6440=y
CONFIG_MACH_SMDK6450=y
CONFIG_CPU_32v6K=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"

4
arch/arm/include/asm/elf.h
View File

@ -127,4 +127,8 @@ struct mm_struct;
extern unsigned long arch_randomize_brk(struct mm_struct *mm);
#define arch_randomize_brk arch_randomize_brk
extern int vectors_user_mapping(void);
#define arch_setup_additional_pages(bprm, uses_interp) vectors_user_mapping()
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
#endif

1
arch/arm/include/asm/io.h
View File

@ -294,6 +294,7 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(unsigned long addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
extern int devmem_is_allowed(unsigned long pfn);
#endif
/*

29
arch/arm/include/asm/mmu_context.h
View File

@ -18,7 +18,6 @@
#include <asm/cacheflush.h>
#include <asm/cachetype.h>
#include <asm/proc-fns.h>
#include <asm-generic/mm_hooks.h>
void __check_kvm_seq(struct mm_struct *mm);
@ -134,4 +133,32 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
#define deactivate_mm(tsk,mm) do { } while (0)
#define activate_mm(prev,next) switch_mm(prev, next, NULL)
/*
* We are inserting a "fake" vma for the user-accessible vector page so
* gdb and friends can get to it through ptrace and /proc/<pid>/mem.
* But we also want to remove it before the generic code gets to see it
* during process exit or the unmapping of it would cause total havoc.
* (the macro is used as remove_vma() is static to mm/mmap.c)
*/
#define arch_exit_mmap(mm) \
do { \
struct vm_area_struct *high_vma = find_vma(mm, 0xffff0000); \
if (high_vma) { \
BUG_ON(high_vma->vm_next); /* it should be last */ \
if (high_vma->vm_prev) \
high_vma->vm_prev->vm_next = NULL; \
else \
mm->mmap = NULL; \
rb_erase(&high_vma->vm_rb, &mm->mm_rb); \
mm->mmap_cache = NULL; \
mm->map_count--; \
remove_vma(high_vma); \
} \
} while (0)
static inline void arch_dup_mmap(struct mm_struct *oldmm,
struct mm_struct *mm)
{
}
#endif

11
arch/arm/include/asm/seccomp.h Normal file
View File

@ -0,0 +1,11 @@
#ifndef _ASM_ARM_SECCOMP_H
#define _ASM_ARM_SECCOMP_H
#include <linux/unistd.h>
#define __NR_seccomp_read __NR_read
#define __NR_seccomp_write __NR_write
#define __NR_seccomp_exit __NR_exit
#define __NR_seccomp_sigreturn __NR_rt_sigreturn
#endif /* _ASM_ARM_SECCOMP_H */

2
arch/arm/include/asm/thread_info.h
View File

@ -144,6 +144,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
#define TIF_FREEZE 19
#define TIF_RESTORE_SIGMASK 20
#define TIF_SECCOMP 21
#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
@ -153,6 +154,7 @@ extern void vfp_flush_hwstate(struct thread_info *);
#define _TIF_USING_IWMMXT (1 << TIF_USING_IWMMXT)
#define _TIF_FREEZE (1 << TIF_FREEZE)
#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
#define _TIF_SECCOMP (1 << TIF_SECCOMP)
/*
* Change these and you break ASM code in entry-common.S

15
arch/arm/kernel/entry-common.S
View File

@ -334,7 +334,6 @@ ENTRY(vector_swi)
get_thread_info tsk
adr tbl, sys_call_table @ load syscall table pointer
ldr ip, [tsk, #TI_FLAGS] @ check for syscall tracing
#if defined(CONFIG_OABI_COMPAT)
/*
@ -351,8 +350,20 @@ ENTRY(vector_swi)
eor scno, scno, #__NR_SYSCALL_BASE @ check OS number
#endif
ldr r10, [tsk, #TI_FLAGS] @ check for syscall tracing
stmdb sp!, {r4, r5} @ push fifth and sixth args
tst ip, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
#ifdef CONFIG_SECCOMP
tst r10, #_TIF_SECCOMP
beq 1f
mov r0, scno
bl __secure_computing
add r0, sp, #S_R0 + S_OFF @ pointer to regs
ldmia r0, {r0 - r3} @ have to reload r0 - r3
1:
#endif
tst r10, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?
bne __sys_trace
cmp scno, #NR_syscalls @ check upper syscall limit

7
arch/arm/kernel/kprobes-decode.c
View File

@ -1162,11 +1162,12 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
{
/*
* MSR : cccc 0011 0x10 xxxx xxxx xxxx xxxx xxxx
* Undef : cccc 0011 0x00 xxxx xxxx xxxx xxxx xxxx
* Undef : cccc 0011 0100 xxxx xxxx xxxx xxxx xxxx
* ALU op with S bit and Rd == 15 :
* cccc 001x xxx1 xxxx 1111 xxxx xxxx xxxx
*/
if ((insn & 0x0f900000) == 0x03200000 || /* MSR & Undef */
if ((insn & 0x0fb00000) == 0x03200000 || /* MSR */
(insn & 0x0ff00000) == 0x03400000 || /* Undef */
(insn & 0x0e10f000) == 0x0210f000) /* ALU s-bit, R15 */
return INSN_REJECTED;
@ -1177,7 +1178,7 @@ space_cccc_001x(kprobe_opcode_t insn, struct arch_specific_insn *asi)
* *S (bit 20) updates condition codes
* ADC/SBC/RSC reads the C flag
*/
insn &= 0xfff00fff; /* Rn = r0, Rd = r0 */
insn &= 0xffff0fff; /* Rd = r0 */
asi->insn[0] = insn;
asi->insn_handler = (insn & (1 << 20)) ? /* S-bit */
emulate_alu_imm_rwflags : emulate_alu_imm_rflags;

21
arch/arm/kernel/process.c
View File

@ -482,3 +482,24 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
unsigned long range_end = mm->brk + 0x02000000;
return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
}
/*
* The vectors page is always readable from user space for the
* atomic helpers and the signal restart code. Let's declare a mapping
* for it so it is visible through ptrace and /proc/<pid>/mem.
*/
int vectors_user_mapping(void)
{
struct mm_struct *mm = current->mm;
return install_special_mapping(mm, 0xffff0000, PAGE_SIZE,
VM_READ | VM_EXEC |
VM_MAYREAD | VM_MAYEXEC |
VM_ALWAYSDUMP | VM_RESERVED,
NULL);
}
const char *arch_vma_name(struct vm_area_struct *vma)
{
return (vma->vm_start == 0xffff0000) ? "[vectors]" : NULL;
}

2
arch/arm/mach-aaec2000/include/mach/vmalloc.h
View File

@ -11,6 +11,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#define VMALLOC_END 0xd0000000
#endif /* __ASM_ARCH_VMALLOC_H */

9
arch/arm/mach-at91/Kconfig
View File

@ -33,6 +33,7 @@ config ARCH_AT91SAM9260
select HAVE_AT91_USART3
select HAVE_AT91_USART4
select HAVE_AT91_USART5
select HAVE_NET_MACB
config ARCH_AT91SAM9261
bool "AT91SAM9261"
@ -51,6 +52,7 @@ config ARCH_AT91SAM9263
select CPU_ARM926T
select GENERIC_CLOCKEVENTS
select HAVE_FB_ATMEL
select HAVE_NET_MACB
config ARCH_AT91SAM9RL
bool "AT91SAM9RL"
@ -66,6 +68,7 @@ config ARCH_AT91SAM9G20
select HAVE_AT91_USART3
select HAVE_AT91_USART4
select HAVE_AT91_USART5
select HAVE_NET_MACB
config ARCH_AT91SAM9G45
bool "AT91SAM9G45"
@ -73,6 +76,7 @@ config ARCH_AT91SAM9G45
select GENERIC_CLOCKEVENTS
select HAVE_AT91_USART3
select HAVE_FB_ATMEL
select HAVE_NET_MACB
config ARCH_AT91CAP9
bool "AT91CAP9"
@ -344,6 +348,7 @@ config MACH_AT91SAM9G20EK
that embeds only one SD/MMC slot.
config MACH_AT91SAM9G20EK_2MMC
depends on MACH_AT91SAM9G20EK
bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
select HAVE_NAND_ATMEL_BUSWIDTH_16
help
@ -389,8 +394,8 @@ if ARCH_AT91SAM9G45
comment "AT91SAM9G45 Board Type"
config MACH_AT91SAM9G45EKES
bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
config MACH_AT91SAM9M10G45EK
bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
select HAVE_NAND_ATMEL_BUSWIDTH_16
help
Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.

3
arch/arm/mach-at91/Makefile
View File

@ -62,7 +62,6 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
# AT91SAM9G20 board-specific support
obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
obj-$(CONFIG_MACH_AT91SAM9G20EK_2MMC) += board-sam9g20ek-2slot-mmc.o
obj-$(CONFIG_MACH_CPU9G20) += board-cpu9krea.o
obj-$(CONFIG_MACH_STAMP9G20) += board-stamp9g20.o
obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
@ -71,7 +70,7 @@ obj-$(CONFIG_MACH_PORTUXG20) += board-stamp9g20.o
obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
# AT91SAM9G45 board-specific support
obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
# AT91CAP9 board-specific support
obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o

2
arch/arm/mach-at91/board-at572d940hf_ek.c
View File

@ -216,7 +216,7 @@ static struct atmel_nand_data __initdata eb_nand_data = {
/* .rdy_pin = AT91_PIN_PC16, */
.enable_pin = AT91_PIN_PA15,
.partition_info = nand_partitions,
#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
.bus_width_16 = 0,

329
arch/arm/mach-at91/board-sam9g20ek-2slot-mmc.c
View File

@ -1,329 +0,0 @@
/*
* Copyright (C) 2005 SAN People
* Copyright (C) 2008 Atmel
* Copyright (C) 2009 Rob Emanuele
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/at73c213.h>
#include <linux/clk.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/consumer.h>
#include <mach/hardware.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <mach/board.h>
#include <mach/gpio.h>
#include <mach/at91sam9_smc.h>
#include "sam9_smc.h"
#include "generic.h"
static void __init ek_map_io(void)
{
/* Initialize processor: 18.432 MHz crystal */
at91sam9260_initialize(18432000);
/* DGBU on ttyS0. (Rx & Tx only) */
at91_register_uart(0, 0, 0);
/* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
| ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
| ATMEL_UART_RI);
/* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
/* set serial console to ttyS0 (ie, DBGU) */
at91_set_serial_console(0);
}
static void __init ek_init_irq(void)
{
at91sam9260_init_interrupts(NULL);
}
/*
* USB Host port
*/
static struct at91_usbh_data __initdata ek_usbh_data = {
.ports = 2,
};
/*
* USB Device port
*/
static struct at91_udc_data __initdata ek_udc_data = {
.vbus_pin = AT91_PIN_PC5,
.pullup_pin = 0, /* pull-up driven by UDC */
};
/*
* SPI devices.
*/
static struct spi_board_info ek_spi_devices[] = {
#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 1,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
{ /* DataFlash card */
.modalias = "mtd_dataflash",
.chip_select = 0,
.max_speed_hz = 15 * 1000 * 1000,
.bus_num = 0,
},
#endif
#endif
};
/*
* MACB Ethernet device
*/
static struct at91_eth_data __initdata ek_macb_data = {
.phy_irq_pin = AT91_PIN_PB0,
.is_rmii = 1,
};
/*
* NAND flash
*/
static struct mtd_partition __initdata ek_nand_partition[] = {
{
.name = "Bootstrap",
.offset = 0,
.size = 4 * SZ_1M,
},
{
.name = "Partition 1",
.offset = MTDPART_OFS_NXTBLK,
.size = 60 * SZ_1M,
},
{
.name = "Partition 2",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL,
},
};
static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
{
*num_partitions = ARRAY_SIZE(ek_nand_partition);
return ek_nand_partition;
}
/* det_pin is not connected */
static struct atmel_nand_data __initdata ek_nand_data = {
.ale = 21,
.cle = 22,
.rdy_pin = AT91_PIN_PC13,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
.bus_width_16 = 0,
#endif
};
static struct sam9_smc_config __initdata ek_nand_smc_config = {
.ncs_read_setup = 0,
.nrd_setup = 2,
.ncs_write_setup = 0,
.nwe_setup = 2,
.ncs_read_pulse = 4,
.nrd_pulse = 4,
.ncs_write_pulse = 4,
.nwe_pulse = 4,
.read_cycle = 7,
.write_cycle = 7,
.mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
.tdf_cycles = 3,
};
static void __init ek_add_device_nand(void)
{
/* setup bus-width (8 or 16) */
if (ek_nand_data.bus_width_16)
ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
else
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
/* configure chip-select 3 (NAND) */
sam9_smc_configure(3, &ek_nand_smc_config);
at91_add_device_nand(&ek_nand_data);
}
/*
* MCI (SD/MMC)
* wp_pin is not connected
*/
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
static struct mci_platform_data __initdata ek_mmc_data = {
.slot[0] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PC2,
.wp_pin = -ENODEV,
},
.slot[1] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PC9,
.wp_pin = -ENODEV,
},
};
#else
static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 1, /* Only one slot so use slot B */
.wire4 = 1,
.det_pin = AT91_PIN_PC9,
};
#endif
/*
* LEDs
*/
static struct gpio_led ek_leds[] = {
{ /* "bottom" led, green, userled1 to be defined */
.name = "ds5",
.gpio = AT91_PIN_PB8,
.active_low = 1,
.default_trigger = "none",
},
{ /* "power" led, yellow */
.name = "ds1",
.gpio = AT91_PIN_PB9,
.default_trigger = "heartbeat",
}
};
#if defined(CONFIG_REGULATOR_FIXED_VOLTAGE) || defined(CONFIG_REGULATOR_FIXED_VOLTAGE_MODULE)
static struct regulator_consumer_supply ek_audio_consumer_supplies[] = {
REGULATOR_SUPPLY("AVDD", "0-001b"),
REGULATOR_SUPPLY("HPVDD", "0-001b"),
REGULATOR_SUPPLY("DBVDD", "0-001b"),
REGULATOR_SUPPLY("DCVDD", "0-001b"),
};
static struct regulator_init_data ek_avdd_reg_init_data = {
.constraints = {
.name = "3V3",
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
.consumer_supplies = ek_audio_consumer_supplies,
.num_consumer_supplies = ARRAY_SIZE(ek_audio_consumer_supplies),
};
static struct fixed_voltage_config ek_vdd_pdata = {
.supply_name = "board-3V3",
.microvolts = 3300000,
.gpio = -EINVAL,
.enabled_at_boot = 0,
.init_data = &ek_avdd_reg_init_data,
};
static struct platform_device ek_voltage_regulator = {
.name = "reg-fixed-voltage",
.id = -1,
.num_resources = 0,
.dev = {
.platform_data = &ek_vdd_pdata,
},
};
static void __init ek_add_regulators(void)
{
platform_device_register(&ek_voltage_regulator);
}
#else
static void __init ek_add_regulators(void) {}
#endif
static struct i2c_board_info __initdata ek_i2c_devices[] = {
{
I2C_BOARD_INFO("24c512", 0x50),
},
};
static void __init ek_board_init(void)
{
/* Serial */
at91_add_device_serial();
/* USB Host */
at91_add_device_usbh(&ek_usbh_data);
/* USB Device */
at91_add_device_udc(&ek_udc_data);
/* SPI */
at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
/* NAND */
ek_add_device_nand();
/* Ethernet */
at91_add_device_eth(&ek_macb_data);
/* Regulators */
ek_add_regulators();
/* MMC */
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
at91_add_device_mci(0, &ek_mmc_data);
#else
at91_add_device_mmc(0, &ek_mmc_data);
#endif
/* I2C */
at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
/* LEDs */
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
/* PCK0 provides MCLK to the WM8731 */
at91_set_B_periph(AT91_PIN_PC1, 0);
/* SSC (for WM8731) */
at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
}
MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
/* Maintainer: Rob Emanuele */
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = ek_map_io,
.init_irq = ek_init_irq,
.init_machine = ek_board_init,
MACHINE_END

80
arch/arm/mach-at91/board-sam9g20ek.c
View File

@ -47,6 +47,18 @@
#include "sam9_smc.h"
#include "generic.h"
/*
* board revision encoding
* bit 0:
* 0 => 1 sd/mmc slot
* 1 => 2 sd/mmc slots connectors (board from revision C)
*/
#define HAVE_2MMC (1 << 0)
static int inline ek_have_2mmc(void)
{
return machine_is_at91sam9g20ek_2mmc() || (system_rev & HAVE_2MMC);
}
static void __init ek_map_io(void)
{
@ -94,7 +106,7 @@ static struct at91_udc_data __initdata ek_udc_data = {
* SPI devices.
*/
static struct spi_board_info ek_spi_devices[] = {
#if !defined(CONFIG_MMC_AT91)
#if !(defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_AT91))
{ /* DataFlash chip */
.modalias = "mtd_dataflash",
.chip_select = 1,
@ -121,6 +133,13 @@ static struct at91_eth_data __initdata ek_macb_data = {
.is_rmii = 1,
};
static void __init ek_add_device_macb(void)
{
if (ek_have_2mmc())
ek_macb_data.phy_irq_pin = AT91_PIN_PB0;
at91_add_device_eth(&ek_macb_data);
}
/*
* NAND flash
@ -198,13 +217,36 @@ static void __init ek_add_device_nand(void)
/*
* MCI (SD/MMC)
* det_pin, wp_pin and vcc_pin are not connected
* wp_pin and vcc_pin are not connected
*/
static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 1,
.wire4 = 1,
};
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
static struct mci_platform_data __initdata ek_mmc_data = {
.slot[1] = {
.bus_width = 4,
.detect_pin = AT91_PIN_PC9,
},
};
#else
static struct at91_mmc_data __initdata ek_mmc_data = {
.slot_b = 1, /* Only one slot so use slot B */
.wire4 = 1,
.det_pin = AT91_PIN_PC9,
};
#endif
static void __init ek_add_device_mmc(void)
{
#if defined(CONFIG_MMC_ATMELMCI) || defined(CONFIG_MMC_ATMELMCI_MODULE)
if (ek_have_2mmc()) {
ek_mmc_data.slot[0].bus_width = 4;
ek_mmc_data.slot[0].detect_pin = AT91_PIN_PC2;
}
at91_add_device_mci(0, &ek_mmc_data);
#else
at91_add_device_mmc(0, &ek_mmc_data);
#endif
}
/*
* LEDs
@ -223,6 +265,15 @@ static struct gpio_led ek_leds[] = {
}
};
static void __init ek_add_device_gpio_leds(void)
{
if (ek_have_2mmc()) {
ek_leds[0].gpio = AT91_PIN_PB8;
ek_leds[1].gpio = AT91_PIN_PB9;
}
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
}
/*
* GPIO Buttons
@ -336,15 +387,15 @@ static void __init ek_board_init(void)
/* NAND */
ek_add_device_nand();
/* Ethernet */
at91_add_device_eth(&ek_macb_data);
ek_add_device_macb();
/* Regulators */
ek_add_regulators();
/* MMC */
at91_add_device_mmc(0, &ek_mmc_data);
ek_add_device_mmc();
/* I2C */
at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices));
/* LEDs */
at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
ek_add_device_gpio_leds();
/* Push Buttons */
ek_add_device_buttons();
/* PCK0 provides MCLK to the WM8731 */
@ -363,3 +414,14 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
.init_irq = ek_init_irq,
.init_machine = ek_board_init,
MACHINE_END
MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
/* Maintainer: Atmel */
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
.boot_params = AT91_SDRAM_BASE + 0x100,
.timer = &at91sam926x_timer,
.map_io = ek_map_io,
.init_irq = ek_init_irq,
.init_machine = ek_board_init,
MACHINE_END

4
arch/arm/mach-at91/board-sam9m10g45ek.c
View File

@ -135,7 +135,7 @@ static struct atmel_nand_data __initdata ek_nand_data = {
.rdy_pin = AT91_PIN_PC8,
.enable_pin = AT91_PIN_PC14,
.partition_info = nand_partitions,
#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
.bus_width_16 = 1,
#else
.bus_width_16 = 0,
@ -399,7 +399,7 @@ static void __init ek_board_init(void)
at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
}
MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
/* Maintainer: Atmel */
.phys_io = AT91_BASE_SYS,
.io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,

6
arch/arm/mach-at91/include/mach/at91x40.h
View File

@ -52,4 +52,10 @@
#define AT91_DBGU_CIDR (AT91_SF + 0) /* CIDR in PS segment */
#define AT91_DBGU_EXID (AT91_SF + 4) /* EXID in PS segment */
/*
* Support defines for the simple Power Controller module.
*/
#define AT91_PS_CR (AT91_PS + 0) /* PS Control register */
#define AT91_PS_CR_CPU (1 << 0) /* CPU clock disable bit */
#endif /* AT91X40_H */

11
arch/arm/mach-at91/include/mach/system.h
View File

@ -28,17 +28,20 @@
static inline void arch_idle(void)
{
#ifndef CONFIG_DEBUG_KERNEL
/*
* Disable the processor clock. The processor will be automatically
* re-enabled by an interrupt or by a reset.
*/
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
#ifdef AT91_PS
at91_sys_write(AT91_PS_CR, AT91_PS_CR_CPU);
#else
at91_sys_write(AT91_PMC_SCDR, AT91_PMC_PCK);
#endif
#ifndef CONFIG_CPU_ARM920T
/*
* Set the processor (CP15) into 'Wait for Interrupt' mode.
* Unlike disabling the processor clock via the PMC (above)
* this allows the processor to be woken via JTAG.
* Post-RM9200 processors need this in conjunction with the above
* to save power when idle.
*/
cpu_do_idle();
#endif

2
arch/arm/mach-bcmring/include/mach/vmalloc.h
View File

@ -22,4 +22,4 @@
* 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
* larger physical memory designs better.
*/
#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
#define VMALLOC_END 0xf0000000

2
arch/arm/mach-clps711x/include/mach/vmalloc.h
View File

@ -17,4 +17,4 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#define VMALLOC_END 0xd0000000

2
arch/arm/mach-ebsa110/include/mach/vmalloc.h
View File

@ -7,4 +7,4 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#define VMALLOC_END (PAGE_OFFSET + 0x1f000000)
#define VMALLOC_END 0xdf000000

2
arch/arm/mach-ep93xx/dma-m2p.c
View File

@ -276,7 +276,7 @@ static void channel_disable(struct m2p_channel *ch)
v &= ~(M2P_CONTROL_STALL_IRQ_EN | M2P_CONTROL_NFB_IRQ_EN);
m2p_set_control(ch, v);
while (m2p_channel_state(ch) == STATE_ON)
while (m2p_channel_state(ch) >= STATE_ON)
cpu_relax();
m2p_set_control(ch, 0x0);

2
arch/arm/mach-footbridge/include/mach/vmalloc.h
View File

@ -7,4 +7,4 @@
*/
#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
#define VMALLOC_END 0xf0000000

2
arch/arm/mach-h720x/include/mach/vmalloc.h
View File

@ -5,6 +5,6 @@
#ifndef __ARCH_ARM_VMALLOC_H
#define __ARCH_ARM_VMALLOC_H
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#define VMALLOC_END 0xd0000000
#endif

15
arch/arm/mach-imx/Kconfig
View File

@ -122,6 +122,7 @@ config MACH_CPUIMX27
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select MXC_ULPI if USB_ULPI
help
Include support for Eukrea CPUIMX27 platform. This includes
specific configurations for the module and its peripherals.
@ -146,8 +147,8 @@ choice
default MACH_EUKREA_MBIMX27_BASEBOARD
config MACH_EUKREA_MBIMX27_BASEBOARD
prompt "Eukrea MBIMX27 development board"
bool
bool "Eukrea MBIMX27 development board"
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SPI_IMX
help
@ -163,6 +164,15 @@ config MACH_MX27_3DS
Include support for MX27PDK platform. This includes specific
configurations for the board and its peripherals.
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
Include support for Visstrim_m10 platform and its different variants.
This includes specific configurations for the board and its
peripherals.
config MACH_IMX27LITE
bool "LogicPD MX27 LITEKIT platform"
select IMX_HAVE_PLATFORM_IMX_UART
@ -173,6 +183,7 @@ config MACH_IMX27LITE
config MACH_PCA100
bool "Phytec phyCARD-s (pca100)"
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_SPI_IMX

1
arch/arm/mach-imx/Makefile
View File

@ -27,6 +27,7 @@ obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
obj-$(CONFIG_MACH_MX27_3DS) += mach-mx27_3ds.o
obj-$(CONFIG_MACH_IMX27LITE) += mach-imx27lite.o
obj-$(CONFIG_MACH_IMX27_VISSTRIM_M10) += mach-imx27_visstrim_m10.o
obj-$(CONFIG_MACH_CPUIMX27) += mach-cpuimx27.o
obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o

2
arch/arm/mach-imx/clock-imx1.c
View File

@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
_REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
_REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
_REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
_REGISTER_CLOCK(NULL, "mshc", mshc_clk)

6
arch/arm/mach-imx/clock-imx21.c
View File

@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
_REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
_REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
_REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
_REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
_REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
_REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
_REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
_REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
_REGISTER_CLOCK(NULL, "csi", csi_clk[0])
_REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])

48
arch/arm/mach-imx/clock-imx27.c
View File

@ -594,27 +594,27 @@ DEFINE_CLOCK(uart2_clk1, 0, PCCR1, 30, NULL, NULL, &ipg_clk);
DEFINE_CLOCK(uart1_clk1, 0, PCCR1, 31, NULL, NULL, &ipg_clk);
/* Clocks we cannot directly gate, but drivers need their rates */
DEFINE_CLOCK(cspi1_clk, 0, 0, 0, NULL, &cspi1_clk1, &per2_clk);
DEFINE_CLOCK(cspi2_clk, 1, 0, 0, NULL, &cspi2_clk1, &per2_clk);
DEFINE_CLOCK(cspi3_clk, 2, 0, 0, NULL, &cspi13_clk1, &per2_clk);
DEFINE_CLOCK(sdhc1_clk, 0, 0, 0, NULL, &sdhc1_clk1, &per2_clk);
DEFINE_CLOCK(sdhc2_clk, 1, 0, 0, NULL, &sdhc2_clk1, &per2_clk);
DEFINE_CLOCK(sdhc3_clk, 2, 0, 0, NULL, &sdhc3_clk1, &per2_clk);
DEFINE_CLOCK(pwm_clk, 0, 0, 0, NULL, &pwm_clk1, &per1_clk);
DEFINE_CLOCK(gpt1_clk, 0, 0, 0, NULL, &gpt1_clk1, &per1_clk);
DEFINE_CLOCK(gpt2_clk, 1, 0, 0, NULL, &gpt2_clk1, &per1_clk);
DEFINE_CLOCK(gpt3_clk, 2, 0, 0, NULL, &gpt3_clk1, &per1_clk);
DEFINE_CLOCK(gpt4_clk, 3, 0, 0, NULL, &gpt4_clk1, &per1_clk);
DEFINE_CLOCK(gpt5_clk, 4, 0, 0, NULL, &gpt5_clk1, &per1_clk);
DEFINE_CLOCK(gpt6_clk, 5, 0, 0, NULL, &gpt6_clk1, &per1_clk);
DEFINE_CLOCK(uart1_clk, 0, 0, 0, NULL, &uart1_clk1, &per1_clk);
DEFINE_CLOCK(uart2_clk, 1, 0, 0, NULL, &uart2_clk1, &per1_clk);
DEFINE_CLOCK(uart3_clk, 2, 0, 0, NULL, &uart3_clk1, &per1_clk);
DEFINE_CLOCK(uart4_clk, 3, 0, 0, NULL, &uart4_clk1, &per1_clk);
DEFINE_CLOCK(uart5_clk, 4, 0, 0, NULL, &uart5_clk1, &per1_clk);
DEFINE_CLOCK(uart6_clk, 5, 0, 0, NULL, &uart6_clk1, &per1_clk);
DEFINE_CLOCK1(lcdc_clk, 0, 0, 0, parent, &lcdc_clk1, &per3_clk);
DEFINE_CLOCK1(csi_clk, 0, 0, 0, parent, &csi_clk1, &per4_clk);
DEFINE_CLOCK(cspi1_clk, 0, NULL, 0, NULL, &cspi1_clk1, &per2_clk);
DEFINE_CLOCK(cspi2_clk, 1, NULL, 0, NULL, &cspi2_clk1, &per2_clk);
DEFINE_CLOCK(cspi3_clk, 2, NULL, 0, NULL, &cspi13_clk1, &per2_clk);
DEFINE_CLOCK(sdhc1_clk, 0, NULL, 0, NULL, &sdhc1_clk1, &per2_clk);
DEFINE_CLOCK(sdhc2_clk, 1, NULL, 0, NULL, &sdhc2_clk1, &per2_clk);
DEFINE_CLOCK(sdhc3_clk, 2, NULL, 0, NULL, &sdhc3_clk1, &per2_clk);
DEFINE_CLOCK(pwm_clk, 0, NULL, 0, NULL, &pwm_clk1, &per1_clk);
DEFINE_CLOCK(gpt1_clk, 0, NULL, 0, NULL, &gpt1_clk1, &per1_clk);
DEFINE_CLOCK(gpt2_clk, 1, NULL, 0, NULL, &gpt2_clk1, &per1_clk);
DEFINE_CLOCK(gpt3_clk, 2, NULL, 0, NULL, &gpt3_clk1, &per1_clk);
DEFINE_CLOCK(gpt4_clk, 3, NULL, 0, NULL, &gpt4_clk1, &per1_clk);
DEFINE_CLOCK(gpt5_clk, 4, NULL, 0, NULL, &gpt5_clk1, &per1_clk);
DEFINE_CLOCK(gpt6_clk, 5, NULL, 0, NULL, &gpt6_clk1, &per1_clk);
DEFINE_CLOCK(uart1_clk, 0, NULL, 0, NULL, &uart1_clk1, &per1_clk);
DEFINE_CLOCK(uart2_clk, 1, NULL, 0, NULL, &uart2_clk1, &per1_clk);
DEFINE_CLOCK(uart3_clk, 2, NULL, 0, NULL, &uart3_clk1, &per1_clk);
DEFINE_CLOCK(uart4_clk, 3, NULL, 0, NULL, &uart4_clk1, &per1_clk);
DEFINE_CLOCK(uart5_clk, 4, NULL, 0, NULL, &uart5_clk1, &per1_clk);
DEFINE_CLOCK(uart6_clk, 5, NULL, 0, NULL, &uart6_clk1, &per1_clk);
DEFINE_CLOCK1(lcdc_clk, 0, NULL, 0, parent, &lcdc_clk1, &per3_clk);
DEFINE_CLOCK1(csi_clk, 0, NULL, 0, parent, &csi_clk1, &per4_clk);
#define _REGISTER_CLOCK(d, n, c) \
{ \
@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
_REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
_REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
_REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
_REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)

14
arch/arm/mach-imx/devices-imx1.h
View File

@ -9,10 +9,12 @@
#include <mach/mx1.h>
#include <mach/devices-common.h>
#define imx1_add_i2c_imx(pdata) \
imx_add_imx_i2c(0, MX1_I2C_BASE_ADDR, SZ_4K, MX1_INT_I2C, pdata)
extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
#define imx1_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
#define imx1_add_imx_uart0(pdata) \
imx_add_imx_uart_3irq(0, MX1_UART1_BASE_ADDR, 0xd0, MX1_INT_UART1RX, MX1_INT_UART1TX, MX1_INT_UART1RTS, pdata)
#define imx1_add_imx_uart1(pdata) \
imx_add_imx_uart_3irq(0, MX1_UART2_BASE_ADDR, 0xd0, MX1_INT_UART2RX, MX1_INT_UART2TX, MX1_INT_UART2RTS, pdata)
extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
#define imx1_add_imx_uart(id, pdata) \
imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)

36
arch/arm/mach-imx/devices-imx21.h
View File

@ -9,22 +9,28 @@
#include <mach/mx21.h>
#include <mach/devices-common.h>
#define imx21_add_i2c_imx(pdata) \
imx_add_imx_i2c(0, MX2x_I2C_BASE_ADDR, SZ_4K, MX2x_INT_I2C, pdata)
extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
#define imx21_add_imx_uart0(pdata) \
imx_add_imx_uart_1irq(0, MX21_UART1_BASE_ADDR, SZ_4K, MX21_INT_UART1, pdata)
#define imx21_add_imx_uart1(pdata) \
imx_add_imx_uart_1irq(1, MX21_UART2_BASE_ADDR, SZ_4K, MX21_INT_UART2, pdata)
#define imx21_add_imx_uart2(pdata) \
imx_add_imx_uart_1irq(2, MX21_UART3_BASE_ADDR, SZ_4K, MX21_INT_UART3, pdata)
#define imx21_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(3, MX21_UART4_BASE_ADDR, SZ_4K, MX21_INT_UART4, pdata)
extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
#define imx21_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
#define imx21_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
#define imx21_add_imx_uart1(pdata) imx21_add_imx_uart(1, pdata)
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
#define imx21_add_spi_imx0(pdata) \
imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
#define imx21_add_spi_imx1(pdata) \
imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
#define imx21_add_cspi(id, pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)
#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)
#define imx21_add_spi_imx1(pdata) imx21_add_cspi(1, pdata)

51
arch/arm/mach-imx/devices-imx27.h
View File

@ -9,30 +9,35 @@
#include <mach/mx27.h>
#include <mach/devices-common.h>
#define imx27_add_i2c_imx0(pdata) \
imx_add_imx_i2c(0, MX27_I2C1_BASE_ADDR, SZ_4K, MX27_INT_I2C1, pdata)
#define imx27_add_i2c_imx1(pdata) \
imx_add_imx_i2c(1, MX27_I2C2_BASE_ADDR, SZ_4K, MX27_INT_I2C2, pdata)
extern const struct imx_fec_data imx27_fec_data __initconst;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
#define imx27_add_imx_uart0(pdata) \
imx_add_imx_uart_1irq(0, MX27_UART1_BASE_ADDR, SZ_4K, MX27_INT_UART1, pdata)
#define imx27_add_imx_uart1(pdata) \
imx_add_imx_uart_1irq(1, MX27_UART2_BASE_ADDR, SZ_4K, MX27_INT_UART2, pdata)
#define imx27_add_imx_uart2(pdata) \
imx_add_imx_uart_1irq(2, MX27_UART3_BASE_ADDR, SZ_4K, MX27_INT_UART3, pdata)
#define imx27_add_imx_uart3(pdata) \
imx_add_imx_uart_1irq(3, MX27_UART4_BASE_ADDR, SZ_4K, MX27_INT_UART4, pdata)
#define imx27_add_imx_uart4(pdata) \
imx_add_imx_uart_1irq(4, MX27_UART5_BASE_ADDR, SZ_4K, MX27_INT_UART5, pdata)
#define imx27_add_imx_uart5(pdata) \
imx_add_imx_uart_1irq(5, MX27_UART6_BASE_ADDR, SZ_4K, MX27_INT_UART6, pdata)
extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
#define imx27_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
#define imx27_add_imx_uart1(pdata) imx27_add_imx_uart(1, pdata)
#define imx27_add_imx_uart2(pdata) imx27_add_imx_uart(2, pdata)
#define imx27_add_imx_uart3(pdata) imx27_add_imx_uart(3, pdata)
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
#define imx27_add_spi_imx0(pdata) \
imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
#define imx27_add_spi_imx1(pdata) \
imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
#define imx27_add_spi_imx2(pdata) \
imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
#define imx27_add_cspi(id, pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)
#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata)
#define imx27_add_spi_imx1(pdata) imx27_add_cspi(1, pdata)
#define imx27_add_spi_imx2(pdata) imx27_add_cspi(2, pdata)

56
arch/arm/mach-imx/devices.c
View File

@ -314,27 +314,6 @@ struct platform_device mxc_fb_device = {
},
};
#ifdef CONFIG_MACH_MX27
static struct resource mxc_fec_resources[] = {
{
.start = MX27_FEC_BASE_ADDR,
.end = MX27_FEC_BASE_ADDR + SZ_4K - 1,
.flags = IORESOURCE_MEM,
}, {
.start = MX27_INT_FEC,
.end = MX27_INT_FEC,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device mxc_fec_device = {
.name = "fec",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_fec_resources),
.resource = mxc_fec_resources,
};
#endif
static struct resource mxc_pwm_resources[] = {
{
.start = MX2x_PWM_BASE_ADDR,
@ -480,41 +459,6 @@ struct platform_device mxc_usbh2 = {
};
#endif
#define DEFINE_IMX_SSI_DMARES(_name, ssin, suffix) \
{ \
.name = _name, \
.start = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
.end = MX2x_DMA_REQ_SSI ## ssin ## _ ## suffix, \
.flags = IORESOURCE_DMA, \
}
#define DEFINE_IMX_SSI_DEVICE(n, ssin, baseaddr, irq) \
static struct resource imx_ssi_resources ## n[] = { \
{ \
.start = MX2x_SSI ## ssin ## _BASE_ADDR, \
.end = MX2x_SSI ## ssin ## _BASE_ADDR + 0x6f, \
.flags = IORESOURCE_MEM, \
}, { \
.start = MX2x_INT_SSI1, \
.end = MX2x_INT_SSI1, \
.flags = IORESOURCE_IRQ, \
}, \
DEFINE_IMX_SSI_DMARES("tx0", ssin, TX0), \
DEFINE_IMX_SSI_DMARES("rx0", ssin, RX0), \
DEFINE_IMX_SSI_DMARES("tx1", ssin, TX1), \
DEFINE_IMX_SSI_DMARES("rx1", ssin, RX1), \
}; \
\
struct platform_device imx_ssi_device ## n = { \
.name = "imx-ssi", \
.id = n, \
.num_resources = ARRAY_SIZE(imx_ssi_resources ## n), \
.resource = imx_ssi_resources ## n, \
}
DEFINE_IMX_SSI_DEVICE(0, 1, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
DEFINE_IMX_SSI_DEVICE(1, 2, MX2x_SSI1_BASE_ADDR, MX2x_INT_SSI1);
/* GPIO port description */
#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
{ \

3
arch/arm/mach-imx/devices.h
View File

@ -16,7 +16,6 @@ extern struct platform_device mxc_gpt5;
extern struct platform_device mxc_wdt;
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mxc_fb_device;
extern struct platform_device mxc_fec_device;
extern struct platform_device mxc_pwm_device;
extern struct platform_device mxc_sdhc_device0;
extern struct platform_device mxc_sdhc_device1;
@ -26,7 +25,5 @@ extern struct platform_device mxc_otg_host;
extern struct platform_device mxc_usbh1;
extern struct platform_device mxc_usbh2;
extern struct platform_device mx21_usbhc_device;
extern struct platform_device imx_ssi_device0;
extern struct platform_device imx_ssi_device1;
extern struct platform_device imx_kpp_device;
#endif

8
arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
View File

@ -36,13 +36,12 @@
#include <mach/hardware.h>
#include <mach/mmc.h>
#include <mach/spi.h>
#include <mach/ssi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"
#include "devices.h"
static int eukrea_mbimx27_pins[] = {
static const int eukrea_mbimx27_pins[] __initconst = {
/* UART2 */
PE3_PF_UART2_CTS,
PE4_PF_UART2_RTS,
@ -311,7 +310,8 @@ static struct imxmmc_platform_data sdhc_pdata = {
.dat3_card_detect = 1,
};
struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata = {
static const
struct imx_ssi_platform_data eukrea_mbimx27_ssi_pdata __initconst = {
.flags = IMX_SSI_DMA | IMX_SSI_USE_I2S_SLAVE,
};
@ -357,7 +357,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
mxc_register_device(&imx_ssi_device0, &eukrea_mbimx27_ssi_pdata);
imx27_add_imx_ssi(0, &eukrea_mbimx27_ssi_pdata);
#if defined(CONFIG_TOUCHSCREEN_ADS7846) \
|| defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)

6
arch/arm/mach-imx/mach-cpuimx27.c
View File

@ -46,7 +46,7 @@
#include "devices-imx27.h"
#include "devices.h"
static int eukrea_cpuimx27_pins[] = {
static const int eukrea_cpuimx27_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
@ -157,7 +157,6 @@ cpuimx27_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&eukrea_cpuimx27_nor_mtd_device,
&mxc_fec_device,
&mxc_wdt,
&mxc_w1_master_device,
};
@ -259,8 +258,9 @@ static void __init eukrea_cpuimx27_init(void)
i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
imx27_add_i2c_imx1(&cpuimx27_i2c1_data);
imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)

263
arch/arm/mach-imx/mach-imx27_visstrim_m10.c Normal file
View File

@ -0,0 +1,263 @@
/*
* mach-imx27_visstrim_m10.c
*
* Copyright 2010 Javier Martin <javier.martin@vista-silicon.com>
*
* Based on mach-pcm038.c, mach-pca100.c, mach-mx27ads.c and others.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*/
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
#include <mach/mmc.h>
#include <mach/iomux.h>
#include <mach/mxc_ehci.h>
#include "devices-imx27.h"
#include "devices.h"
#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
#define SDHC1_IRQ IRQ_GPIOB(25)
static const int visstrim_m10_pins[] __initconst = {
/* UART1 (console) */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* SDHC1 */
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
/* Both I2Cs */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
/* USB OTG */
OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT,
PC9_PF_USBOTG_DATA0,
PC11_PF_USBOTG_DATA1,
PC10_PF_USBOTG_DATA2,
PC13_PF_USBOTG_DATA3,
PC12_PF_USBOTG_DATA4,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PE25_PF_USBOTG_DATA7,
PE24_PF_USBOTG_CLK,
PE2_PF_USBOTG_DIR,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PB23_PF_USB_PWR,
PB24_PF_USB_OC,
};
/* GPIOs used as events for applications */
static struct gpio_keys_button visstrim_gpio_keys[] = {
{
.type = EV_KEY,
.code = KEY_RESTART,
.gpio = (GPIO_PORTC + 15),
.desc = "Default config",
.active_low = 0,
.wakeup = 1,
},
{
.type = EV_KEY,
.code = KEY_RECORD,
.gpio = (GPIO_PORTF + 14),
.desc = "Record",
.active_low = 0,
.wakeup = 1,
},
{
.type = EV_KEY,
.code = KEY_STOP,
.gpio = (GPIO_PORTF + 13),
.desc = "Stop",
.active_low = 0,
.wakeup = 1,
}
};
static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
.buttons = visstrim_gpio_keys,
.nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
};
static struct platform_device visstrim_gpio_keys_device = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &visstrim_gpio_keys_platform_data,
},
};
/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
static int visstrim_m10_sdhc1_init(struct device *dev,
irq_handler_t detect_irq, void *data)
{
int ret;
ret = request_irq(SDHC1_IRQ, detect_irq, IRQF_TRIGGER_FALLING,
"mmc-detect", data);
return ret;
}
static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
{
free_irq(SDHC1_IRQ, data);
}
static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = {
.init = visstrim_m10_sdhc1_init,
.exit = visstrim_m10_sdhc1_exit,
};
/* Visstrim_SM10 NOR flash */
static struct physmap_flash_data visstrim_m10_flash_data = {
.width = 2,
};
static struct resource visstrim_m10_flash_resource = {
.start = 0xc0000000,
.end = 0xc0000000 + SZ_64M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device visstrim_m10_nor_mtd_device = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &visstrim_m10_flash_data,
},
.num_resources = 1,
.resource = &visstrim_m10_flash_resource,
};
static struct platform_device *platform_devices[] __initdata = {
&visstrim_gpio_keys_device,
&visstrim_m10_nor_mtd_device,
};
/* Visstrim_M10 uses UART0 as console */
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
/* I2C */
static const struct imxi2c_platform_data visstrim_m10_i2c_data __initconst = {
.bitrate = 100000,
};
static struct pca953x_platform_data visstrim_m10_pca9555_pdata = {
.gpio_base = 240, /* After MX27 internal GPIOs */
.invert = 0,
};
static struct i2c_board_info visstrim_m10_i2c_devices[] = {
{
I2C_BOARD_INFO("pca9555", 0x20),
.platform_data = &visstrim_m10_pca9555_pdata,
},
};
/* USB OTG */
static int otg_phy_init(struct platform_device *pdev)
{
gpio_set_value(OTG_PHY_CS_GPIO, 0);
return 0;
}
static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = {
.init = otg_phy_init,
.portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
.flags = MXC_EHCI_POWER_PINS_ENABLED,
};
static void __init visstrim_m10_board_init(void)
{
int ret;
ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
if (ret)
pr_err("Failed to setup pins (%d)\n", ret);
imx27_add_imx_uart0(&uart_pdata);
i2c_register_board_info(0, visstrim_m10_i2c_devices,
ARRAY_SIZE(visstrim_m10_i2c_devices));
imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata);
mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
static void __init visstrim_m10_timer_init(void)
{
mx27_clocks_init((unsigned long)25000000);
}
static struct sys_timer visstrim_m10_timer = {
.init = visstrim_m10_timer_init,
};
MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
.phys_io = MX27_AIPI_BASE_ADDR,
.io_pg_offst = ((MX27_AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = MX27_PHYS_OFFSET + 0x100,
.map_io = mx27_map_io,
.init_irq = mx27_init_irq,
.init_machine = visstrim_m10_board_init,
.timer = &visstrim_m10_timer,
MACHINE_END

8
arch/arm/mach-imx/mach-imx27lite.c
View File

@ -27,7 +27,7 @@
#include "devices-imx27.h"
#include "devices.h"
static unsigned int mx27lite_pins[] = {
static const int mx27lite_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
@ -58,16 +58,12 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct platform_device *platform_devices[] __initdata = {
&mxc_fec_device,
};
static void __init mx27lite_init(void)
{
mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
"imx27lite");
imx27_add_imx_uart0(&uart_pdata);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_fec(NULL);
}
static void __init mx27lite_timer_init(void)

4
arch/arm/mach-imx/mach-mx1ads.c
View File

@ -32,7 +32,7 @@
#include "devices-imx1.h"
#include "devices.h"
static int mx1ads_pins[] = {
static const int mx1ads_pins[] __initconst = {
/* UART1 */
PC9_PF_UART1_CTS,
PC10_PF_UART1_RTS,
@ -131,7 +131,7 @@ static void __init mx1ads_init(void)
i2c_register_board_info(0, mx1ads_i2c_devices,
ARRAY_SIZE(mx1ads_i2c_devices));
imx1_add_i2c_imx(&mx1ads_i2c_data);
imx1_add_imx_i2c(&mx1ads_i2c_data);
}
static void __init mx1ads_timer_init(void)

2
arch/arm/mach-imx/mach-mx21ads.c
View File

@ -67,7 +67,7 @@
#define MX21ADS_IO_LED4_ON 0x4000
#define MX21ADS_IO_LED3_ON 0x8000
static unsigned int mx21ads_pins[] = {
static const int mx21ads_pins[] __initconst = {
/* CS8900A */
(GPIO_PORTE | GPIO_GPIO | GPIO_IN | 11),

8
arch/arm/mach-imx/mach-mx27_3ds.c
View File

@ -33,7 +33,7 @@
#include "devices-imx27.h"
#include "devices.h"
static unsigned int mx27pdk_pins[] = {
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
@ -64,10 +64,6 @@ static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct platform_device *platform_devices[] __initdata = {
&mxc_fec_device,
};
/*
* Matrix keyboard
*/
@ -94,7 +90,7 @@ static void __init mx27pdk_init(void)
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
"mx27pdk");
imx27_add_imx_uart0(&uart_pdata);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_fec(NULL);
mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data);
}

6
arch/arm/mach-imx/mach-mx27ads.c
View File

@ -66,7 +66,7 @@
/* to determine the correct external crystal reference */
#define CKIH_27MHZ_BIT_SET (1 << 3)
static unsigned int mx27ads_pins[] = {
static const int mx27ads_pins[] __initconst = {
/* UART0 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
@ -284,7 +284,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
static struct platform_device *platform_devices[] __initdata = {
&mx27ads_nor_mtd_device,
&mxc_fec_device,
&mxc_w1_master_device,
};
@ -308,11 +307,12 @@ static void __init mx27ads_board_init(void)
/* only the i2c master 1 is used on this CPU card */
i2c_register_board_info(1, mx27ads_i2c_devices,
ARRAY_SIZE(mx27ads_i2c_devices));
imx27_add_i2c_imx1(&mx27ads_i2c1_data);
imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
mxc_register_device(&mxc_fb_device, &mx27ads_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

13
arch/arm/mach-imx/mach-mxt_td60.c
View File

@ -37,7 +37,7 @@
#include "devices-imx27.h"
#include "devices.h"
static unsigned int mxt_td60_pins[] __initdata = {
static const int mxt_td60_pins[] __initconst = {
/* UART0 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
@ -231,10 +231,6 @@ static struct imxmmc_platform_data sdhc1_pdata = {
.exit = mxt_td60_sdhc1_exit,
};
static struct platform_device *platform_devices[] __initdata = {
&mxc_fec_device,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@ -255,12 +251,11 @@ static void __init mxt_td60_board_init(void)
i2c_register_board_info(1, mxt_td60_i2c2_devices,
ARRAY_SIZE(mxt_td60_i2c2_devices));
imx27_add_i2c_imx0(&mxt_td60_i2c0_data);
imx27_add_i2c_imx1(&mxt_td60_i2c1_data);
imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data);
mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx27_add_fec(NULL);
}
static void __init mxt_td60_timer_init(void)

15
arch/arm/mach-imx/mach-pca100.c
View File

@ -38,7 +38,6 @@
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
#include <mach/audmux.h>
#include <mach/ssi.h>
#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/mmc.h>
@ -55,7 +54,7 @@
#define SPI1_SS1 (GPIO_PORTD + 27)
#define SD2_CD (GPIO_PORTC + 29)
static int pca100_pins[] = {
static const int pca100_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
@ -174,7 +173,6 @@ pca100_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&mxc_w1_master_device,
&mxc_fec_device,
&mxc_wdt,
};
@ -193,11 +191,9 @@ static struct i2c_board_info pca100_i2c_devices[] = {
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
.platform_data = &board_eeprom,
}, {
I2C_BOARD_INFO("rtc-pcf8563", 0x51),
.type = "pcf8563"
I2C_BOARD_INFO("pcf8563", 0x51),
}, {
I2C_BOARD_INFO("lm75", 0x4a),
.type = "lm75"
}
};
@ -252,7 +248,7 @@ static void pca100_ac97_cold_reset(struct snd_ac97 *ac97)
msleep(2);
}
static struct imx_ssi_platform_data pca100_ssi_pdata = {
static const struct imx_ssi_platform_data pca100_ssi_pdata __initconst = {
.ac97_reset = pca100_ac97_cold_reset,
.ac97_warm_reset = pca100_ac97_warm_reset,
.flags = IMX_SSI_USE_AC97,
@ -389,7 +385,7 @@ static void __init pca100_init(void)
if (ret)
printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
mxc_register_device(&imx_ssi_device0, &pca100_ssi_pdata);
imx27_add_imx_ssi(0, &pca100_ssi_pdata);
imx27_add_imx_uart0(&uart_pdata);
@ -401,7 +397,7 @@ static void __init pca100_init(void)
i2c_register_board_info(1, pca100_i2c_devices,
ARRAY_SIZE(pca100_i2c_devices));
imx27_add_i2c_imx1(&pca100_i2c1_data);
imx27_add_imx_i2c(1, &pca100_i2c1_data);
#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
@ -436,6 +432,7 @@ static void __init pca100_init(void)
mxc_register_device(&mxc_fb_device, &pca100_fb_data);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}

8
arch/arm/mach-imx/mach-pcm038.c
View File

@ -43,7 +43,7 @@
#include "devices-imx27.h"
#include "devices.h"
static int pcm038_pins[] = {
static const int pcm038_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
@ -173,7 +173,6 @@ pcm038_nand_board_info __initconst = {
static struct platform_device *platform_devices[] __initdata = {
&pcm038_nor_mtd_device,
&mxc_w1_master_device,
&mxc_fec_device,
&pcm038_sram_mtd_device,
&mxc_wdt,
};
@ -257,7 +256,7 @@ static struct regulator_init_data cam_data = {
.consumer_supplies = cam_consumers,
};
struct mc13783_regulator_init_data pcm038_regulators[] = {
static struct mc13783_regulator_init_data pcm038_regulators[] = {
{
.id = MC13783_REGU_VCAM,
.init_data = &cam_data,
@ -309,7 +308,7 @@ static void __init pcm038_init(void)
i2c_register_board_info(1, pcm038_i2c_devices,
ARRAY_SIZE(pcm038_i2c_devices));
imx27_add_i2c_imx1(&pcm038_i2c1_data);
imx27_add_imx_i2c(1, &pcm038_i2c1_data);
/* PE18 for user-LED D40 */
mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
@ -325,6 +324,7 @@ static void __init pcm038_init(void)
mxc_register_device(&mxc_usbh2, &usbh2_pdata);
imx27_add_fec(NULL);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
#ifdef CONFIG_MACH_PCM970_BASEBOARD

2
arch/arm/mach-imx/mach-scb9328.c
View File

@ -95,7 +95,7 @@ static struct platform_device dm9000x_device = {
}
};
static int mxc_uart1_pins[] = {
static const int mxc_uart1_pins[] = {
PC9_PF_UART1_CTS,
PC10_PF_UART1_RTS,
PC11_PF_UART1_TXD,

4
arch/arm/mach-imx/pcm970-baseboard.c
View File

@ -31,7 +31,7 @@
#include "devices.h"
static int pcm970_pins[] = {
static const int pcm970_pins[] __initconst = {
/* SDHC */
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
@ -200,7 +200,7 @@ static struct resource pcm970_sja1000_resources[] = {
},
};
struct sja1000_platform_data pcm970_sja1000_platform_data = {
static struct sja1000_platform_data pcm970_sja1000_platform_data = {
.osc_freq = 16000000,
.ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
.cdr = CDR_CBP,

2
arch/arm/mach-integrator/include/mach/vmalloc.h
View File

@ -17,4 +17,4 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#define VMALLOC_END 0xd0000000

12
arch/arm/mach-kirkwood/Kconfig
View File

@ -58,6 +58,12 @@ config MACH_TS41X
QNAP TS-410, TS-410U, TS-419P and TS-419U Turbo NAS
devices.
config MACH_DOCKSTAR
bool "Seagate FreeAgent DockStar"
help
Say 'Y' here if you want your kernel to support the
Seagate FreeAgent DockStar.
config MACH_OPENRD
bool
@ -100,6 +106,12 @@ config MACH_NETSPACE_MAX_V2
Say 'Y' here if you want your kernel to support the
LaCie Network Space Max v2 NAS.
config MACH_D2NET_V2
bool "LaCie d2 Network v2 NAS Board"
help
Say 'Y' here if you want your kernel to support the
LaCie d2 Network v2 NAS.
config MACH_NET2BIG_V2
bool "LaCie 2Big Network v2 NAS Board"
help

12
arch/arm/mach-kirkwood/Makefile
View File

@ -7,14 +7,16 @@ obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o
obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o
obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o
obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o
obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o
obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o
obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o
obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o
obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o
obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_T5325) += t5325-setup.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o

231
arch/arm/mach-kirkwood/d2net_v2-setup.c Normal file
View File

@ -0,0 +1,231 @@
/*
* arch/arm/mach-kirkwood/d2net_v2-setup.c
*
* LaCie d2 Network Space v2 Board Setup
*
* Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/kirkwood.h>
#include <mach/leds-ns2.h>
#include "common.h"
#include "mpp.h"
#include "lacie_v2-common.h"
/*****************************************************************************
* Ethernet
****************************************************************************/
static struct mv643xx_eth_platform_data d2net_v2_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
/*****************************************************************************
* SATA
****************************************************************************/
static struct mv_sata_platform_data d2net_v2_sata_data = {
.n_ports = 2,
};
/*****************************************************************************
* GPIO keys
****************************************************************************/
#define D2NET_V2_GPIO_PUSH_BUTTON 34
#define D2NET_V2_GPIO_POWER_SWITCH_ON 13
#define D2NET_V2_GPIO_POWER_SWITCH_OFF 15
#define D2NET_V2_SWITCH_POWER_ON 0x1
#define D2NET_V2_SWITCH_POWER_OFF 0x2
static struct gpio_keys_button d2net_v2_buttons[] = {
[0] = {
.type = EV_SW,
.code = D2NET_V2_SWITCH_POWER_ON,
.gpio = D2NET_V2_GPIO_POWER_SWITCH_ON,
.desc = "Back power switch (on|auto)",
.active_low = 0,
},
[1] = {
.type = EV_SW,
.code = D2NET_V2_SWITCH_POWER_OFF,
.gpio = D2NET_V2_GPIO_POWER_SWITCH_OFF,
.desc = "Back power switch (auto|off)",
.active_low = 0,
},
[2] = {
.code = KEY_POWER,
.gpio = D2NET_V2_GPIO_PUSH_BUTTON,
.desc = "Front Push Button",
.active_low = 1,
},
};
static struct gpio_keys_platform_data d2net_v2_button_data = {
.buttons = d2net_v2_buttons,
.nbuttons = ARRAY_SIZE(d2net_v2_buttons),
};
static struct platform_device d2net_v2_gpio_buttons = {
.name = "gpio-keys",
.id = -1,
.dev = {
.platform_data = &d2net_v2_button_data,
},
};
/*****************************************************************************
* GPIO LEDs
****************************************************************************/
#define D2NET_V2_GPIO_RED_LED 12
static struct gpio_led d2net_v2_gpio_led_pins[] = {
{
.name = "d2net_v2:red:fail",
.gpio = D2NET_V2_GPIO_RED_LED,
},
};
static struct gpio_led_platform_data d2net_v2_gpio_leds_data = {
.num_leds = ARRAY_SIZE(d2net_v2_gpio_led_pins),
.leds = d2net_v2_gpio_led_pins,
};
static struct platform_device d2net_v2_gpio_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &d2net_v2_gpio_leds_data,
},
};
/*****************************************************************************
* Dual-GPIO CPLD LEDs
****************************************************************************/
#define D2NET_V2_GPIO_BLUE_LED_SLOW 29
#define D2NET_V2_GPIO_BLUE_LED_CMD 30
static struct ns2_led d2net_v2_led_pins[] = {
{
.name = "d2net_v2:blue:sata",
.cmd = D2NET_V2_GPIO_BLUE_LED_CMD,
.slow = D2NET_V2_GPIO_BLUE_LED_SLOW,
},
};
static struct ns2_led_platform_data d2net_v2_leds_data = {
.num_leds = ARRAY_SIZE(d2net_v2_led_pins),
.leds = d2net_v2_led_pins,
};
static struct platform_device d2net_v2_leds = {
.name = "leds-ns2",
.id = -1,
.dev = {
.platform_data = &d2net_v2_leds_data,
},
};
/*****************************************************************************
* General Setup
****************************************************************************/
static unsigned int d2net_v2_mpp_config[] __initdata = {
MPP0_SPI_SCn,
MPP1_SPI_MOSI,
MPP2_SPI_SCK,
MPP3_SPI_MISO,
MPP6_SYSRST_OUTn,
MPP7_GPO, /* Request power-off */
MPP8_TW0_SDA,
MPP9_TW0_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_GPO, /* Red led */
MPP13_GPIO, /* Rear power switch (on|auto) */
MPP14_GPIO, /* USB fuse */
MPP15_GPIO, /* Rear power switch (auto|off) */
MPP16_GPIO, /* SATA 0 power */
MPP21_SATA0_ACTn,
MPP24_GPIO, /* USB mode select */
MPP26_GPIO, /* USB device vbus */
MPP28_GPIO, /* USB enable host vbus */
MPP29_GPIO, /* Blue led (slow register) */
MPP30_GPIO, /* Blue led (command register) */
MPP34_GPIO, /* Power button (1 = Released, 0 = Pushed) */
MPP35_GPIO, /* Inhibit power-off */
0
};
#define D2NET_V2_GPIO_POWER_OFF 7
static void d2net_v2_power_off(void)
{
gpio_set_value(D2NET_V2_GPIO_POWER_OFF, 1);
}
static void __init d2net_v2_init(void)
{
/*
* Basic setup. Needs to be called early.
*/
kirkwood_init();
kirkwood_mpp_conf(d2net_v2_mpp_config);
lacie_v2_hdd_power_init(1);
kirkwood_ehci_init();
kirkwood_ge00_init(&d2net_v2_ge00_data);
kirkwood_sata_init(&d2net_v2_sata_data);
kirkwood_uart0_init();
lacie_v2_register_flash();
lacie_v2_register_i2c_devices();
platform_device_register(&d2net_v2_leds);
platform_device_register(&d2net_v2_gpio_leds);
platform_device_register(&d2net_v2_gpio_buttons);
if (gpio_request(D2NET_V2_GPIO_POWER_OFF, "power-off") == 0 &&
gpio_direction_output(D2NET_V2_GPIO_POWER_OFF, 0) == 0)
pm_power_off = d2net_v2_power_off;
else
pr_err("d2net_v2: failed to configure power-off GPIO\n");
}
MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
.phys_io = KIRKWOOD_REGS_PHYS_BASE,
.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = d2net_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &lacie_v2_timer,
MACHINE_END

112
arch/arm/mach-kirkwood/dockstar-setup.c Normal file
View File

@ -0,0 +1,112 @@
/*
* arch/arm/mach-kirkwood/dockstar-setup.c
*
* Seagate FreeAgent DockStar Setup
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/ata_platform.h>
#include <linux/mtd/partitions.h>
#include <linux/mv643xx_eth.h>
#include <linux/gpio.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/kirkwood.h>
#include <plat/mvsdio.h>
#include "common.h"
#include "mpp.h"
static struct mtd_partition dockstar_nand_parts[] = {
{
.name = "u-boot",
.offset = 0,
.size = SZ_1M
}, {
.name = "uImage",
.offset = MTDPART_OFS_NXTBLK,
.size = SZ_4M
}, {
.name = "root",
.offset = MTDPART_OFS_NXTBLK,
.size = MTDPART_SIZ_FULL
},
};
static struct mv643xx_eth_platform_data dockstar_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
};
static struct gpio_led dockstar_led_pins[] = {
{
.name = "dockstar:green:health",
.default_trigger = "default-on",
.gpio = 46,
.active_low = 1,
},
{
.name = "dockstar:orange:misc",
.default_trigger = "none",
.gpio = 47,
.active_low = 1,
},
};
static struct gpio_led_platform_data dockstar_led_data = {
.leds = dockstar_led_pins,
.num_leds = ARRAY_SIZE(dockstar_led_pins),
};
static struct platform_device dockstar_leds = {
.name = "leds-gpio",
.id = -1,
.dev = {
.platform_data = &dockstar_led_data,
}
};
static unsigned int dockstar_mpp_config[] __initdata = {
MPP29_GPIO, /* USB Power Enable */
MPP46_GPIO, /* LED green */
MPP47_GPIO, /* LED orange */
0
};
static void __init dockstar_init(void)
{
/*
* Basic setup. Needs to be called early.
*/
kirkwood_init();
/* setup gpio pin select */
kirkwood_mpp_conf(dockstar_mpp_config);
kirkwood_uart0_init();
kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25);
if (gpio_request(29, "USB Power Enable") != 0 ||
gpio_direction_output(29, 1) != 0)
printk(KERN_ERR "can't set up GPIO 29 (USB Power Enable)\n");
kirkwood_ehci_init();
kirkwood_ge00_init(&dockstar_ge00_data);
platform_device_register(&dockstar_leds);
}
MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
.phys_io = KIRKWOOD_REGS_PHYS_BASE,
.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
.boot_params = 0x00000100,
.init_machine = dockstar_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &kirkwood_timer,
MACHINE_END

55
arch/arm/mach-kirkwood/include/mach/leds-netxbig.h Normal file
View File

@ -0,0 +1,55 @@
/*
* arch/arm/mach-kirkwood/include/mach/leds-netxbig.h
*
* Platform data structure for netxbig LED driver
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MACH_LEDS_NETXBIG_H
#define __MACH_LEDS_NETXBIG_H
struct netxbig_gpio_ext {
unsigned *addr;
int num_addr;
unsigned *data;
int num_data;
unsigned enable;
};
enum netxbig_led_mode {
NETXBIG_LED_OFF,
NETXBIG_LED_ON,
NETXBIG_LED_SATA,
NETXBIG_LED_TIMER1,
NETXBIG_LED_TIMER2,
NETXBIG_LED_MODE_NUM,
};
#define NETXBIG_LED_INVALID_MODE NETXBIG_LED_MODE_NUM
struct netxbig_led_timer {
unsigned long delay_on;
unsigned long delay_off;
enum netxbig_led_mode mode;
};
struct netxbig_led {
const char *name;
const char *default_trigger;
int mode_addr;
int *mode_val;
int bright_addr;
};
struct netxbig_led_platform_data {
struct netxbig_gpio_ext *gpio_ext;
struct netxbig_led_timer *timer;
int num_timer;
struct netxbig_led *leds;
int num_leds;
};
#endif /* __MACH_LEDS_NETXBIG_H */

127
arch/arm/mach-kirkwood/lacie_v2-common.c Normal file
View File

@ -0,0 +1,127 @@
/*
* arch/arm/mach-kirkwood/lacie_v2-common.c
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/gpio.h>
#include <asm/mach/time.h>
#include <mach/kirkwood.h>
#include <mach/irqs.h>
#include <plat/time.h>
#include "common.h"
/*****************************************************************************
* 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
****************************************************************************/
static struct mtd_partition lacie_v2_flash_parts[] = {
{
.name = "u-boot",
.size = MTDPART_SIZ_FULL,
.offset = 0,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
};
static const struct flash_platform_data lacie_v2_flash = {
.type = "mx25l4005a",
.name = "spi_flash",
.parts = lacie_v2_flash_parts,
.nr_parts = ARRAY_SIZE(lacie_v2_flash_parts),
};
static struct spi_board_info __initdata lacie_v2_spi_slave_info[] = {
{
.modalias = "m25p80",
.platform_data = &lacie_v2_flash,
.irq = -1,
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 0,
},
};
void __init lacie_v2_register_flash(void)
{
spi_register_board_info(lacie_v2_spi_slave_info,
ARRAY_SIZE(lacie_v2_spi_slave_info));
kirkwood_spi_init();
}
/*****************************************************************************
* I2C devices
****************************************************************************/
static struct at24_platform_data at24c04 = {
.byte_len = SZ_4K / 8,
.page_size = 16,
};
/*
* i2c addr | chip | description
* 0x50 | HT24LC04 | eeprom (512B)
*/
static struct i2c_board_info __initdata lacie_v2_i2c_info[] = {
{
I2C_BOARD_INFO("24c04", 0x50),
.platform_data = &at24c04,
}
};
void __init lacie_v2_register_i2c_devices(void)
{
kirkwood_i2c_init();
i2c_register_board_info(0, lacie_v2_i2c_info,
ARRAY_SIZE(lacie_v2_i2c_info));
}
/*****************************************************************************
* Hard Disk power
****************************************************************************/
static int __initdata lacie_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
void __init lacie_v2_hdd_power_init(int hdd_num)
{
int i;
int err;
/* Power up all hard disks. */
for (i = 0; i < hdd_num; i++) {
err = gpio_request(lacie_v2_gpio_hdd_power[i], NULL);
if (err == 0) {
err = gpio_direction_output(
lacie_v2_gpio_hdd_power[i], 1);
/* Free the HDD power GPIOs. This allow user-space to
* configure them via the gpiolib sysfs interface. */
gpio_free(lacie_v2_gpio_hdd_power[i]);
}
if (err)
pr_err("Failed to power up HDD%d\n", i + 1);
}
}
/*****************************************************************************
* Timer
****************************************************************************/
static void lacie_v2_timer_init(void)
{
kirkwood_tclk = 166666667;
orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
struct sys_timer lacie_v2_timer = {
.init = lacie_v2_timer_init,
};

18
arch/arm/mach-kirkwood/lacie_v2-common.h Normal file
View File

@ -0,0 +1,18 @@
/*
* arch/arm/mach-kirkwood/lacie_v2-common.h
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
#define __ARCH_KIRKWOOD_LACIE_V2_COMMON_H
void lacie_v2_register_flash(void);
void lacie_v2_register_i2c_devices(void);
void lacie_v2_hdd_power_init(int hdd_num);
extern struct sys_timer lacie_v2_timer;
#endif

122
arch/arm/mach-kirkwood/netspace_v2-setup.c
View File

@ -24,56 +24,19 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/kirkwood.h>
#include <mach/leds-ns2.h>
#include <plat/time.h>
#include "common.h"
#include "mpp.h"
/*****************************************************************************
* 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
****************************************************************************/
static struct mtd_partition netspace_v2_flash_parts[] = {
{
.name = "u-boot",
.size = MTDPART_SIZ_FULL,
.offset = 0,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
};
static const struct flash_platform_data netspace_v2_flash = {
.type = "mx25l4005a",
.name = "spi_flash",
.parts = netspace_v2_flash_parts,
.nr_parts = ARRAY_SIZE(netspace_v2_flash_parts),
};
static struct spi_board_info __initdata netspace_v2_spi_slave_info[] = {
{
.modalias = "m25p80",
.platform_data = &netspace_v2_flash,
.irq = -1,
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 0,
},
};
#include "lacie_v2-common.h"
/*****************************************************************************
* Ethernet
@ -83,27 +46,6 @@ static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(8),
};
/*****************************************************************************
* I2C devices
****************************************************************************/
static struct at24_platform_data at24c04 = {
.byte_len = SZ_4K / 8,
.page_size = 16,
};
/*
* i2c addr | chip | description
* 0x50 | HT24LC04 | eeprom (512B)
*/
static struct i2c_board_info __initdata netspace_v2_i2c_info[] = {
{
I2C_BOARD_INFO("24c04", 0x50),
.platform_data = &at24c04,
}
};
/*****************************************************************************
* SATA
****************************************************************************/
@ -112,35 +54,6 @@ static struct mv_sata_platform_data netspace_v2_sata_data = {
.n_ports = 2,
};
#define NETSPACE_V2_GPIO_SATA0_POWER 16
#define NETSPACE_V2_GPIO_SATA1_POWER 17
static void __init netspace_v2_sata_power_init(void)
{
int err;
err = gpio_request(NETSPACE_V2_GPIO_SATA0_POWER, "SATA0 power");
if (err == 0) {
err = gpio_direction_output(NETSPACE_V2_GPIO_SATA0_POWER, 1);
if (err)
gpio_free(NETSPACE_V2_GPIO_SATA0_POWER);
}
if (err)
pr_err("netspace_v2: failed to setup SATA0 power\n");
if (machine_is_netspace_max_v2()) {
err = gpio_request(NETSPACE_V2_GPIO_SATA1_POWER, "SATA1 power");
if (err == 0) {
err = gpio_direction_output(
NETSPACE_V2_GPIO_SATA1_POWER, 1);
if (err)
gpio_free(NETSPACE_V2_GPIO_SATA1_POWER);
}
if (err)
pr_err("netspace_v2: failed to setup SATA1 power\n");
}
}
/*****************************************************************************
* GPIO keys
****************************************************************************/
@ -223,20 +136,6 @@ static struct platform_device netspace_v2_leds = {
},
};
/*****************************************************************************
* Timer
****************************************************************************/
static void netspace_v2_timer_init(void)
{
kirkwood_tclk = 166666667;
orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
struct sys_timer netspace_v2_timer = {
.init = netspace_v2_timer_init,
};
/*****************************************************************************
* General Setup
****************************************************************************/
@ -291,18 +190,17 @@ static void __init netspace_v2_init(void)
kirkwood_init();
kirkwood_mpp_conf(netspace_v2_mpp_config);
netspace_v2_sata_power_init();
if (machine_is_netspace_max_v2())
lacie_v2_hdd_power_init(2);
else
lacie_v2_hdd_power_init(1);
kirkwood_ehci_init();
kirkwood_ge00_init(&netspace_v2_ge00_data);
kirkwood_sata_init(&netspace_v2_sata_data);
kirkwood_uart0_init();
spi_register_board_info(netspace_v2_spi_slave_info,
ARRAY_SIZE(netspace_v2_spi_slave_info));
kirkwood_spi_init();
kirkwood_i2c_init();
i2c_register_board_info(0, netspace_v2_i2c_info,
ARRAY_SIZE(netspace_v2_i2c_info));
lacie_v2_register_flash();
lacie_v2_register_i2c_devices();
platform_device_register(&netspace_v2_leds);
platform_device_register(&netspace_v2_gpio_leds);
@ -323,7 +221,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &netspace_v2_timer,
.timer = &lacie_v2_timer,
MACHINE_END
#endif
@ -335,7 +233,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &netspace_v2_timer,
.timer = &lacie_v2_timer,
MACHINE_END
#endif
@ -347,6 +245,6 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
.init_machine = netspace_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &netspace_v2_timer,
.timer = &lacie_v2_timer,
MACHINE_END
#endif

269
arch/arm/mach-kirkwood/netxbig_v2-setup.c
View File

@ -23,55 +23,19 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/gpio_keys.h>
#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/kirkwood.h>
#include <plat/time.h>
#include <mach/leds-netxbig.h>
#include "common.h"
#include "mpp.h"
/*****************************************************************************
* 512KB SPI Flash on Boot Device (MACRONIX MX25L4005)
****************************************************************************/
static struct mtd_partition netxbig_v2_flash_parts[] = {
{
.name = "u-boot",
.size = MTDPART_SIZ_FULL,
.offset = 0,
.mask_flags = MTD_WRITEABLE, /* force read-only */
},
};
static const struct flash_platform_data netxbig_v2_flash = {
.type = "mx25l4005a",
.name = "spi_flash",
.parts = netxbig_v2_flash_parts,
.nr_parts = ARRAY_SIZE(netxbig_v2_flash_parts),
};
static struct spi_board_info __initdata netxbig_v2_spi_slave_info[] = {
{
.modalias = "m25p80",
.platform_data = &netxbig_v2_flash,
.irq = -1,
.max_speed_hz = 20000000,
.bus_num = 0,
.chip_select = 0,
},
};
#include "lacie_v2-common.h"
/*****************************************************************************
* Ethernet
@ -85,27 +49,6 @@ static struct mv643xx_eth_platform_data netxbig_v2_ge01_data = {
.phy_addr = MV643XX_ETH_PHY_ADDR(0),
};
/*****************************************************************************
* I2C devices
****************************************************************************/
static struct at24_platform_data at24c04 = {
.byte_len = SZ_4K / 8,
.page_size = 16,
};
/*
* i2c addr | chip | description
* 0x50 | HT24LC04 | eeprom (512B)
*/
static struct i2c_board_info __initdata netxbig_v2_i2c_info[] = {
{
I2C_BOARD_INFO("24c04", 0x50),
.platform_data = &at24c04,
}
};
/*****************************************************************************
* SATA
****************************************************************************/
@ -114,34 +57,6 @@ static struct mv_sata_platform_data netxbig_v2_sata_data = {
.n_ports = 2,
};
static int __initdata netxbig_v2_gpio_hdd_power[] = { 16, 17, 41, 42, 43 };
static void __init netxbig_v2_sata_power_init(void)
{
int i;
int err;
int hdd_nb;
if (machine_is_net2big_v2())
hdd_nb = 2;
else
hdd_nb = 5;
/* Power up all hard disks. */
for (i = 0; i < hdd_nb; i++) {
err = gpio_request(netxbig_v2_gpio_hdd_power[i], NULL);
if (err == 0) {
err = gpio_direction_output(
netxbig_v2_gpio_hdd_power[i], 1);
/* Free the HDD power GPIOs. This allow user-space to
* configure them via the gpiolib sysfs interface. */
gpio_free(netxbig_v2_gpio_hdd_power[i]);
}
if (err)
pr_err("netxbig_v2: failed to power up HDD%d\n", i + 1);
}
}
/*****************************************************************************
* GPIO keys
****************************************************************************/
@ -190,7 +105,7 @@ static struct platform_device netxbig_v2_gpio_buttons = {
};
/*****************************************************************************
* GPIO LEDs
* GPIO extension LEDs
****************************************************************************/
/*
@ -200,19 +115,32 @@ static struct platform_device netxbig_v2_gpio_buttons = {
* - address register : bit [0-2] -> GPIO [47-49]
* - data register : bit [0-2] -> GPIO [44-46]
* - enable register : GPIO 29
*
*/
static int netxbig_v2_gpio_ext_addr[] = { 47, 48, 49 };
static int netxbig_v2_gpio_ext_data[] = { 44, 45, 46 };
static struct netxbig_gpio_ext netxbig_v2_gpio_ext = {
.addr = netxbig_v2_gpio_ext_addr,
.num_addr = ARRAY_SIZE(netxbig_v2_gpio_ext_addr),
.data = netxbig_v2_gpio_ext_data,
.num_data = ARRAY_SIZE(netxbig_v2_gpio_ext_data),
.enable = 29,
};
/*
* Address register selection:
*
* addr | register
* ----------------------------
* 0 | front LED
* 1 | front LED brightness
* 2 | HDD LED brightness
* 3 | HDD1 LED
* 4 | HDD2 LED
* 5 | HDD3 LED
* 6 | HDD4 LED
* 7 | HDD5 LED
* 2 | SATA LED brightness
* 3 | SATA0 LED
* 4 | SATA1 LED
* 5 | SATA2 LED
* 6 | SATA3 LED
* 7 | SATA4 LED
*
* Data register configuration:
*
@ -233,30 +161,107 @@ static struct platform_device netxbig_v2_gpio_buttons = {
* 6 | blink blue on=1 sec and red on=1 sec
* 7 | blink blue on=0.5 sec and blue off=2.5 sec
*
* data | HDD LED mode
* data | SATA LED mode
* -------------------------------------------------
* 0 | fix blue on
* 0 | fix off
* 1 | SATA activity blink
* 2 | fix red on
* 3 | blink blue on=1 sec and blue off=1 sec
* 4 | blink red on=1 sec and red off=1 sec
* 5 | blink blue on=2.5 sec and red on=0.5 sec
* 6 | blink blue on=1 sec and red on=1 sec
* 7 | blink blue on=0.5 sec and blue off=2.5 sec
* 7 | fix blue on
*/
/*****************************************************************************
* Timer
****************************************************************************/
static int netxbig_v2_red_mled[NETXBIG_LED_MODE_NUM] = {
[NETXBIG_LED_OFF] = 0,
[NETXBIG_LED_ON] = 2,
[NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE,
[NETXBIG_LED_TIMER1] = 4,
[NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE,
};
static void netxbig_v2_timer_init(void)
{
kirkwood_tclk = 166666667;
orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
}
static int netxbig_v2_blue_pwr_mled[NETXBIG_LED_MODE_NUM] = {
[NETXBIG_LED_OFF] = 0,
[NETXBIG_LED_ON] = 1,
[NETXBIG_LED_SATA] = NETXBIG_LED_INVALID_MODE,
[NETXBIG_LED_TIMER1] = 3,
[NETXBIG_LED_TIMER2] = 7,
};
struct sys_timer netxbig_v2_timer = {
.init = netxbig_v2_timer_init,
static int netxbig_v2_blue_sata_mled[NETXBIG_LED_MODE_NUM] = {
[NETXBIG_LED_OFF] = 0,
[NETXBIG_LED_ON] = 7,
[NETXBIG_LED_SATA] = 1,
[NETXBIG_LED_TIMER1] = 3,
[NETXBIG_LED_TIMER2] = NETXBIG_LED_INVALID_MODE,
};
static struct netxbig_led_timer netxbig_v2_led_timer[] = {
[0] = {
.delay_on = 500,
.delay_off = 500,
.mode = NETXBIG_LED_TIMER1,
},
[1] = {
.delay_on = 500,
.delay_off = 1000,
.mode = NETXBIG_LED_TIMER2,
},
};
#define NETXBIG_LED(_name, maddr, mval, baddr) \
{ .name = _name, \
.mode_addr = maddr, \
.mode_val = mval, \
.bright_addr = baddr }
static struct netxbig_led net2big_v2_leds_ctrl[] = {
NETXBIG_LED("net2big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1),
NETXBIG_LED("net2big-v2:red:power", 0, netxbig_v2_red_mled, 1),
NETXBIG_LED("net2big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
NETXBIG_LED("net2big-v2:red:sata0", 3, netxbig_v2_red_mled, 2),
NETXBIG_LED("net2big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
NETXBIG_LED("net2big-v2:red:sata1", 4, netxbig_v2_red_mled, 2),
};
static struct netxbig_led_platform_data net2big_v2_leds_data = {
.gpio_ext = &netxbig_v2_gpio_ext,
.timer = netxbig_v2_led_timer,
.num_timer = ARRAY_SIZE(netxbig_v2_led_timer),
.leds = net2big_v2_leds_ctrl,
.num_leds = ARRAY_SIZE(net2big_v2_leds_ctrl),
};
static struct netxbig_led net5big_v2_leds_ctrl[] = {
NETXBIG_LED("net5big-v2:blue:power", 0, netxbig_v2_blue_pwr_mled, 1),
NETXBIG_LED("net5big-v2:red:power", 0, netxbig_v2_red_mled, 1),
NETXBIG_LED("net5big-v2:blue:sata0", 3, netxbig_v2_blue_sata_mled, 2),
NETXBIG_LED("net5big-v2:red:sata0", 3, netxbig_v2_red_mled, 2),
NETXBIG_LED("net5big-v2:blue:sata1", 4, netxbig_v2_blue_sata_mled, 2),
NETXBIG_LED("net5big-v2:red:sata1", 4, netxbig_v2_red_mled, 2),
NETXBIG_LED("net5big-v2:blue:sata2", 5, netxbig_v2_blue_sata_mled, 2),
NETXBIG_LED("net5big-v2:red:sata2", 5, netxbig_v2_red_mled, 2),
NETXBIG_LED("net5big-v2:blue:sata3", 6, netxbig_v2_blue_sata_mled, 2),
NETXBIG_LED("net5big-v2:red:sata3", 6, netxbig_v2_red_mled, 2),
NETXBIG_LED("net5big-v2:blue:sata4", 7, netxbig_v2_blue_sata_mled, 2),
NETXBIG_LED("net5big-v2:red:sata5", 7, netxbig_v2_red_mled, 2),
};
static struct netxbig_led_platform_data net5big_v2_leds_data = {
.gpio_ext = &netxbig_v2_gpio_ext,
.timer = netxbig_v2_led_timer,
.num_timer = ARRAY_SIZE(netxbig_v2_led_timer),
.leds = net5big_v2_leds_ctrl,
.num_leds = ARRAY_SIZE(net5big_v2_leds_ctrl),
};
static struct platform_device netxbig_v2_leds = {
.name = "leds-netxbig",
.id = -1,
.dev = {
.platform_data = &net2big_v2_leds_data,
},
};
/*****************************************************************************
@ -284,18 +289,18 @@ static unsigned int net2big_v2_mpp_config[] __initdata = {
MPP24_GPIO, /* USB mode select */
MPP26_GPIO, /* USB device vbus */
MPP28_GPIO, /* USB enable host vbus */
MPP29_GPIO, /* CPLD extension ALE */
MPP29_GPIO, /* GPIO extension ALE */
MPP34_GPIO, /* Rear Push button */
MPP35_GPIO, /* Inhibit switch power-off */
MPP36_GPIO, /* SATA HDD1 presence */
MPP37_GPIO, /* SATA HDD2 presence */
MPP40_GPIO, /* eSATA presence */
MPP44_GPIO, /* CPLD extension (data 0) */
MPP45_GPIO, /* CPLD extension (data 1) */
MPP46_GPIO, /* CPLD extension (data 2) */
MPP47_GPIO, /* CPLD extension (addr 0) */
MPP48_GPIO, /* CPLD extension (addr 1) */
MPP49_GPIO, /* CPLD extension (addr 2) */
MPP44_GPIO, /* GPIO extension (data 0) */
MPP45_GPIO, /* GPIO extension (data 1) */
MPP46_GPIO, /* GPIO extension (data 2) */
MPP47_GPIO, /* GPIO extension (addr 0) */
MPP48_GPIO, /* GPIO extension (addr 1) */
MPP49_GPIO, /* GPIO extension (addr 2) */
0
};
@ -324,7 +329,7 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
MPP26_GE1_RXD2,
MPP27_GE1_RXD3,
MPP28_GPIO, /* USB enable host vbus */
MPP29_GPIO, /* CPLD extension ALE */
MPP29_GPIO, /* GPIO extension ALE */
MPP30_GE1_RXCTL,
MPP31_GE1_RXCLK,
MPP32_GE1_TCLKOUT,
@ -339,12 +344,12 @@ static unsigned int net5big_v2_mpp_config[] __initdata = {
MPP41_GPIO, /* SATA HDD3 power */
MPP42_GPIO, /* SATA HDD4 power */
MPP43_GPIO, /* SATA HDD5 power */
MPP44_GPIO, /* CPLD extension (data 0) */
MPP45_GPIO, /* CPLD extension (data 1) */
MPP46_GPIO, /* CPLD extension (data 2) */
MPP47_GPIO, /* CPLD extension (addr 0) */
MPP48_GPIO, /* CPLD extension (addr 1) */
MPP49_GPIO, /* CPLD extension (addr 2) */
MPP44_GPIO, /* GPIO extension (data 0) */
MPP45_GPIO, /* GPIO extension (data 1) */
MPP46_GPIO, /* GPIO extension (data 2) */
MPP47_GPIO, /* GPIO extension (addr 0) */
MPP48_GPIO, /* GPIO extension (addr 1) */
MPP49_GPIO, /* GPIO extension (addr 2) */
0
};
@ -366,7 +371,10 @@ static void __init netxbig_v2_init(void)
else
kirkwood_mpp_conf(net5big_v2_mpp_config);
netxbig_v2_sata_power_init();
if (machine_is_net2big_v2())
lacie_v2_hdd_power_init(2);
else
lacie_v2_hdd_power_init(5);
kirkwood_ehci_init();
kirkwood_ge00_init(&netxbig_v2_ge00_data);
@ -374,13 +382,12 @@ static void __init netxbig_v2_init(void)
kirkwood_ge01_init(&netxbig_v2_ge01_data);
kirkwood_sata_init(&netxbig_v2_sata_data);
kirkwood_uart0_init();
spi_register_board_info(netxbig_v2_spi_slave_info,
ARRAY_SIZE(netxbig_v2_spi_slave_info));
kirkwood_spi_init();
kirkwood_i2c_init();
i2c_register_board_info(0, netxbig_v2_i2c_info,
ARRAY_SIZE(netxbig_v2_i2c_info));
lacie_v2_register_flash();
lacie_v2_register_i2c_devices();
if (machine_is_net5big_v2())
netxbig_v2_leds.dev.platform_data = &net5big_v2_leds_data;
platform_device_register(&netxbig_v2_leds);
platform_device_register(&netxbig_v2_gpio_buttons);
if (gpio_request(NETXBIG_V2_GPIO_POWER_OFF, "power-off") == 0 &&
@ -398,7 +405,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &netxbig_v2_timer,
.timer = &lacie_v2_timer,
MACHINE_END
#endif
@ -410,6 +417,6 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
.init_machine = netxbig_v2_init,
.map_io = kirkwood_map_io,
.init_irq = kirkwood_init_irq,
.timer = &netxbig_v2_timer,
.timer = &lacie_v2_timer,
MACHINE_END
#endif

101
arch/arm/mach-kirkwood/openrd-setup.c
View File

@ -16,6 +16,7 @@
#include <linux/ata_platform.h>
#include <linux/mv643xx_eth.h>
#include <linux/i2c.h>
#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/kirkwood.h>
@ -57,7 +58,22 @@ static struct mvsdio_platform_data openrd_mvsdio_data = {
};
static unsigned int openrd_mpp_config[] __initdata = {
MPP12_SD_CLK,
MPP13_SD_CMD,
MPP14_SD_D0,
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
MPP28_GPIO,
MPP29_GPIO,
MPP34_GPIO,
0
};
/* Configure MPP for UART1 */
static unsigned int openrd_uart1_mpp_config[] __initdata = {
MPP13_UART1_TXD,
MPP14_UART1_RXD,
0
};
@ -67,6 +83,68 @@ static struct i2c_board_info i2c_board_info[] __initdata = {
},
};
static int __initdata uart1;
static int __init sd_uart_selection(char *str)
{
uart1 = -EINVAL;
/* Default is SD. Change if required, for UART */
if (!str)
return 0;
if (!strncmp(str, "232", 3)) {
uart1 = 232;
} else if (!strncmp(str, "485", 3)) {
/* OpenRD-Base doesn't have RS485. Treat is as an
* unknown argument & just have default setting -
* which is SD */
if (machine_is_openrd_base()) {
uart1 = -ENODEV;
return 1;
}
uart1 = 485;
}
return 1;
}
/* Parse boot_command_line string kw_openrd_init_uart1=232/485 */
__setup("kw_openrd_init_uart1=", sd_uart_selection);
static int __init uart1_mpp_config(void)
{
kirkwood_mpp_conf(openrd_uart1_mpp_config);
if (gpio_request(34, "SD_UART1_SEL")) {
printk(KERN_ERR "GPIO request failed for SD/UART1 selection"
", gpio: 34\n");
return -EIO;
}
if (gpio_request(28, "RS232_RS485_SEL")) {
printk(KERN_ERR "GPIO request failed for RS232/RS485 selection"
", gpio# 28\n");
gpio_free(34);
return -EIO;
}
/* Select UART1
* Pin # 34: 0 => UART1, 1 => SD */
gpio_direction_output(34, 0);
/* Select RS232 OR RS485
* Pin # 28: 0 => RS232, 1 => RS485 */
if (uart1 == 232)
gpio_direction_output(28, 0);
else
gpio_direction_output(28, 1);
gpio_free(34);
gpio_free(28);
return 0;
}
static void __init openrd_init(void)
{
/*
@ -90,7 +168,6 @@ static void __init openrd_init(void)
kirkwood_ge01_init(&openrd_ge01_data);
kirkwood_sata_init(&openrd_sata_data);
kirkwood_sdio_init(&openrd_mvsdio_data);
kirkwood_i2c_init();
@ -99,6 +176,28 @@ static void __init openrd_init(void)
ARRAY_SIZE(i2c_board_info));
kirkwood_audio_init();
}
if (uart1 <= 0) {
if (uart1 < 0)
printk(KERN_ERR "Invalid kernel parameter to select "
"UART1. Defaulting to SD. ERROR CODE: %d\n",
uart1);
/* Select SD
* Pin # 34: 0 => UART1, 1 => SD */
if (gpio_request(34, "SD_UART1_SEL")) {
printk(KERN_ERR "GPIO request failed for SD/UART1 "
"selection, gpio: 34\n");
} else {
gpio_direction_output(34, 1);
gpio_free(34);
kirkwood_sdio_init(&openrd_mvsdio_data);
}
} else {
if (!uart1_mpp_config())
kirkwood_uart1_init();
}
}
static int __init openrd_pci_init(void)

7
arch/arm/mach-mmp/Kconfig
View File

@ -57,6 +57,13 @@ config MACH_MARVELL_JASPER
PXA910-based development board. Since MMP2 is compatible to
ARMv6 architecture.
config MACH_TETON_BGA
bool "Marvell's PXA168 Teton BGA Development Board"
select CPU_PXA168
help
Say 'Y' here if you want to support the Marvell PXA168-based
Teton BGA Development Board.
endmenu
config CPU_PXA168

1
arch/arm/mach-mmp/Makefile
View File

@ -17,3 +17,4 @@ obj-$(CONFIG_MACH_TAVOREVB) += tavorevb.o
obj-$(CONFIG_MACH_TTC_DKB) += ttc_dkb.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o

90
arch/arm/mach-mmp/aspenite.c
View File

@ -16,6 +16,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/nand.h>
#include <linux/interrupt.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -23,6 +24,9 @@
#include <mach/mfp-pxa168.h>
#include <mach/pxa168.h>
#include <mach/gpio.h>
#include <video/pxa168fb.h>
#include <linux/input.h>
#include <plat/pxa27x_keypad.h>
#include "common.h"
@ -66,6 +70,43 @@ static unsigned long common_pin_config[] __initdata = {
GPIO115_I2S_BCLK,
GPIO116_I2S_RXD,
GPIO117_I2S_TXD,
/* LCD */
GPIO56_LCD_FCLK_RD,
GPIO57_LCD_LCLK_A0,
GPIO58_LCD_PCLK_WR,
GPIO59_LCD_DENA_BIAS,
GPIO60_LCD_DD0,
GPIO61_LCD_DD1,
GPIO62_LCD_DD2,
GPIO63_LCD_DD3,
GPIO64_LCD_DD4,
GPIO65_LCD_DD5,
GPIO66_LCD_DD6,
GPIO67_LCD_DD7,
GPIO68_LCD_DD8,
GPIO69_LCD_DD9,
GPIO70_LCD_DD10,
GPIO71_LCD_DD11,
GPIO72_LCD_DD12,
GPIO73_LCD_DD13,
GPIO74_LCD_DD14,
GPIO75_LCD_DD15,
GPIO76_LCD_DD16,
GPIO77_LCD_DD17,
GPIO78_LCD_DD18,
GPIO79_LCD_DD19,
GPIO80_LCD_DD20,
GPIO81_LCD_DD21,
GPIO82_LCD_DD22,
GPIO83_LCD_DD23,
/* Keypad */
GPIO109_KP_MKIN1,
GPIO110_KP_MKIN0,
GPIO111_KP_MKOUT7,
GPIO112_KP_MKOUT6,
GPIO121_KP_MKIN4,
};
static struct smc91x_platdata smc91x_info = {
@ -134,6 +175,51 @@ static struct i2c_board_info aspenite_i2c_info[] __initdata = {
{ I2C_BOARD_INFO("wm8753", 0x1b), },
};
static struct fb_videomode video_modes[] = {
[0] = {
.pixclock = 30120,
.refresh = 60,
.xres = 800,
.yres = 480,
.hsync_len = 1,
.left_margin = 215,
.right_margin = 40,
.vsync_len = 1,
.upper_margin = 34,
.lower_margin = 10,
.sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
},
};
struct pxa168fb_mach_info aspenite_lcd_info = {
.id = "Graphic Frame",
.modes = video_modes,
.num_modes = ARRAY_SIZE(video_modes),
.pix_fmt = PIX_FMT_RGB565,
.io_pin_allocation_mode = PIN_MODE_DUMB_24,
.dumb_mode = DUMB_MODE_RGB888,
.active = 1,
.panel_rbswap = 0,
.invert_pixclock = 0,
};
static unsigned int aspenite_matrix_key_map[] = {
KEY(0, 6, KEY_UP), /* SW 4 */
KEY(0, 7, KEY_DOWN), /* SW 5 */
KEY(1, 6, KEY_LEFT), /* SW 6 */
KEY(1, 7, KEY_RIGHT), /* SW 7 */
KEY(4, 6, KEY_ENTER), /* SW 8 */
KEY(4, 7, KEY_ESC), /* SW 9 */
};
static struct pxa27x_keypad_platform_data aspenite_keypad_info __initdata = {
.matrix_key_rows = 5,
.matrix_key_cols = 8,
.matrix_key_map = aspenite_matrix_key_map,
.matrix_key_map_size = ARRAY_SIZE(aspenite_matrix_key_map),
.debounce_interval = 30,
};
static void __init common_init(void)
{
mfp_config(ARRAY_AND_SIZE(common_pin_config));
@ -143,6 +229,8 @@ static void __init common_init(void)
pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
pxa168_add_ssp(1);
pxa168_add_nand(&aspenite_nand_info);
pxa168_add_fb(&aspenite_lcd_info);
pxa168_add_keypad(&aspenite_keypad_info);
/* off-chip devices */
platform_device_register(&smc91x_device);
@ -152,6 +240,7 @@ MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
.phys_io = APB_PHYS_BASE,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = mmp_map_io,
.nr_irqs = IRQ_BOARD_START,
.init_irq = pxa168_init_irq,
.timer = &pxa168_timer,
.init_machine = common_init,
@ -161,6 +250,7 @@ MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
.phys_io = APB_PHYS_BASE,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = mmp_map_io,
.nr_irqs = IRQ_BOARD_START,
.init_irq = pxa168_init_irq,
.timer = &pxa168_timer,
.init_machine = common_init,

10
arch/arm/mach-mmp/common.c
View File

@ -10,13 +10,20 @@
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <asm/page.h>
#include <asm/mach/map.h>
#include <mach/addr-map.h>
#include <mach/cputype.h>
#include "common.h"
#define MMP_CHIPID (AXI_VIRT_BASE + 0x82c00)
unsigned int mmp_chip_id;
EXPORT_SYMBOL(mmp_chip_id);
static struct map_desc standard_io_desc[] __initdata = {
{
.pfn = __phys_to_pfn(APB_PHYS_BASE),
@ -34,4 +41,7 @@ static struct map_desc standard_io_desc[] __initdata = {
void __init mmp_map_io(void)
{
iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
/* this is early, initialize mmp_chip_id here */
mmp_chip_id = __raw_readl(MMP_CHIPID);
}

4
arch/arm/mach-mmp/flint.c
View File

@ -16,6 +16,7 @@
#include <linux/smc91x.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -25,6 +26,8 @@
#include "common.h"
#define FLINT_NR_IRQS (IRQ_BOARD_START + 48)
static unsigned long flint_pin_config[] __initdata = {
/* UART1 */
GPIO45_UART1_RXD,
@ -116,6 +119,7 @@ MACHINE_START(FLINT, "Flint Development Platform")
.phys_io = APB_PHYS_BASE,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = mmp_map_io,
.nr_irqs = FLINT_NR_IRQS,
.init_irq = mmp2_init_irq,
.timer = &mmp2_timer,
.init_machine = flint_init,

49
arch/arm/mach-mmp/include/mach/cputype.h
View File

@ -4,36 +4,51 @@
#include <asm/cputype.h>
/*
* CPU Stepping OLD_ID CPU_ID CHIP_ID
* CPU Stepping CPU_ID CHIP_ID
*
* PXA168 A0 0x41159263 0x56158400 0x00A0A333
* PXA910 Y0 0x41159262 0x56158000 0x00F0C910
* MMP2 Z0 0x560f5811
* PXA168 S0 0x56158400 0x0000C910
* PXA168 A0 0x56158400 0x00A0A168
* PXA910 Y1 0x56158400 0x00F2C920
* PXA910 A0 0x56158400 0x00F2C910
* PXA910 A1 0x56158400 0x00A0C910
* PXA920 Y0 0x56158400 0x00F2C920
* PXA920 A0 0x56158400 0x00A0C920
* PXA920 A1 0x56158400 0x00A1C920
* MMP2 Z0 0x560f5811 0x00F00410
* MMP2 Z1 0x560f5811 0x00E00410
* MMP2 A0 0x560f5811 0x00A0A610
*/
extern unsigned int mmp_chip_id;
#ifdef CONFIG_CPU_PXA168
# define __cpu_is_pxa168(id) \
({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x84; })
static inline int cpu_is_pxa168(void)
{
return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
((mmp_chip_id & 0xfff) == 0x168);
}
#else
# define __cpu_is_pxa168(id) (0)
#define cpu_is_pxa168() (0)
#endif
/* cpu_is_pxa910() is shared on both pxa910 and pxa920 */
#ifdef CONFIG_CPU_PXA910
# define __cpu_is_pxa910(id) \
({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x80; })
static inline int cpu_is_pxa910(void)
{
return (((read_cpuid_id() >> 8) & 0xff) == 0x84) &&
(((mmp_chip_id & 0xfff) == 0x910) ||
((mmp_chip_id & 0xfff) == 0x920));
}
#else
# define __cpu_is_pxa910(id) (0)
#define cpu_is_pxa910() (0)
#endif
#ifdef CONFIG_CPU_MMP2
# define __cpu_is_mmp2(id) \
({ unsigned int _id = ((id) >> 8) & 0xff; _id == 0x58; })
static inline int cpu_is_mmp2(void)
{
return (((cpu_readid_id() >> 8) & 0xff) == 0x58);
#else
# define __cpu_is_mmp2(id) (0)
#define cpu_is_mmp2() (0)
#endif
#define cpu_is_pxa168() ({ __cpu_is_pxa168(read_cpuid_id()); })
#define cpu_is_pxa910() ({ __cpu_is_pxa910(read_cpuid_id()); })
#define cpu_is_mmp2() ({ __cpu_is_mmp2(read_cpuid_id()); })
#endif /* __ASM_MACH_CPUTYPE_H */

4
arch/arm/mach-mmp/include/mach/irqs.h
View File

@ -222,10 +222,8 @@
#define IRQ_GPIO_NUM 192
#define IRQ_GPIO(x) (IRQ_GPIO_START + (x))
/* Board IRQ - 64 by default, increase if not enough */
#define IRQ_BOARD_START (IRQ_GPIO_START + IRQ_GPIO_NUM)
#define IRQ_BOARD_END (IRQ_BOARD_START + 64)
#define NR_IRQS (IRQ_BOARD_END)
#define NR_IRQS (IRQ_BOARD_START)
#endif /* __ASM_MACH_IRQS_H */

7
arch/arm/mach-mmp/include/mach/mfp-pxa168.h
View File

@ -289,4 +289,11 @@
#define GPIO86_PWM1_OUT MFP_CFG(GPIO86, AF2)
#define GPIO86_PWM2_OUT MFP_CFG(GPIO86, AF3)
/* Keypad */
#define GPIO109_KP_MKIN1 MFP_CFG(GPIO109, AF7)
#define GPIO110_KP_MKIN0 MFP_CFG(GPIO110, AF7)
#define GPIO111_KP_MKOUT7 MFP_CFG(GPIO111, AF7)
#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
#endif /* __ASM_MACH_MFP_PXA168_H */

20
arch/arm/mach-mmp/include/mach/pxa168.h
View File

@ -5,11 +5,15 @@ struct sys_timer;
extern struct sys_timer pxa168_timer;
extern void __init pxa168_init_irq(void);
extern void pxa168_clear_keypad_wakeup(void);
#include <linux/i2c.h>
#include <mach/devices.h>
#include <plat/i2c.h>
#include <plat/pxa3xx_nand.h>
#include <video/pxa168fb.h>
#include <plat/pxa27x_keypad.h>
#include <mach/cputype.h>
extern struct pxa_device_desc pxa168_device_uart1;
extern struct pxa_device_desc pxa168_device_uart2;
@ -25,6 +29,8 @@ extern struct pxa_device_desc pxa168_device_ssp3;
extern struct pxa_device_desc pxa168_device_ssp4;
extern struct pxa_device_desc pxa168_device_ssp5;
extern struct pxa_device_desc pxa168_device_nand;
extern struct pxa_device_desc pxa168_device_fb;
extern struct pxa_device_desc pxa168_device_keypad;
static inline int pxa168_add_uart(int id)
{
@ -97,4 +103,18 @@ static inline int pxa168_add_nand(struct pxa3xx_nand_platform_data *info)
{
return pxa_register_device(&pxa168_device_nand, info, sizeof(*info));
}
static inline int pxa168_add_fb(struct pxa168fb_mach_info *mi)
{
return pxa_register_device(&pxa168_device_fb, mi, sizeof(*mi));
}
static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
{
if (cpu_is_pxa168())
data->clear_wakeup_event = pxa168_clear_keypad_wakeup;
return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
}
#endif /* __ASM_MACH_PXA168_H */

12
arch/arm/mach-mmp/include/mach/regs-apmu.h
View File

@ -33,4 +33,16 @@
#define APMU_FNRST_DIS (1 << 1)
#define APMU_AXIRST_DIS (1 << 0)
/* Wake Clear Register */
#define APMU_WAKE_CLR APMU_REG(0x07c)
#define APMU_PXA168_KP_WAKE_CLR (1 << 7)
#define APMU_PXA168_CFI_WAKE_CLR (1 << 6)
#define APMU_PXA168_XD_WAKE_CLR (1 << 5)
#define APMU_PXA168_MSP_WAKE_CLR (1 << 4)
#define APMU_PXA168_SD4_WAKE_CLR (1 << 3)
#define APMU_PXA168_SD3_WAKE_CLR (1 << 2)
#define APMU_PXA168_SD2_WAKE_CLR (1 << 1)
#define APMU_PXA168_SD1_WAKE_CLR (1 << 0)
#endif /* __ASM_MACH_REGS_APMU_H */

27
arch/arm/mach-mmp/include/mach/teton_bga.h Normal file
View File

@ -0,0 +1,27 @@
/*
* linux/arch/arm/mach-mmp/include/mach/teton_bga.h
*
* Support for the Marvell PXA168 Teton BGA Development Platform.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#ifndef __ASM_MACH_TETON_BGA_H
#define __ASM_MACH_TETON_BGA_H
/* GPIOs */
#define MMC_PWENA_GPIO 27
#define USBHPENB_GPIO 55
#define RTC_INT_GPIO 78
#define LCD_VBLK_EN_GPIO 79
#define LCD_DVDD_EN_GPIO 80
#define RST_WIFI_GPIO 81
#define CF_PWEN_GPIO 82
#define USB_OC_GPIO 83
#define PWM_GPIO 84
#define USBHPENA_GPIO 85
#define TS_INT_GPIO 86
#define CIR_GPIO 108
#endif /* __ASM_MACH_TETON_BGA_H */

5
arch/arm/mach-mmp/jasper.c
View File

@ -18,16 +18,18 @@
#include <linux/regulator/machine.h>
#include <linux/regulator/max8649.h>
#include <linux/mfd/max8925.h>
#include <linux/interrupt.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/addr-map.h>
#include <mach/mfp-mmp2.h>
#include <mach/mmp2.h>
#include <mach/irqs.h>
#include "common.h"
#define JASPER_NR_IRQS (IRQ_BOARD_START + 48)
static unsigned long jasper_pin_config[] __initdata = {
/* UART1 */
GPIO29_UART1_RXD,
@ -137,6 +139,7 @@ MACHINE_START(MARVELL_JASPER, "Jasper Development Platform")
.phys_io = APB_PHYS_BASE,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = mmp_map_io,
.nr_irqs = JASPER_NR_IRQS,
.init_irq = mmp2_init_irq,
.timer = &mmp2_timer,
.init_machine = jasper_init,

16
arch/arm/mach-mmp/pxa168.c
View File

@ -77,8 +77,10 @@ static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
static APMU_CLK(nand, NAND, 0x01db, 208000000);
static APMU_CLK(lcd, LCD, 0x7f, 312000000);
/* device and clock bindings */
static struct clk_lookup pxa168_clkregs[] = {
@ -96,6 +98,8 @@ static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
};
static int __init pxa168_init(void)
@ -132,6 +136,16 @@ struct sys_timer pxa168_timer = {
.init = pxa168_timer_init,
};
void pxa168_clear_keypad_wakeup(void)
{
uint32_t val;
uint32_t mask = APMU_PXA168_KP_WAKE_CLR;
/* wake event clear is needed in order to clear keypad interrupt */
val = __raw_readl(APMU_WAKE_CLR);
__raw_writel(val | mask, APMU_WAKE_CLR);
}
/* on-chip devices */
PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
@ -147,3 +161,5 @@ PXA168_DEVICE(ssp2, "pxa168-ssp", 1, SSP2, 0xd401c000, 0x40, 54, 55);
PXA168_DEVICE(ssp3, "pxa168-ssp", 2, SSP3, 0xd401f000, 0x40, 56, 57);
PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);

91
arch/arm/mach-mmp/teton_bga.c Normal file
View File

@ -0,0 +1,91 @@
/*
* linux/arch/arm/mach-mmp/teton_bga.c
*
* Support for the Marvell PXA168 Teton BGA Development Platform.
*
* Author: Mark F. Brown <mark.brown314@gmail.com>
*
* This code is based on aspenite.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* publishhed by the Free Software Foundation.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/input.h>
#include <plat/pxa27x_keypad.h>
#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/addr-map.h>
#include <mach/mfp-pxa168.h>
#include <mach/pxa168.h>
#include <mach/teton_bga.h>
#include "common.h"
static unsigned long teton_bga_pin_config[] __initdata = {
/* UART1 */
GPIO107_UART1_TXD,
GPIO108_UART1_RXD,
/* Keypad */
GPIO109_KP_MKIN1,
GPIO110_KP_MKIN0,
GPIO111_KP_MKOUT7,
GPIO112_KP_MKOUT6,
/* I2C Bus */
GPIO105_CI2C_SDA,
GPIO106_CI2C_SCL,
/* RTC */
GPIO78_GPIO,
};
static unsigned int teton_bga_matrix_key_map[] = {
KEY(0, 6, KEY_ESC),
KEY(0, 7, KEY_ENTER),
KEY(1, 6, KEY_LEFT),
KEY(1, 7, KEY_RIGHT),
};
static struct pxa27x_keypad_platform_data teton_bga_keypad_info __initdata = {
.matrix_key_rows = 2,
.matrix_key_cols = 8,
.matrix_key_map = teton_bga_matrix_key_map,
.matrix_key_map_size = ARRAY_SIZE(teton_bga_matrix_key_map),
.debounce_interval = 30,
};
static struct i2c_board_info teton_bga_i2c_info[] __initdata = {
{
I2C_BOARD_INFO("ds1337", 0x68),
.irq = gpio_to_irq(RTC_INT_GPIO)
},
};
static void __init teton_bga_init(void)
{
mfp_config(ARRAY_AND_SIZE(teton_bga_pin_config));
/* on-chip devices */
pxa168_add_uart(1);
pxa168_add_keypad(&teton_bga_keypad_info);
pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(teton_bga_i2c_info));
}
MACHINE_START(TETON_BGA, "PXA168-based Teton BGA Development Platform")
.phys_io = APB_PHYS_BASE,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = mmp_map_io,
.nr_irqs = IRQ_BOARD_START,
.init_irq = pxa168_init_irq,
.timer = &pxa168_timer,
.init_machine = teton_bga_init,
MACHINE_END

4
arch/arm/mach-mmp/ttc_dkb.c
View File

@ -14,6 +14,7 @@
#include <linux/mtd/mtd.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/onenand.h>
#include <linux/interrupt.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@ -24,6 +25,8 @@
#include "common.h"
#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 24)
static unsigned long ttc_dkb_pin_config[] __initdata = {
/* UART2 */
GPIO47_UART2_RXD,
@ -125,6 +128,7 @@ MACHINE_START(TTC_DKB, "PXA910-based TTC_DKB Development Platform")
.phys_io = APB_PHYS_BASE,
.io_pg_offst = (APB_VIRT_BASE >> 18) & 0xfffc,
.map_io = mmp_map_io,
.nr_irqs = TTCDKB_NR_IRQS,
.init_irq = pxa910_init_irq,
.timer = &pxa910_timer,
.init_machine = ttc_dkb_init,

55
arch/arm/mach-msm/Kconfig
View File

@ -10,6 +10,8 @@ config ARCH_MSM7X00A
select MSM_SMD
select MSM_SMD_PKG3
select CPU_V6
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM7X30
bool "MSM7x30"
@ -18,6 +20,9 @@ config ARCH_MSM7X30
select MSM_VIC
select CPU_V7
select MSM_REMOTE_SPINLOCK_DEKKERS
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_QSD8X50
bool "QSD8X50"
@ -26,6 +31,19 @@ config ARCH_QSD8X50
select MSM_VIC
select CPU_V7
select MSM_REMOTE_SPINLOCK_LDREX
select MSM_GPIOMUX
select MSM_PROC_COMM
select HAS_MSM_DEBUG_UART_PHYS
config ARCH_MSM8X60
bool "MSM8X60"
select ARM_GIC
select CPU_V7
select MSM_V2_TLMM
select MSM_GPIOMUX
select MACH_MSM8X60_SURF if (!MACH_MSM8X60_RUMI3 && !MACH_MSM8X60_SIM \
&& !MACH_MSM8X60_FFA)
endchoice
config MSM_SOC_REV_A
@ -36,6 +54,9 @@ config ARCH_MSM_ARM11
config ARCH_MSM_SCORPION
bool
config HAS_MSM_DEBUG_UART_PHYS
bool
config MSM_VIC
bool
@ -74,6 +95,30 @@ config MACH_QSD8X50A_ST1_5
help
Support for the Qualcomm ST1.5.
config MACH_MSM8X60_RUMI3
depends on ARCH_MSM8X60
bool "MSM8x60 RUMI3"
help
Support for the Qualcomm MSM8x60 RUMI3 emulator.
config MACH_MSM8X60_SURF
depends on ARCH_MSM8X60
bool "MSM8x60 SURF"
help
Support for the Qualcomm MSM8x60 SURF eval board.
config MACH_MSM8X60_SIM
depends on ARCH_MSM8X60
bool "MSM8x60 Simulator"
help
Support for the Qualcomm MSM8x60 simulator.
config MACH_MSM8X60_FFA
depends on ARCH_MSM8X60
bool "MSM8x60 FFA"
help
Support for the Qualcomm MSM8x60 FFA eval board.
endmenu
config MSM_DEBUG_UART
@ -82,6 +127,7 @@ config MSM_DEBUG_UART
default 2 if MSM_DEBUG_UART2
default 3 if MSM_DEBUG_UART3
if HAS_MSM_DEBUG_UART_PHYS
choice
prompt "Debug UART"
@ -99,11 +145,20 @@ choice
config MSM_DEBUG_UART3
bool "UART3"
endchoice
endif
config MSM_SMD_PKG3
bool
config MSM_PROC_COMM
bool
config MSM_SMD
bool
config MSM_GPIOMUX
bool
config MSM_V2_TLMM
bool
endif

21
arch/arm/mach-msm/Makefile
View File

@ -1,16 +1,20 @@
obj-y += proc_comm.o
obj-y += io.o idle.o timer.o dma.o
obj-y += vreg.o
obj-y += io.o idle.o timer.o
ifndef CONFIG_ARCH_MSM8X60
obj-y += acpuclock-arm11.o
obj-y += clock.o clock-pcom.o
obj-y += gpio.o
obj-y += dma.o
endif
ifdef CONFIG_MSM_VIC
obj-y += irq-vic.o
else
ifndef CONFIG_ARCH_MSM8X60
obj-y += irq.o
endif
endif
obj-$(CONFIG_ARCH_MSM8X60) += clock-dummy.o iommu.o iommu_dev.o devices-msm8x60-iommu.o
obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
obj-$(CONFIG_MSM_PROC_COMM) += clock.o
obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
obj-$(CONFIG_MSM_SMD) += last_radio_log.o
@ -19,4 +23,11 @@ obj-$(CONFIG_MACH_TROUT) += board-trout.o board-trout-gpio.o board-trout-mmc.o d
obj-$(CONFIG_MACH_HALIBUT) += board-halibut.o devices-msm7x00.o
obj-$(CONFIG_ARCH_MSM7X30) += board-msm7x30.o devices-msm7x30.o
obj-$(CONFIG_ARCH_QSD8X50) += board-qsd8x50.o devices-qsd8x50.o
obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
ifndef CONFIG_MSM_V2_TLMM
obj-y += gpio.o
endif

22
arch/arm/mach-msm/board-msm7x30.c
View File

@ -39,27 +39,11 @@
extern struct sys_timer msm_timer;
#ifdef CONFIG_SERIAL_MSM_CONSOLE
static struct msm_gpio uart2_config_data[] = {
{ GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_RFR"},
{ GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_CTS"},
{ GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
{ GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
};
static void msm7x30_init_uart2(void)
{
msm_gpios_request_enable(uart2_config_data,
ARRAY_SIZE(uart2_config_data));
}
#endif
static struct platform_device *devices[] __initdata = {
#if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
&msm_device_uart2,
#endif
&msm_device_smd,
};
static void __init msm7x30_init_irq(void)
@ -70,10 +54,6 @@ static void __init msm7x30_init_irq(void)
static void __init msm7x30_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
#ifdef CONFIG_SERIAL_MSM_CONSOLE
msm7x30_init_uart2();
#endif
}
static void __init msm7x30_map_io(void)

100
arch/arm/mach-msm/board-msm8x60.c Normal file
View File

@ -0,0 +1,100 @@
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
void __iomem *gic_cpu_base_addr;
unsigned long clk_get_max_axi_khz(void)
{
return 0;
}
static void __init msm8x60_map_io(void)
{
msm_map_msm8x60_io();
}
static void __init msm8x60_init_irq(void)
{
unsigned int i;
gic_dist_init(0, MSM_QGIC_DIST_BASE, GIC_PPI_START);
gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
gic_cpu_init(0, MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
/* RUMI does not adhere to GIC spec by enabling STIs by default.
* Enable/clear is supposed to be RO for STIs, but is RW on RUMI.
*/
if (!machine_is_msm8x60_sim())
writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
* as they are configured as level, which does not play nice with
* handle_percpu_irq.
*/
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq);
}
}
static void __init msm8x60_init(void)
{
}
MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END
MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
.map_io = msm8x60_map_io,
.init_irq = msm8x60_init_irq,
.init_machine = msm8x60_init,
.timer = &msm_timer,
MACHINE_END

48
arch/arm/mach-msm/board-qsd8x50.c
View File

@ -35,21 +35,50 @@
extern struct sys_timer msm_timer;
static struct msm_gpio uart3_config_data[] = {
{ GPIO_CFG(86, 1, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Rx"},
{ GPIO_CFG(87, 1, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), "UART2_Tx"},
static const resource_size_t qsd8x50_surf_smc91x_base __initdata = 0x70000300;
static const unsigned qsd8x50_surf_smc91x_gpio __initdata = 156;
/* Leave smc91x resources empty here, as we'll fill them in
* at run-time: they vary from board to board, and the true
* configuration won't be known until boot.
*/
static struct resource smc91x_resources[] __initdata = {
[0] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device smc91x_device __initdata = {
.name = "smc91x",
.id = 0,
.num_resources = ARRAY_SIZE(smc91x_resources),
.resource = smc91x_resources,
};
static int __init msm_init_smc91x(void)
{
if (machine_is_qsd8x50_surf()) {
smc91x_resources[0].start = qsd8x50_surf_smc91x_base;
smc91x_resources[0].end = qsd8x50_surf_smc91x_base + 0xff;
smc91x_resources[1].start =
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
smc91x_resources[1].end =
gpio_to_irq(qsd8x50_surf_smc91x_gpio);
platform_device_register(&smc91x_device);
}
return 0;
}
module_init(msm_init_smc91x);
static struct platform_device *devices[] __initdata = {
&msm_device_uart3,
&msm_device_smd,
};
static void msm8x50_init_uart3(void)
{
msm_gpios_request_enable(uart3_config_data,
ARRAY_SIZE(uart3_config_data));
}
static void __init qsd8x50_map_io(void)
{
msm_map_qsd8x50_io();
@ -64,7 +93,6 @@ static void __init qsd8x50_init_irq(void)
static void __init qsd8x50_init(void)
{
msm8x50_init_uart3();
platform_add_devices(devices, ARRAY_SIZE(devices));
}

54
arch/arm/mach-msm/clock-dummy.c Normal file
View File

@ -0,0 +1,54 @@
/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
* 02110-1301, USA.
*
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/module.h>
struct clk *clk_get(struct device *dev, const char *id)
{
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
int clk_enable(struct clk *clk)
{
return -ENOENT;
}
EXPORT_SYMBOL(clk_enable);
void clk_disable(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_disable);
unsigned long clk_get_rate(struct clk *clk)
{
return 0;
}
EXPORT_SYMBOL(clk_get_rate);
int clk_set_rate(struct clk *clk, unsigned long rate)
{
return -ENOENT;
}
EXPORT_SYMBOL(clk_set_rate);
void clk_put(struct clk *clk)
{
}
EXPORT_SYMBOL(clk_put);

5
arch/arm/mach-msm/devices-msm7x30.c
View File

@ -51,6 +51,11 @@ struct platform_device msm_device_uart2 = {
.resource = resources_uart2,
};
struct platform_device msm_device_smd = {
.name = "msm_smd",
.id = -1,
};
struct clk msm_clocks_7x30[] = {
CLK_PCOM("adm_clk", ADM_CLK, NULL, 0),
CLK_PCOM("adsp_clk", ADSP_CLK, NULL, 0),

Some files were not shown because too many files have changed in this diff Show More