platform/x86/intel/pmc: Alder Lake PCH slp_s0_residency fix
[ Upstream commitfb5755100a
] For platforms with Alder Lake PCH (Alder Lake S and Raptor Lake S) the slp_s0_residency attribute has been reporting the wrong value. Unlike other platforms, ADL PCH does not have a counter for the time that the SLP_S0 signal was asserted. Instead, firmware uses the aggregate of the Low Power Mode (LPM) substate counters as the S0ix value. Since the LPM counters run at a different frequency, this lead to misreporting of the S0ix time. Add a check for Alder Lake PCH and adjust the frequency accordingly when display slp_s0_residency. Fixes:bbab31101f
("platform/x86/intel: pmc/core: Add Alderlake support to pmc core driver") Signed-off-by: Rajvi Jingar <rajvi.jingar@linux.intel.com> Signed-off-by: David E. Box <david.e.box@linux.intel.com> Reviewed-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20230320212029.3154407-1-david.e.box@linux.intel.com Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -958,6 +958,17 @@ static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int reg_offset,
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static inline u64 pmc_core_adjust_slp_s0_step(struct pmc_dev *pmcdev, u32 value)
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{
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/*
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* ADL PCH does not have the SLP_S0 counter and LPM Residency counters are
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* used as a workaround which uses 30.5 usec tick. All other client
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* programs have the legacy SLP_S0 residency counter that is using the 122
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* usec tick.
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*/
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const int lpm_adj_x2 = pmcdev->map->lpm_res_counter_step_x2;
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if (pmcdev->map == &adl_reg_map)
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return (u64)value * GET_X2_COUNTER((u64)lpm_adj_x2);
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else
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return (u64)value * pmcdev->map->slp_s0_res_counter_step;
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}
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