staging: ccree: simplify ioread/iowrite
Registers ioread/iowrite operations were done via macros, sometime using a "magical" implicit parameter. Replace all register access with simple inline macros. Signed-off-by: Gilad Ben-Yossef <gilad@benyossef.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Gilad Ben-Yossef
Greg Kroah-Hartman
parent
57a1f2a04a
commit
7f5ce9dddb
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@ -1,33 +0,0 @@
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/*
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* Copyright (C) 2012-2017 ARM Limited or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/* pseudo cc_hal.h for cc7x_perf_test_driver (to be able to include code from
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* CC drivers).
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*/
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#ifndef __CC_HAL_H__
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#define __CC_HAL_H__
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#include <linux/io.h>
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#define READ_REGISTER(_addr) ioread32((_addr))
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#define WRITE_REGISTER(_addr, _data) iowrite32((_data), (_addr))
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#define CC_HAL_WRITE_REGISTER(offset, val) \
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WRITE_REGISTER(cc_base + (offset), val)
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#define CC_HAL_READ_REGISTER(offset) READ_REGISTER(cc_base + (offset))
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#endif
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@ -1,35 +0,0 @@
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/*
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* Copyright (C) 2012-2017 ARM Limited or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*!
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* @file
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* @brief This file contains macro definitions for accessing ARM TrustZone
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* CryptoCell register space.
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*/
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#ifndef _CC_REGS_H_
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#define _CC_REGS_H_
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#include <linux/bitfield.h>
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#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
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DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
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DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
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/* Register name mangling macro */
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#define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET
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#endif /*_CC_REGS_H_*/
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@ -1,25 +0,0 @@
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/*
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* Copyright (C) 2012-2017 ARM Limited or its affiliates.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __DX_REG_BASE_HOST_H__
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#define __DX_REG_BASE_HOST_H__
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#define DX_BASE_CC 0x80000000
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#define DX_BASE_HOST_RGF 0x0UL
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#define DX_BASE_CRY_KERNEL 0x0UL
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#define DX_BASE_ROM 0x40000000
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#endif /*__DX_REG_BASE_HOST_H__*/
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@ -91,7 +91,6 @@ void dump_byte_array(const char *name, const u8 *buf, size_t len)
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static irqreturn_t cc_isr(int irq, void *dev_id)
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{
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struct ssi_drvdata *drvdata = (struct ssi_drvdata *)dev_id;
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void __iomem *cc_base = drvdata->cc_base;
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struct device *dev = drvdata_to_dev(drvdata);
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u32 irr;
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u32 imr;
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@ -99,22 +98,22 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
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/* STAT_OP_TYPE_GENERIC STAT_PHASE_0: Interrupt */
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/* read the interrupt status */
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irr = CC_HAL_READ_REGISTER(CC_REG(HOST_IRR));
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irr = cc_ioread(drvdata, CC_REG(HOST_IRR));
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dev_dbg(dev, "Got IRR=0x%08X\n", irr);
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if (unlikely(irr == 0)) { /* Probably shared interrupt line */
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dev_err(dev, "Got interrupt with empty IRR\n");
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return IRQ_NONE;
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}
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imr = CC_HAL_READ_REGISTER(CC_REG(HOST_IMR));
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imr = cc_ioread(drvdata, CC_REG(HOST_IMR));
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/* clear interrupt - must be before processing events */
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_ICR), irr);
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cc_iowrite(drvdata, CC_REG(HOST_ICR), irr);
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drvdata->irq = irr;
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/* Completion interrupt - most probable */
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if (likely((irr & SSI_COMP_IRQ_MASK) != 0)) {
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/* Mask AXI completion interrupt - will be unmasked in Deferred service handler */
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR), imr | SSI_COMP_IRQ_MASK);
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cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | SSI_COMP_IRQ_MASK);
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irr &= ~SSI_COMP_IRQ_MASK;
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complete_request(drvdata);
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}
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@ -122,7 +121,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
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/* TEE FIPS interrupt */
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if (likely((irr & SSI_GPR0_IRQ_MASK) != 0)) {
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/* Mask interrupt - will be unmasked in Deferred service handler */
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR), imr | SSI_GPR0_IRQ_MASK);
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cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | SSI_GPR0_IRQ_MASK);
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irr &= ~SSI_GPR0_IRQ_MASK;
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fips_handler(drvdata);
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}
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@ -132,7 +131,7 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
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u32 axi_err;
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/* Read the AXI error ID */
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axi_err = CC_HAL_READ_REGISTER(CC_REG(AXIM_MON_ERR));
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axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
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dev_dbg(dev, "AXI completion error: axim_mon_err=0x%08X\n",
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axi_err);
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@ -151,47 +150,44 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
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int init_cc_regs(struct ssi_drvdata *drvdata, bool is_probe)
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{
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unsigned int val, cache_params;
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void __iomem *cc_base = drvdata->cc_base;
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struct device *dev = drvdata_to_dev(drvdata);
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/* Unmask all AXI interrupt sources AXI_CFG1 register */
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val = CC_HAL_READ_REGISTER(CC_REG(AXIM_CFG));
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CC_HAL_WRITE_REGISTER(CC_REG(AXIM_CFG), val & ~SSI_AXI_IRQ_MASK);
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val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
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cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~SSI_AXI_IRQ_MASK);
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dev_dbg(dev, "AXIM_CFG=0x%08X\n",
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CC_HAL_READ_REGISTER(CC_REG(AXIM_CFG)));
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cc_ioread(drvdata, CC_REG(AXIM_CFG)));
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/* Clear all pending interrupts */
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val = CC_HAL_READ_REGISTER(CC_REG(HOST_IRR));
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val = cc_ioread(drvdata, CC_REG(HOST_IRR));
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dev_dbg(dev, "IRR=0x%08X\n", val);
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_ICR), val);
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cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
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/* Unmask relevant interrupt cause */
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val = (unsigned int)(~(SSI_COMP_IRQ_MASK | SSI_AXI_ERR_IRQ_MASK |
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SSI_GPR0_IRQ_MASK));
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR), val);
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cc_iowrite(drvdata, CC_REG(HOST_IMR), val);
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#ifdef DX_HOST_IRQ_TIMER_INIT_VAL_REG_OFFSET
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#ifdef DX_IRQ_DELAY
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/* Set CC IRQ delay */
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_IRQ_TIMER_INIT_VAL),
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DX_IRQ_DELAY);
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cc_iowrite(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL), DX_IRQ_DELAY);
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#endif
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if (CC_HAL_READ_REGISTER(CC_REG(HOST_IRQ_TIMER_INIT_VAL)) > 0) {
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if (cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL)) > 0) {
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dev_dbg(dev, "irq_delay=%d CC cycles\n",
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CC_HAL_READ_REGISTER(CC_REG(HOST_IRQ_TIMER_INIT_VAL)));
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cc_ioread(drvdata, CC_REG(HOST_IRQ_TIMER_INIT_VAL)));
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}
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#endif
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cache_params = (drvdata->coherent ? CC_COHERENT_CACHE_PARAMS : 0x0);
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val = CC_HAL_READ_REGISTER(CC_REG(AXIM_CACHE_PARAMS));
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val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
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if (is_probe)
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dev_info(dev, "Cache params previous: 0x%08X\n", val);
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CC_HAL_WRITE_REGISTER(CC_REG(AXIM_CACHE_PARAMS),
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cache_params);
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val = CC_HAL_READ_REGISTER(CC_REG(AXIM_CACHE_PARAMS));
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cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params);
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val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
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if (is_probe)
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dev_info(dev, "Cache params current: 0x%08X (expect: 0x%08X)\n",
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@ -280,7 +276,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
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}
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/* Verify correct mapping */
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signature_val = CC_HAL_READ_REGISTER(CC_REG(HOST_SIGNATURE));
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signature_val = cc_ioread(new_drvdata, CC_REG(HOST_SIGNATURE));
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if (signature_val != DX_DEV_SIGNATURE) {
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dev_err(dev, "Invalid CC signature: SIGNATURE=0x%08X != expected=0x%08X\n",
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signature_val, (u32)DX_DEV_SIGNATURE);
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@ -292,7 +288,7 @@ static int init_cc_resources(struct platform_device *plat_dev)
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/* Display HW versions */
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dev_info(dev, "ARM CryptoCell %s Driver: HW version 0x%08X, Driver version %s\n",
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SSI_DEV_NAME_STR,
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CC_HAL_READ_REGISTER(CC_REG(HOST_VERSION)),
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cc_ioread(new_drvdata, CC_REG(HOST_VERSION)),
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DRV_MODULE_VERSION);
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rc = init_cc_regs(new_drvdata, true);
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@ -410,8 +406,7 @@ post_clk_err:
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void fini_cc_regs(struct ssi_drvdata *drvdata)
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{
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/* Mask all interrupts */
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WRITE_REGISTER(drvdata->cc_base +
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CC_REG(HOST_IMR), 0xFFFFFFFF);
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cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF);
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}
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static void cleanup_cc_resources(struct platform_device *plat_dev)
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@ -40,11 +40,8 @@
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#include <linux/platform_device.h>
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/* Registers definitions from shared/hw/ree_include */
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#include "dx_reg_base_host.h"
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#include "dx_host.h"
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#include "cc_regs.h"
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#include "dx_reg_common.h"
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#include "cc_hal.h"
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#define CC_SUPPORT_SHA DX_DEV_SHA_MAX
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#include "cc_crypto_ctx.h"
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#include "ssi_sysfs.h"
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@ -73,6 +70,13 @@
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#define SSI_COMP_IRQ_MASK BIT(DX_HOST_IRR_AXIM_COMP_INT_BIT_SHIFT)
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#define AXIM_MON_COMP_VALUE GENMASK(DX_AXIM_MON_COMP_VALUE_BIT_SIZE + \
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DX_AXIM_MON_COMP_VALUE_BIT_SHIFT, \
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DX_AXIM_MON_COMP_VALUE_BIT_SHIFT)
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/* Register name mangling macro */
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#define CC_REG(reg_name) DX_ ## reg_name ## _REG_OFFSET
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/* TEE FIPS status interrupt */
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#define SSI_GPR0_IRQ_MASK BIT(DX_HOST_IRR_GPR0_BIT_SHIFT)
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@ -188,5 +192,15 @@ void fini_cc_regs(struct ssi_drvdata *drvdata);
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int cc_clk_on(struct ssi_drvdata *drvdata);
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void cc_clk_off(struct ssi_drvdata *drvdata);
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static inline void cc_iowrite(struct ssi_drvdata *drvdata, u32 reg, u32 val)
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{
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iowrite32(val, (drvdata->cc_base + reg));
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}
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static inline u32 cc_ioread(struct ssi_drvdata *drvdata, u32 reg)
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{
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return ioread32(drvdata->cc_base + reg);
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}
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#endif /*__SSI_DRIVER_H__*/
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@ -19,7 +19,6 @@
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#include "ssi_config.h"
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#include "ssi_driver.h"
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#include "cc_hal.h"
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#include "ssi_fips.h"
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static void fips_dsr(unsigned long devarg);
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@ -34,9 +33,8 @@ struct ssi_fips_handle {
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static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata)
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{
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u32 reg;
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void __iomem *cc_base = drvdata->cc_base;
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reg = CC_HAL_READ_REGISTER(CC_REG(GPR_HOST));
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reg = cc_ioread(drvdata, CC_REG(GPR_HOST));
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return (reg == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK));
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}
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@ -46,12 +44,11 @@ static bool cc_get_tee_fips_status(struct ssi_drvdata *drvdata)
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*/
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void cc_set_ree_fips_status(struct ssi_drvdata *drvdata, bool status)
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{
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void __iomem *cc_base = drvdata->cc_base;
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int val = CC_FIPS_SYNC_REE_STATUS;
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val |= (status ? CC_FIPS_SYNC_MODULE_OK : CC_FIPS_SYNC_MODULE_ERROR);
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_GPR0), val);
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cc_iowrite(drvdata, CC_REG(HOST_GPR0), val);
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}
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void ssi_fips_fini(struct ssi_drvdata *drvdata)
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@ -89,13 +86,12 @@ static void fips_dsr(unsigned long devarg)
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{
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struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg;
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struct device *dev = drvdata_to_dev(drvdata);
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void __iomem *cc_base = drvdata->cc_base;
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u32 irq, state, val;
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irq = (drvdata->irq & (SSI_GPR0_IRQ_MASK));
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if (irq) {
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state = CC_HAL_READ_REGISTER(CC_REG(GPR_HOST));
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state = cc_ioread(drvdata, CC_REG(GPR_HOST));
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if (state != (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK))
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tee_fips_error(dev);
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@ -105,7 +101,7 @@ static void fips_dsr(unsigned long devarg)
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* unmask AXI completion interrupt.
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*/
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val = (CC_REG(HOST_IMR) & ~irq);
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CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR), val);
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cc_iowrite(drvdata, CC_REG(HOST_IMR), val);
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}
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/* The function called once at driver entry point .*/
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@ -41,7 +41,7 @@ int ssi_power_mgr_runtime_suspend(struct device *dev)
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int rc;
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dev_dbg(dev, "set HOST_POWER_DOWN_EN\n");
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WRITE_REGISTER(drvdata->cc_base + CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE);
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cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_ENABLE);
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rc = ssi_request_mgr_runtime_suspend_queue(drvdata);
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if (rc != 0) {
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dev_err(dev, "ssi_request_mgr_runtime_suspend_queue (%x)\n",
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@ -60,7 +60,7 @@ int ssi_power_mgr_runtime_resume(struct device *dev)
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(struct ssi_drvdata *)dev_get_drvdata(dev);
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dev_dbg(dev, "unset HOST_POWER_DOWN_EN\n");
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WRITE_REGISTER(drvdata->cc_base + CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);
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cc_iowrite(drvdata, CC_REG(HOST_POWER_DOWN_EN), POWER_DOWN_DISABLE);
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rc = cc_clk_on(drvdata);
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if (rc) {
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@ -122,8 +122,8 @@ int request_mgr_init(struct ssi_drvdata *drvdata)
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dev_dbg(dev, "Initializing completion tasklet\n");
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tasklet_init(&req_mgr_h->comptask, comp_handler, (unsigned long)drvdata);
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#endif
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req_mgr_h->hw_queue_size = READ_REGISTER(drvdata->cc_base +
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CC_REG(DSCRPTR_QUEUE_SRAM_SIZE));
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req_mgr_h->hw_queue_size = cc_ioread(drvdata,
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CC_REG(DSCRPTR_QUEUE_SRAM_SIZE));
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dev_dbg(dev, "hw_queue_size=0x%08X\n", req_mgr_h->hw_queue_size);
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if (req_mgr_h->hw_queue_size < MIN_HW_QUEUE_SIZE) {
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dev_err(dev, "Invalid HW queue size = %u (Min. required is %u)\n",
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@ -197,12 +197,12 @@ static void request_mgr_complete(struct device *dev, void *dx_compl_h, void __io
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}
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static inline int request_mgr_queues_status_check(
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||||
struct device *dev,
|
||||
struct ssi_drvdata *drvdata,
|
||||
struct ssi_request_mgr_handle *req_mgr_h,
|
||||
void __iomem *cc_base,
|
||||
unsigned int total_seq_len)
|
||||
{
|
||||
unsigned long poll_queue;
|
||||
struct device *dev = drvdata_to_dev(drvdata);
|
||||
|
||||
/* SW queue is checked only once as it will not
|
||||
* be chaned during the poll becasue the spinlock_bh
|
||||
|
|
@ -222,7 +222,7 @@ static inline int request_mgr_queues_status_check(
|
|||
/* Wait for space in HW queue. Poll constant num of iterations. */
|
||||
for (poll_queue = 0; poll_queue < SSI_MAX_POLL_ITER ; poll_queue++) {
|
||||
req_mgr_h->q_free_slots =
|
||||
CC_HAL_READ_REGISTER(CC_REG(DSCRPTR_QUEUE_CONTENT));
|
||||
cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));
|
||||
if (unlikely(req_mgr_h->q_free_slots <
|
||||
req_mgr_h->min_free_hw_slots)) {
|
||||
req_mgr_h->min_free_hw_slots = req_mgr_h->q_free_slots;
|
||||
|
|
@ -288,7 +288,7 @@ int send_request(
|
|||
* in case iv gen add the max size and in case of no dout add 1
|
||||
* for the internal completion descriptor
|
||||
*/
|
||||
rc = request_mgr_queues_status_check(dev, req_mgr_h, cc_base,
|
||||
rc = request_mgr_queues_status_check(drvdata, req_mgr_h,
|
||||
max_required_seq_len);
|
||||
if (likely(rc == 0))
|
||||
/* There is enough place in the queue */
|
||||
|
|
@ -404,14 +404,13 @@ int send_request(
|
|||
int send_request_init(
|
||||
struct ssi_drvdata *drvdata, struct cc_hw_desc *desc, unsigned int len)
|
||||
{
|
||||
struct device *dev = drvdata_to_dev(drvdata);
|
||||
void __iomem *cc_base = drvdata->cc_base;
|
||||
struct ssi_request_mgr_handle *req_mgr_h = drvdata->request_mgr_handle;
|
||||
unsigned int total_seq_len = len; /*initial sequence length*/
|
||||
int rc = 0;
|
||||
|
||||
/* Wait for space in HW and SW FIFO. Poll for as much as FIFO_TIMEOUT. */
|
||||
rc = request_mgr_queues_status_check(dev, req_mgr_h, cc_base,
|
||||
rc = request_mgr_queues_status_check(drvdata, req_mgr_h,
|
||||
total_seq_len);
|
||||
if (unlikely(rc != 0))
|
||||
return rc;
|
||||
|
|
@ -422,7 +421,7 @@ int send_request_init(
|
|||
|
||||
/* Update the free slots in HW queue */
|
||||
req_mgr_h->q_free_slots =
|
||||
CC_HAL_READ_REGISTER(CC_REG(DSCRPTR_QUEUE_CONTENT));
|
||||
cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -486,7 +485,8 @@ static void proc_completions(struct ssi_drvdata *drvdata)
|
|||
|
||||
dev_info(dev, "Delay\n");
|
||||
for (i = 0; i < 1000000; i++)
|
||||
axi_err = READ_REGISTER(drvdata->cc_base + CC_REG(AXIM_MON_ERR));
|
||||
axi_err = cc_ioread(drvdata,
|
||||
CC_REG(AXIM_MON_ERR));
|
||||
}
|
||||
#endif /* COMPLETION_DELAY */
|
||||
|
||||
|
|
@ -507,20 +507,16 @@ static void proc_completions(struct ssi_drvdata *drvdata)
|
|||
}
|
||||
}
|
||||
|
||||
static inline u32 cc_axi_comp_count(void __iomem *cc_base)
|
||||
static inline u32 cc_axi_comp_count(struct ssi_drvdata *drvdata)
|
||||
{
|
||||
/* The CC_HAL_READ_REGISTER macro implictly requires and uses
|
||||
* a base MMIO register address variable named cc_base.
|
||||
*/
|
||||
return FIELD_GET(AXIM_MON_COMP_VALUE,
|
||||
CC_HAL_READ_REGISTER(CC_REG(AXIM_MON_COMP)));
|
||||
cc_ioread(drvdata, CC_REG(AXIM_MON_COMP)));
|
||||
}
|
||||
|
||||
/* Deferred service handler, run as interrupt-fired tasklet */
|
||||
static void comp_handler(unsigned long devarg)
|
||||
{
|
||||
struct ssi_drvdata *drvdata = (struct ssi_drvdata *)devarg;
|
||||
void __iomem *cc_base = drvdata->cc_base;
|
||||
struct ssi_request_mgr_handle *request_mgr_handle =
|
||||
drvdata->request_mgr_handle;
|
||||
|
||||
|
|
@ -529,12 +525,16 @@ static void comp_handler(unsigned long devarg)
|
|||
irq = (drvdata->irq & SSI_COMP_IRQ_MASK);
|
||||
|
||||
if (irq & SSI_COMP_IRQ_MASK) {
|
||||
/* To avoid the interrupt from firing as we unmask it, we clear it now */
|
||||
CC_HAL_WRITE_REGISTER(CC_REG(HOST_ICR), SSI_COMP_IRQ_MASK);
|
||||
/* To avoid the interrupt from firing as we unmask it,
|
||||
* we clear it now
|
||||
*/
|
||||
cc_iowrite(drvdata, CC_REG(HOST_ICR), SSI_COMP_IRQ_MASK);
|
||||
|
||||
/* Avoid race with above clear: Test completion counter once more */
|
||||
/* Avoid race with above clear: Test completion counter
|
||||
* once more
|
||||
*/
|
||||
request_mgr_handle->axi_completed +=
|
||||
cc_axi_comp_count(cc_base);
|
||||
cc_axi_comp_count(drvdata);
|
||||
|
||||
while (request_mgr_handle->axi_completed) {
|
||||
do {
|
||||
|
|
@ -543,20 +543,21 @@ static void comp_handler(unsigned long devarg)
|
|||
* request_mgr_handle->axi_completed is 0.
|
||||
*/
|
||||
request_mgr_handle->axi_completed =
|
||||
cc_axi_comp_count(cc_base);
|
||||
cc_axi_comp_count(drvdata);
|
||||
} while (request_mgr_handle->axi_completed > 0);
|
||||
|
||||
/* To avoid the interrupt from firing as we unmask it, we clear it now */
|
||||
CC_HAL_WRITE_REGISTER(CC_REG(HOST_ICR), SSI_COMP_IRQ_MASK);
|
||||
cc_iowrite(drvdata, CC_REG(HOST_ICR),
|
||||
SSI_COMP_IRQ_MASK);
|
||||
|
||||
/* Avoid race with above clear: Test completion counter once more */
|
||||
request_mgr_handle->axi_completed +=
|
||||
cc_axi_comp_count(cc_base);
|
||||
cc_axi_comp_count(drvdata);
|
||||
}
|
||||
}
|
||||
/* after verifing that there is nothing to do, Unmask AXI completion interrupt */
|
||||
CC_HAL_WRITE_REGISTER(CC_REG(HOST_IMR),
|
||||
CC_HAL_READ_REGISTER(CC_REG(HOST_IMR)) & ~irq);
|
||||
/* after verifing that there is nothing to do,
|
||||
* unmask AXI completion interrupt
|
||||
*/
|
||||
cc_iowrite(drvdata, CC_REG(HOST_IMR),
|
||||
cc_ioread(drvdata, CC_REG(HOST_IMR)) & ~irq);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
|||
|
|
@ -29,18 +29,17 @@ static ssize_t ssi_sys_regdump_show(struct kobject *kobj,
|
|||
{
|
||||
struct ssi_drvdata *drvdata = sys_get_drvdata();
|
||||
u32 register_value;
|
||||
void __iomem *cc_base = drvdata->cc_base;
|
||||
int offset = 0;
|
||||
|
||||
register_value = CC_HAL_READ_REGISTER(CC_REG(HOST_SIGNATURE));
|
||||
register_value = cc_ioread(drvdata, CC_REG(HOST_SIGNATURE));
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_SIGNATURE ", DX_HOST_SIGNATURE_REG_OFFSET, register_value);
|
||||
register_value = CC_HAL_READ_REGISTER(CC_REG(HOST_IRR));
|
||||
register_value = cc_ioread(drvdata, CC_REG(HOST_IRR));
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_IRR ", DX_HOST_IRR_REG_OFFSET, register_value);
|
||||
register_value = CC_HAL_READ_REGISTER(CC_REG(HOST_POWER_DOWN_EN));
|
||||
register_value = cc_ioread(drvdata, CC_REG(HOST_POWER_DOWN_EN));
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "HOST_POWER_DOWN_EN ", DX_HOST_POWER_DOWN_EN_REG_OFFSET, register_value);
|
||||
register_value = CC_HAL_READ_REGISTER(CC_REG(AXIM_MON_ERR));
|
||||
register_value = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "AXIM_MON_ERR ", DX_AXIM_MON_ERR_REG_OFFSET, register_value);
|
||||
register_value = CC_HAL_READ_REGISTER(CC_REG(DSCRPTR_QUEUE_CONTENT));
|
||||
register_value = cc_ioread(drvdata, CC_REG(DSCRPTR_QUEUE_CONTENT));
|
||||
offset += scnprintf(buf + offset, PAGE_SIZE - offset, "%s \t(0x%lX)\t 0x%08X\n", "DSCRPTR_QUEUE_CONTENT", DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET, register_value);
|
||||
return offset;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue