[ARM] 2889/1: S3C2410 - Add machine Anubis
Patch from Ben Dooks Add the Simtec Anubis to the list of supported machines in the arch/arm/mach-s3c2410 directory. This ensures the core peripherals are registered, the timer source is configured and the correct power-management is enabled. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This commit is contained in:
Ben Dooks
Russell King
parent
2be863c959
commit
7efb833d64
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@ -2,6 +2,13 @@ if ARCH_S3C2410
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menu "S3C24XX Implementations"
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config MACH_ANUBIS
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bool "Simtec Electronics ANUBIS"
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select CPU_S3C2440
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help
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Say Y gere if you are using the Simtec Electronics ANUBIS
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development system
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config ARCH_BAST
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bool "Simtec Electronics BAST (EB2410ITX)"
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select CPU_S3C2410
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@ -28,6 +28,7 @@ obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
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# machine specific support
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obj-$(CONFIG_MACH_ANUBIS) += mach-anubis.o
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obj-$(CONFIG_ARCH_BAST) += mach-bast.o usb-simtec.o
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obj-$(CONFIG_ARCH_H1940) += mach-h1940.o
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obj-$(CONFIG_MACH_N30) += mach-n30.o
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@ -0,0 +1,270 @@
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/* linux/arch/arm/mach-s3c2410/mach-anubis.c
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*
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* Copyright (c) 2003-2005 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Modifications:
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* 02-May-2005 BJD Copied from mach-bast.c
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/anubis-map.h>
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#include <asm/arch/anubis-irq.h>
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#include <asm/arch/anubis-cpld.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/arch/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-lcd.h>
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#include <asm/arch/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include "clock.h"
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#include "devs.h"
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#include "cpu.h"
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#define COPYRIGHT ", (c) 2005 Simtec Electronics"
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static struct map_desc anubis_iodesc[] __initdata = {
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/* ISA IO areas */
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{ (u32)S3C24XX_VA_ISA_BYTE, 0x0, SZ_16M, MT_DEVICE },
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{ (u32)S3C24XX_VA_ISA_WORD, 0x0, SZ_16M, MT_DEVICE },
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/* we could possibly compress the next set down into a set of smaller tables
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* pagetables, but that would mean using an L2 section, and it still means
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* we cannot actually feed the same register to an LDR due to 16K spacing
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*/
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/* CPLD control registers */
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{ (u32)ANUBIS_VA_CTRL1, ANUBIS_PA_CTRL1, SZ_4K, MT_DEVICE },
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{ (u32)ANUBIS_VA_CTRL2, ANUBIS_PA_CTRL2, SZ_4K, MT_DEVICE },
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/* IDE drives */
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{ (u32)ANUBIS_IDEPRI, S3C2410_CS3, SZ_1M, MT_DEVICE },
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{ (u32)ANUBIS_IDEPRIAUX, S3C2410_CS3+(1<<26), SZ_1M, MT_DEVICE },
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{ (u32)ANUBIS_IDESEC, S3C2410_CS4, SZ_1M, MT_DEVICE },
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{ (u32)ANUBIS_IDESECAUX, S3C2410_CS4+(1<<26), SZ_1M, MT_DEVICE },
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};
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#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
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[0] = {
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.name = "uclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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},
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[1] = {
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.name = "pclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0.
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}
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};
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static struct s3c2410_uartcfg anubis_uartcfgs[] = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clocks = anubis_serial_clocks,
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.clocks_size = ARRAY_SIZE(anubis_serial_clocks)
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},
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[1] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clocks = anubis_serial_clocks,
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.clocks_size = ARRAY_SIZE(anubis_serial_clocks)
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},
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};
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/* NAND Flash on Anubis board */
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static int external_map[] = { 2 };
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static int chip0_map[] = { 0 };
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static int chip1_map[] = { 1 };
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struct mtd_partition anubis_default_nand_part[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_16K,
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.offset = 0
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_16K,
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.offset = SZ_16K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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/* the Anubis has 3 selectable slots for nand-flash, the two
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* on-board chip areas, as well as the external slot.
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*
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* Note, there is no current hot-plug support for the External
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* socket.
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*/
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static struct s3c2410_nand_set anubis_nand_sets[] = {
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[1] = {
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.name = "External",
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.nr_chips = 1,
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.nr_map = external_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part
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},
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[0] = {
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.name = "chip0",
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.nr_chips = 1,
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.nr_map = chip0_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part
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},
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[2] = {
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.name = "chip1",
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.nr_chips = 1,
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.nr_map = chip1_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part
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},
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};
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static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
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{
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unsigned int tmp;
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slot = set->nr_map[slot] & 3;
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pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
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slot, set, set->nr_map);
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tmp = __raw_readb(ANUBIS_VA_CTRL1);
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tmp &= ~ANUBIS_CTRL1_NANDSEL;
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tmp |= slot;
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pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
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__raw_writeb(tmp, ANUBIS_VA_CTRL1);
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}
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static struct s3c2410_platform_nand anubis_nand_info = {
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.tacls = 25,
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.twrph0 = 80,
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.twrph1 = 80,
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.nr_sets = ARRAY_SIZE(anubis_nand_sets),
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.sets = anubis_nand_sets,
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.select_chip = anubis_nand_select,
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};
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/* Standard Anubis devices */
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static struct platform_device *anubis_devices[] __initdata = {
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&s3c_device_usb,
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&s3c_device_wdt,
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&s3c_device_adc,
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&s3c_device_i2c,
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&s3c_device_rtc,
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&s3c_device_nand,
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};
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static struct clk *anubis_clocks[] = {
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&s3c24xx_dclk0,
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&s3c24xx_dclk1,
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&s3c24xx_clkout0,
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&s3c24xx_clkout1,
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&s3c24xx_uclk,
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};
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static struct s3c24xx_board anubis_board __initdata = {
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.devices = anubis_devices,
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.devices_count = ARRAY_SIZE(anubis_devices),
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.clocks = anubis_clocks,
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.clocks_count = ARRAY_SIZE(anubis_clocks)
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};
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void __init anubis_map_io(void)
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{
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/* initialise the clocks */
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s3c24xx_dclk0.parent = NULL;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = NULL;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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s3c24xx_clkout1.parent = &s3c24xx_dclk1;
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s3c24xx_uclk.parent = &s3c24xx_clkout1;
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s3c_device_nand.dev.platform_data = &anubis_nand_info;
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s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
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s3c24xx_init_clocks(0);
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s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
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s3c24xx_set_board(&anubis_board);
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/* ensure that the GPIO is setup */
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s3c2410_gpio_setpin(S3C2410_GPA0, 1);
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}
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MACHINE_START(ANUBIS, "Simtec-Anubis")
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/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
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.phys_ram = S3C2410_SDRAM_PA,
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.phys_io = S3C2410_PA_UART,
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.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
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.boot_params = S3C2410_SDRAM_PA + 0x100,
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.map_io = anubis_map_io,
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.init_irq = s3c24xx_init_irq,
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.timer = &s3c24xx_timer,
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MACHINE_END
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@ -48,7 +48,7 @@ static __init int pm_simtec_init(void)
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/* check which machine we are running on */
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if (!machine_is_bast() && !machine_is_vr1000())
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if (!machine_is_bast() && !machine_is_vr1000() && !machine_is_anubis())
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return 0;
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printk(KERN_INFO "Simtec Board Power Manangement" COPYRIGHT "\n");
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@ -164,7 +164,7 @@ static void s3c2410_timer_setup (void)
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/* configure the system for whichever machine is in use */
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if (machine_is_bast() || machine_is_vr1000()) {
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if (machine_is_bast() || machine_is_vr1000() || machine_is_anubis()) {
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/* timer is at 12MHz, scaler is 1 */
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timer_usec_ticks = timer_mask_usec_ticks(1, 12000000);
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tcnt = 12000000 / HZ;
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@ -0,0 +1,24 @@
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/* linux/include/asm-arm/arch-s3c2410/anubis-cpld.h
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*
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* (c) 2005 Simtec Electronics
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* http://www.simtec.co.uk/products/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* ANUBIS - CPLD control constants
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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*
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*/
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#ifndef __ASM_ARCH_ANUBISCPLD_H
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#define __ASM_ARCH_ANUBISCPLD_H
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/* CTRL2 - NAND WP control, IDE Reset assert/check */
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#define ANUBIS_CTRL1_NANDSEL (0x3)
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#endif /* __ASM_ARCH_ANUBISCPLD_H */
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@ -0,0 +1,23 @@
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/* linux/include/asm-arm/arch-s3c2410/anubis-irq.h
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*
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* (c) 2005 Simtec Electronics
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* http://www.simtec.co.uk/products/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* ANUBIS - IRQ Number definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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*/
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#ifndef __ASM_ARCH_ANUBISIRQ_H
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#define __ASM_ARCH_ANUBISIRQ_H
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#define IRQ_IDE0 IRQ_EINT2
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#define IRQ_IDE1 IRQ_EINT3
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#define IRQ_ASIX IRQ_EINT1
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#endif /* __ASM_ARCH_ANUBISIRQ_H */
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@ -0,0 +1,46 @@
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/* linux/include/asm-arm/arch-s3c2410/anubis-map.h
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*
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* (c) 2005 Simtec Electronics
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* http://www.simtec.co.uk/products/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* ANUBIS - Memory map definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Changelog:
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*/
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/* needs arch/map.h including with this */
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#ifndef __ASM_ARCH_ANUBISMAP_H
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#define __ASM_ARCH_ANUBISMAP_H
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/* start peripherals off after the S3C2410 */
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#define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x02000000))
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#define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26))
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/* we put the CPLD registers next, to get them out of the way */
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#define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01300000 */
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#define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD)
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#define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01400000 */
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#define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD)
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#define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01500000 */
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#define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD)
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#define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01600000 */
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#define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD)
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#define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000)
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#define ANUBIS_IDEPRIAUX ANUBIS_IOADDR(0x01100000)
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#define ANUBIS_IDESEC ANUBIS_IOADDR(0x01200000)
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#define ANUBIS_IDESECAUX ANUBIS_IOADDR(0x01300000)
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#endif /* __ASM_ARCH_ANUBISMAP_H */
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