ie31200_edac: Introduce the driver
Add a driver for the E3-1200 series of Intel DRAM controllers, based on the following E3-1200 specs: http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200v3-vol-2-datasheet.html I've tested this on bad memory hardware, and observed correlating bad reads and uncorrected memory errors as reported by the driver. Tested against: CPU E3-1270 v3 @ 3.50GHz : 8086:0c08 (haswell) CPU E3-1270 V2 @ 3.50GHz : 8086:0158 (ivy bridge) CPU E31270 @ 3.40GHz : 8086:0108 (sandy bridge) Signed-off-by: Jason Baron <jbaron@akamai.com> Link: http://lkml.kernel.org/r/95c83e80dd40b5377e8bb206285c5d95ac623872.1403818526.git.jbaron@akamai.com [ Boris: realign defines ] Signed-off-by: Borislav Petkov <bp@suse.de>
This commit is contained in:
Jason Baron
Borislav Petkov
parent
a21e98ce1e
commit
7ee40b897d
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@ -186,6 +186,13 @@ config EDAC_I3200
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Support for error detection and correction on the Intel
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3200 and 3210 server chipsets.
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config EDAC_IE31200
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tristate "Intel e312xx"
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depends on EDAC_MM_EDAC && PCI && X86
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help
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Support for error detection and correction on the Intel
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E3-1200 based DRAM controllers.
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config EDAC_X38
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tristate "Intel X38"
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depends on EDAC_MM_EDAC && PCI && X86
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@ -37,6 +37,7 @@ obj-$(CONFIG_EDAC_I82875P) += i82875p_edac.o
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obj-$(CONFIG_EDAC_I82975X) += i82975x_edac.o
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obj-$(CONFIG_EDAC_I3000) += i3000_edac.o
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obj-$(CONFIG_EDAC_I3200) += i3200_edac.o
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obj-$(CONFIG_EDAC_IE31200) += ie31200_edac.o
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obj-$(CONFIG_EDAC_X38) += x38_edac.o
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obj-$(CONFIG_EDAC_I82860) += i82860_edac.o
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obj-$(CONFIG_EDAC_R82600) += r82600_edac.o
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@ -0,0 +1,541 @@
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/*
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* Intel E3-1200
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* Copyright (C) 2014 Jason Baron <jbaron@akamai.com>
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*
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* Support for the E3-1200 processor family. Heavily based on previous
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* Intel EDAC drivers.
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*
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* Since the DRAM controller is on the cpu chip, we can use its PCI device
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* id to identify these processors.
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*
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* PCI DRAM controller device ids (Taken from The PCI ID Repository - http://pci-ids.ucw.cz/)
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*
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* 0108: Xeon E3-1200 Processor Family DRAM Controller
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* 010c: Xeon E3-1200/2nd Generation Core Processor Family DRAM Controller
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* 0150: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
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* 0158: Xeon E3-1200 v2/Ivy Bridge DRAM Controller
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* 015c: Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller
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* 0c04: Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller
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* 0c08: Xeon E3-1200 v3 Processor DRAM Controller
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*
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* Based on Intel specification:
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* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e3-1200v3-vol-2-datasheet.pdf
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* http://www.intel.com/content/www/us/en/processors/xeon/xeon-e3-1200-family-vol-2-datasheet.html
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*
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* According to the above datasheet (p.16):
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* "
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* 6. Software must not access B0/D0/F0 32-bit memory-mapped registers with
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* requests that cross a DW boundary.
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* "
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*
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* Thus, we make use of the explicit: lo_hi_readq(), which breaks the readq into
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* 2 readl() calls. This restriction may be lifted in subsequent chip releases,
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* but lo_hi_readq() ensures that we are safe across all e3-1200 processors.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/pci_ids.h>
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#include <linux/edac.h>
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#include <asm-generic/io-64-nonatomic-lo-hi.h>
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#include "edac_core.h"
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#define IE31200_REVISION "1.0"
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#define EDAC_MOD_STR "ie31200_edac"
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#define ie31200_printk(level, fmt, arg...) \
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edac_printk(level, "ie31200", fmt, ##arg)
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_1 0x0108
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_2 0x010c
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_3 0x0150
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_4 0x0158
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_5 0x015c
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_6 0x0c04
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#define PCI_DEVICE_ID_INTEL_IE31200_HB_7 0x0c08
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#define IE31200_DIMMS 4
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#define IE31200_RANKS 8
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#define IE31200_RANKS_PER_CHANNEL 4
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#define IE31200_DIMMS_PER_CHANNEL 2
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#define IE31200_CHANNELS 2
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/* Intel IE31200 register addresses - device 0 function 0 - DRAM Controller */
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#define IE31200_MCHBAR_LOW 0x48
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#define IE31200_MCHBAR_HIGH 0x4c
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#define IE31200_MCHBAR_MASK GENMASK_ULL(38, 15)
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#define IE31200_MMR_WINDOW_SIZE BIT(15)
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/*
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* Error Status Register (16b)
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*
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* 15 reserved
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* 14 Isochronous TBWRR Run Behind FIFO Full
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* (ITCV)
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* 13 Isochronous TBWRR Run Behind FIFO Put
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* (ITSTV)
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* 12 reserved
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* 11 MCH Thermal Sensor Event
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* for SMI/SCI/SERR (GTSE)
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* 10 reserved
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* 9 LOCK to non-DRAM Memory Flag (LCKF)
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* 8 reserved
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* 7 DRAM Throttle Flag (DTF)
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* 6:2 reserved
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* 1 Multi-bit DRAM ECC Error Flag (DMERR)
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* 0 Single-bit DRAM ECC Error Flag (DSERR)
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*/
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#define IE31200_ERRSTS 0xc8
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#define IE31200_ERRSTS_UE BIT(1)
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#define IE31200_ERRSTS_CE BIT(0)
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#define IE31200_ERRSTS_BITS (IE31200_ERRSTS_UE | IE31200_ERRSTS_CE)
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/*
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* Channel 0 ECC Error Log (64b)
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*
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* 63:48 Error Column Address (ERRCOL)
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* 47:32 Error Row Address (ERRROW)
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* 31:29 Error Bank Address (ERRBANK)
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* 28:27 Error Rank Address (ERRRANK)
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* 26:24 reserved
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* 23:16 Error Syndrome (ERRSYND)
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* 15: 2 reserved
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* 1 Multiple Bit Error Status (MERRSTS)
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* 0 Correctable Error Status (CERRSTS)
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*/
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#define IE31200_C0ECCERRLOG 0x40c8
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#define IE31200_C1ECCERRLOG 0x44c8
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#define IE31200_ECCERRLOG_CE BIT(0)
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#define IE31200_ECCERRLOG_UE BIT(1)
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#define IE31200_ECCERRLOG_RANK_BITS GENMASK_ULL(28, 27)
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#define IE31200_ECCERRLOG_RANK_SHIFT 27
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#define IE31200_ECCERRLOG_SYNDROME_BITS GENMASK_ULL(23, 16)
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#define IE31200_ECCERRLOG_SYNDROME_SHIFT 16
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#define IE31200_ECCERRLOG_SYNDROME(log) \
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((log & IE31200_ECCERRLOG_SYNDROME_BITS) >> \
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IE31200_ECCERRLOG_SYNDROME_SHIFT)
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#define IE31200_CAPID0 0xe4
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#define IE31200_CAPID0_PDCD BIT(4)
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#define IE31200_CAPID0_DDPCD BIT(6)
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#define IE31200_CAPID0_ECC BIT(1)
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#define IE31200_MAD_DIMM_0_OFFSET 0x5004
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#define IE31200_MAD_DIMM_SIZE GENMASK_ULL(7, 0)
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#define IE31200_MAD_DIMM_A_RANK BIT(17)
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#define IE31200_MAD_DIMM_A_WIDTH BIT(19)
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#define IE31200_PAGES(n) (n << (28 - PAGE_SHIFT))
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static int nr_channels;
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struct ie31200_priv {
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void __iomem *window;
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};
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enum ie31200_chips {
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IE31200 = 0,
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};
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struct ie31200_dev_info {
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const char *ctl_name;
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};
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struct ie31200_error_info {
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u16 errsts;
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u16 errsts2;
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u64 eccerrlog[IE31200_CHANNELS];
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};
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static const struct ie31200_dev_info ie31200_devs[] = {
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[IE31200] = {
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.ctl_name = "IE31200"
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},
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};
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struct dimm_data {
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u8 size; /* in 256MB multiples */
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u8 dual_rank : 1,
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x16_width : 1; /* 0 means x8 width */
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};
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static int how_many_channels(struct pci_dev *pdev)
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{
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int n_channels;
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unsigned char capid0_2b; /* 2nd byte of CAPID0 */
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pci_read_config_byte(pdev, IE31200_CAPID0 + 1, &capid0_2b);
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/* check PDCD: Dual Channel Disable */
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if (capid0_2b & IE31200_CAPID0_PDCD) {
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edac_dbg(0, "In single channel mode\n");
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n_channels = 1;
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} else {
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edac_dbg(0, "In dual channel mode\n");
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n_channels = 2;
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}
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/* check DDPCD - check if both channels are filled */
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if (capid0_2b & IE31200_CAPID0_DDPCD)
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edac_dbg(0, "2 DIMMS per channel disabled\n");
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else
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edac_dbg(0, "2 DIMMS per channel enabled\n");
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return n_channels;
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}
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static bool ecc_capable(struct pci_dev *pdev)
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{
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unsigned char capid0_4b; /* 4th byte of CAPID0 */
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pci_read_config_byte(pdev, IE31200_CAPID0 + 3, &capid0_4b);
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if (capid0_4b & IE31200_CAPID0_ECC)
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return false;
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return true;
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}
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static int eccerrlog_row(int channel, u64 log)
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{
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int rank = ((log & IE31200_ECCERRLOG_RANK_BITS) >>
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IE31200_ECCERRLOG_RANK_SHIFT);
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return rank | (channel * IE31200_RANKS_PER_CHANNEL);
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}
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static void ie31200_clear_error_info(struct mem_ctl_info *mci)
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{
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/*
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* Clear any error bits.
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* (Yes, we really clear bits by writing 1 to them.)
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*/
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pci_write_bits16(to_pci_dev(mci->pdev), IE31200_ERRSTS,
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IE31200_ERRSTS_BITS, IE31200_ERRSTS_BITS);
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}
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static void ie31200_get_and_clear_error_info(struct mem_ctl_info *mci,
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struct ie31200_error_info *info)
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{
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struct pci_dev *pdev;
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struct ie31200_priv *priv = mci->pvt_info;
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void __iomem *window = priv->window;
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pdev = to_pci_dev(mci->pdev);
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/*
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* This is a mess because there is no atomic way to read all the
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* registers at once and the registers can transition from CE being
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* overwritten by UE.
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*/
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pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts);
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if (!(info->errsts & IE31200_ERRSTS_BITS))
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return;
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info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
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if (nr_channels == 2)
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info->eccerrlog[1] = lo_hi_readq(window + IE31200_C1ECCERRLOG);
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pci_read_config_word(pdev, IE31200_ERRSTS, &info->errsts2);
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/*
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* If the error is the same for both reads then the first set
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* of reads is valid. If there is a change then there is a CE
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* with no info and the second set of reads is valid and
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* should be UE info.
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*/
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if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
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info->eccerrlog[0] = lo_hi_readq(window + IE31200_C0ECCERRLOG);
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if (nr_channels == 2)
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info->eccerrlog[1] =
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lo_hi_readq(window + IE31200_C1ECCERRLOG);
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}
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ie31200_clear_error_info(mci);
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}
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static void ie31200_process_error_info(struct mem_ctl_info *mci,
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struct ie31200_error_info *info)
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{
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int channel;
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u64 log;
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if (!(info->errsts & IE31200_ERRSTS_BITS))
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return;
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if ((info->errsts ^ info->errsts2) & IE31200_ERRSTS_BITS) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
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-1, -1, -1, "UE overwrote CE", "");
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info->errsts = info->errsts2;
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}
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for (channel = 0; channel < nr_channels; channel++) {
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log = info->eccerrlog[channel];
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if (log & IE31200_ECCERRLOG_UE) {
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edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
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0, 0, 0,
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eccerrlog_row(channel, log),
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channel, -1,
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"ie31200 UE", "");
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} else if (log & IE31200_ECCERRLOG_CE) {
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
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0, 0,
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IE31200_ECCERRLOG_SYNDROME(log),
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eccerrlog_row(channel, log),
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channel, -1,
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"ie31200 CE", "");
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}
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}
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}
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static void ie31200_check(struct mem_ctl_info *mci)
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{
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struct ie31200_error_info info;
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edac_dbg(1, "MC%d\n", mci->mc_idx);
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ie31200_get_and_clear_error_info(mci, &info);
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ie31200_process_error_info(mci, &info);
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}
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static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev)
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{
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union {
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u64 mchbar;
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struct {
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u32 mchbar_low;
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u32 mchbar_high;
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};
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} u;
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void __iomem *window;
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pci_read_config_dword(pdev, IE31200_MCHBAR_LOW, &u.mchbar_low);
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pci_read_config_dword(pdev, IE31200_MCHBAR_HIGH, &u.mchbar_high);
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u.mchbar &= IE31200_MCHBAR_MASK;
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if (u.mchbar != (resource_size_t)u.mchbar) {
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ie31200_printk(KERN_ERR, "mmio space beyond accessible range (0x%llx)\n",
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(unsigned long long)u.mchbar);
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return NULL;
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}
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window = ioremap_nocache(u.mchbar, IE31200_MMR_WINDOW_SIZE);
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if (!window)
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ie31200_printk(KERN_ERR, "Cannot map mmio space at 0x%llx\n",
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(unsigned long long)u.mchbar);
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return window;
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}
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static int ie31200_probe1(struct pci_dev *pdev, int dev_idx)
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{
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int rc;
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int i, j;
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struct mem_ctl_info *mci = NULL;
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struct edac_mc_layer layers[2];
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struct dimm_data dimm_info[IE31200_CHANNELS][IE31200_DIMMS_PER_CHANNEL];
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void __iomem *window;
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struct ie31200_priv *priv;
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u32 addr_decode;
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edac_dbg(0, "MC:\n");
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if (!ecc_capable(pdev)) {
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ie31200_printk(KERN_INFO, "No ECC support\n");
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return -ENODEV;
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}
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window = ie31200_map_mchbar(pdev);
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if (!window)
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return -ENODEV;
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/* populate DIMM info */
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for (i = 0; i < IE31200_CHANNELS; i++) {
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addr_decode = readl(window + IE31200_MAD_DIMM_0_OFFSET +
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(i * 4));
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edac_dbg(0, "addr_decode: 0x%x\n", addr_decode);
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for (j = 0; j < IE31200_DIMMS_PER_CHANNEL; j++) {
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dimm_info[i][j].size = (addr_decode >> (j * 8)) &
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IE31200_MAD_DIMM_SIZE;
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dimm_info[i][j].dual_rank = (addr_decode &
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(IE31200_MAD_DIMM_A_RANK << j)) ? 1 : 0;
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dimm_info[i][j].x16_width = (addr_decode &
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(IE31200_MAD_DIMM_A_WIDTH << j)) ? 1 : 0;
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edac_dbg(0, "size: 0x%x, rank: %d, width: %d\n",
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dimm_info[i][j].size,
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dimm_info[i][j].dual_rank,
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dimm_info[i][j].x16_width);
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}
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}
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nr_channels = how_many_channels(pdev);
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layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
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layers[0].size = IE31200_DIMMS;
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layers[0].is_virt_csrow = true;
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layers[1].type = EDAC_MC_LAYER_CHANNEL;
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layers[1].size = nr_channels;
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layers[1].is_virt_csrow = false;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct ie31200_priv));
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rc = -ENOMEM;
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if (!mci)
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goto fail_unmap;
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||||
|
||||
edac_dbg(3, "MC: init mci\n");
|
||||
|
||||
mci->pdev = &pdev->dev;
|
||||
mci->mtype_cap = MEM_FLAG_DDR3;
|
||||
|
||||
mci->edac_ctl_cap = EDAC_FLAG_SECDED;
|
||||
mci->edac_cap = EDAC_FLAG_SECDED;
|
||||
|
||||
mci->mod_name = EDAC_MOD_STR;
|
||||
mci->mod_ver = IE31200_REVISION;
|
||||
mci->ctl_name = ie31200_devs[dev_idx].ctl_name;
|
||||
mci->dev_name = pci_name(pdev);
|
||||
mci->edac_check = ie31200_check;
|
||||
mci->ctl_page_to_phys = NULL;
|
||||
priv = mci->pvt_info;
|
||||
priv->window = window;
|
||||
|
||||
/*
|
||||
* The dram rank boundary (DRB) reg values are boundary addresses
|
||||
* for each DRAM rank with a granularity of 64MB. DRB regs are
|
||||
* cumulative; the last one will contain the total memory
|
||||
* contained in all ranks.
|
||||
*/
|
||||
for (i = 0; i < IE31200_DIMMS_PER_CHANNEL; i++) {
|
||||
for (j = 0; j < IE31200_CHANNELS; j++) {
|
||||
struct dimm_info *dimm;
|
||||
unsigned long nr_pages;
|
||||
|
||||
nr_pages = IE31200_PAGES(dimm_info[j][i].size);
|
||||
if (nr_pages == 0)
|
||||
continue;
|
||||
|
||||
if (dimm_info[j][i].dual_rank) {
|
||||
nr_pages = nr_pages / 2;
|
||||
dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
|
||||
mci->n_layers, (i * 2) + 1,
|
||||
j, 0);
|
||||
dimm->nr_pages = nr_pages;
|
||||
edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
|
||||
dimm->grain = 8; /* just a guess */
|
||||
dimm->mtype = MEM_DDR3;
|
||||
dimm->dtype = DEV_UNKNOWN;
|
||||
dimm->edac_mode = EDAC_UNKNOWN;
|
||||
}
|
||||
dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
|
||||
mci->n_layers, i * 2, j, 0);
|
||||
dimm->nr_pages = nr_pages;
|
||||
edac_dbg(0, "set nr pages: 0x%lx\n", nr_pages);
|
||||
dimm->grain = 8; /* same guess */
|
||||
dimm->mtype = MEM_DDR3;
|
||||
dimm->dtype = DEV_UNKNOWN;
|
||||
dimm->edac_mode = EDAC_UNKNOWN;
|
||||
}
|
||||
}
|
||||
|
||||
ie31200_clear_error_info(mci);
|
||||
|
||||
rc = -ENODEV;
|
||||
if (edac_mc_add_mc(mci)) {
|
||||
edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
|
||||
goto fail_free;
|
||||
}
|
||||
|
||||
/* get this far and it's successful */
|
||||
edac_dbg(3, "MC: success\n");
|
||||
return 0;
|
||||
|
||||
fail_free:
|
||||
if (mci)
|
||||
edac_mc_free(mci);
|
||||
fail_unmap:
|
||||
iounmap(window);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int ie31200_init_one(struct pci_dev *pdev,
|
||||
const struct pci_device_id *ent)
|
||||
{
|
||||
edac_dbg(0, "MC:\n");
|
||||
|
||||
if (pci_enable_device(pdev) < 0)
|
||||
return -EIO;
|
||||
|
||||
return ie31200_probe1(pdev, ent->driver_data);
|
||||
}
|
||||
|
||||
static void ie31200_remove_one(struct pci_dev *pdev)
|
||||
{
|
||||
struct mem_ctl_info *mci;
|
||||
struct ie31200_priv *priv;
|
||||
|
||||
edac_dbg(0, "\n");
|
||||
mci = edac_mc_del_mc(&pdev->dev);
|
||||
if (!mci)
|
||||
return;
|
||||
priv = mci->pvt_info;
|
||||
iounmap(priv->window);
|
||||
edac_mc_free(mci);
|
||||
}
|
||||
|
||||
static const struct pci_device_id ie31200_pci_tbl[] = {
|
||||
{
|
||||
PCI_VEND_DEV(INTEL, IE31200_HB_1), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
IE31200},
|
||||
{
|
||||
PCI_VEND_DEV(INTEL, IE31200_HB_2), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
IE31200},
|
||||
{
|
||||
PCI_VEND_DEV(INTEL, IE31200_HB_3), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
IE31200},
|
||||
{
|
||||
PCI_VEND_DEV(INTEL, IE31200_HB_4), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
IE31200},
|
||||
{
|
||||
PCI_VEND_DEV(INTEL, IE31200_HB_5), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
IE31200},
|
||||
{
|
||||
PCI_VEND_DEV(INTEL, IE31200_HB_6), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
IE31200},
|
||||
{
|
||||
PCI_VEND_DEV(INTEL, IE31200_HB_7), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
|
||||
IE31200},
|
||||
{
|
||||
0,
|
||||
} /* 0 terminated list. */
|
||||
};
|
||||
MODULE_DEVICE_TABLE(pci, ie31200_pci_tbl);
|
||||
|
||||
static struct pci_driver ie31200_driver = {
|
||||
.name = EDAC_MOD_STR,
|
||||
.probe = ie31200_init_one,
|
||||
.remove = ie31200_remove_one,
|
||||
.id_table = ie31200_pci_tbl,
|
||||
};
|
||||
|
||||
static int __init ie31200_init(void)
|
||||
{
|
||||
edac_dbg(3, "MC:\n");
|
||||
/* Ensure that the OPSTATE is set correctly for POLL or NMI */
|
||||
opstate_init();
|
||||
|
||||
return pci_register_driver(&ie31200_driver);
|
||||
}
|
||||
|
||||
static void __exit ie31200_exit(void)
|
||||
{
|
||||
edac_dbg(3, "MC:\n");
|
||||
pci_unregister_driver(&ie31200_driver);
|
||||
}
|
||||
|
||||
module_init(ie31200_init);
|
||||
module_exit(ie31200_exit);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Jason Baron <jbaron@akamai.com>");
|
||||
MODULE_DESCRIPTION("MC support for Intel Processor E31200 memory hub controllers");
|
||||
Loading…
Reference in New Issue