phy: miphy365x: Represent each PHY channel as a DT subnode
This has the added advantages of being able to enable/disable each of the channels as simply as enabling/disabling the DT node. Suggested-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
This commit is contained in:
Lee Jones
Kishon Vijay Abraham I
parent
6e877fedb1
commit
7ebdb52e19
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@ -18,6 +18,7 @@
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/of_address.h>
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#include <linux/clk.h>
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#include <linux/phy/phy.h>
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#include <linux/delay.h>
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@ -28,10 +29,8 @@
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#define HFC_TIMEOUT 100
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#define SYSCFG_2521 0x824
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#define SYSCFG_2522 0x828
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#define SYSCFG_PCIE_SATA_MASK BIT(1)
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#define SYSCFG_PCIE_SATA_POS 1
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#define SYSCFG_SELECT_SATA_MASK BIT(1)
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#define SYSCFG_SELECT_SATA_POS 1
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/* MiPHY365x register definitions */
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#define RESET_REG 0x00
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@ -136,25 +135,21 @@
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#define BIT_LOCK_LEVEL 0x01
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#define BIT_LOCK_CNT_512 (0x03 << 5)
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static u8 ports[] = { MIPHY_PORT_0, MIPHY_PORT_1 };
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struct miphy365x_phy {
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struct phy *phy;
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void __iomem *base;
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void __iomem *sata;
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void __iomem *pcie;
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bool pcie_tx_pol_inv;
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bool sata_tx_pol_inv;
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u32 sata_gen;
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u64 ctrlreg;
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u8 type;
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u8 port;
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};
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struct miphy365x_dev {
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struct device *dev;
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struct regmap *regmap;
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struct mutex miphy_mutex;
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struct miphy365x phys[ARRAY_SIZE(ports)];
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bool pcie_tx_pol_inv;
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bool sata_tx_pol_inv;
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u32 sata_gen;
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struct miphy365x_phy **phys;
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};
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/*
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@ -180,27 +175,12 @@ static u8 rx_tx_spd[] = {
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static int miphy365x_set_path(struct miphy365x_phy *miphy_phy,
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struct miphy365x_dev *miphy_dev)
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{
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u8 config = miphy_phy->type | miphy_phy->port;
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u32 mask = SYSCFG_PCIE_SATA_MASK;
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u32 reg;
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bool sata;
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bool sata = (miphy_phy->type == MIPHY_TYPE_SATA);
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switch (config) {
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case MIPHY_SATA_PORT0:
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reg = SYSCFG_2521;
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sata = true;
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break;
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case MIPHY_PCIE_PORT1:
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reg = SYSCFG_2522;
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sata = false;
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break;
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default:
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dev_err(miphy_dev->dev, "Configuration not supported\n");
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return -EINVAL;
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}
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return regmap_update_bits(miphy_dev->regmap, reg, mask,
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sata << SYSCFG_PCIE_SATA_POS);
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return regmap_update_bits(miphy_dev->regmap,
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(unsigned int)miphy_phy->ctrlreg,
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SYSCFG_SELECT_SATA_MASK,
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sata << SYSCFG_SELECT_SATA_POS);
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}
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static int miphy365x_init_pcie_port(struct miphy365x_phy *miphy_phy,
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@ -261,14 +241,14 @@ static inline void miphy365x_set_comp(struct miphy365x_phy *miphy_phy,
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{
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u8 val, mask;
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if (miphy_dev->sata_gen == SATA_GEN1)
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if (miphy_phy->sata_gen == SATA_GEN1)
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writeb_relaxed(COMP_2MHZ_RAT_GEN1,
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miphy_phy->base + COMP_CTRL2_REG);
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else
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writeb_relaxed(COMP_2MHZ_RAT,
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miphy_phy->base + COMP_CTRL2_REG);
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if (miphy_dev->sata_gen != SATA_GEN3) {
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if (miphy_phy->sata_gen != SATA_GEN3) {
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writeb_relaxed(COMSR_COMP_REF,
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miphy_phy->base + COMP_CTRL3_REG);
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/*
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@ -312,7 +292,7 @@ static inline void miphy365x_set_ssc(struct miphy365x_phy *miphy_phy,
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miphy_phy->base + PLL_SSC_PER_LSB_REG);
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/* SSC Settings complete */
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if (miphy_dev->sata_gen == SATA_GEN1) {
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if (miphy_phy->sata_gen == SATA_GEN1) {
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val = PLL_START_CAL | BUF_EN | SYNCHRO_TX | CONFIG_PLL;
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writeb_relaxed(val, miphy_phy->base + PLL_CTRL1_REG);
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} else {
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@ -334,7 +314,7 @@ static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
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val = RST_PLL | RST_PLL_CAL | RST_RX | RST_MACRO;
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writeb_relaxed(val, miphy_phy->base + RESET_REG);
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if (miphy_dev->sata_tx_pol_inv)
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if (miphy_phy->sata_tx_pol_inv)
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writeb_relaxed(TX_POL, miphy_phy->base + CTRL_REG);
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/*
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@ -344,7 +324,7 @@ static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
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*/
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writeb_relaxed(SPDSEL_SEL, miphy_phy->base + BOUNDARY1_REG);
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writeb_relaxed(START_CLK_HF, miphy_phy->base + IDLL_TEST_REG);
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val = rx_tx_spd[miphy_dev->sata_gen];
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val = rx_tx_spd[miphy_phy->sata_gen];
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writeb_relaxed(val, miphy_phy->base + BOUNDARY3_REG);
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/* Wait for HFC_READY = 0 */
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@ -355,7 +335,7 @@ static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
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/* Compensation Recalibration */
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miphy365x_set_comp(miphy_phy, miphy_dev);
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switch (miphy_dev->sata_gen) {
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switch (miphy_phy->sata_gen) {
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case SATA_GEN3:
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/*
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* TX Swing target 550-600mv peak to peak diff
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@ -423,7 +403,7 @@ static int miphy365x_init_sata_port(struct miphy365x_phy *miphy_phy,
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writeb_relaxed(0x00, miphy_phy->base + BOUNDARY1_REG);
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writeb_relaxed(0x00, miphy_phy->base + IDLL_TEST_REG);
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writeb_relaxed(RST_RX, miphy_phy->base + RESET_REG);
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val = miphy_dev->sata_tx_pol_inv ?
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val = miphy_phy->sata_tx_pol_inv ?
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(TX_POL | DES_BIT_LOCK_EN) : DES_BIT_LOCK_EN;
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writeb_relaxed(val, miphy_phy->base + CTRL_REG);
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@ -459,40 +439,95 @@ static int miphy365x_init(struct phy *phy)
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return ret;
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}
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int miphy365x_get_addr(struct device *dev, struct miphy365x_phy *miphy_phy,
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int index)
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{
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struct device_node *phynode = miphy_phy->phy->dev.of_node;
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const char *name;
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const __be32 *taddr;
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int type = miphy_phy->type;
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int ret;
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ret = of_property_read_string_index(phynode, "reg-names", index, &name);
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if (ret) {
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dev_err(dev, "no reg-names property not found\n");
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return ret;
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}
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if (!strncmp(name, "syscfg", 6)) {
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taddr = of_get_address(phynode, index, NULL, NULL);
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if (!taddr) {
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dev_err(dev, "failed to fetch syscfg address\n");
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return -EINVAL;
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}
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miphy_phy->ctrlreg = of_translate_address(phynode, taddr);
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if (miphy_phy->ctrlreg == OF_BAD_ADDR) {
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dev_err(dev, "failed to translate syscfg address\n");
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return -EINVAL;
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}
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return 0;
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}
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if (!((!strncmp(name, "sata", 4) && type == MIPHY_TYPE_SATA) ||
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(!strncmp(name, "pcie", 4) && type == MIPHY_TYPE_PCIE)))
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return 0;
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miphy_phy->base = of_iomap(phynode, index);
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if (!miphy_phy->base) {
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dev_err(dev, "Failed to map %s\n", phynode->full_name);
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return -EINVAL;
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}
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return 0;
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}
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static struct phy *miphy365x_xlate(struct device *dev,
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struct of_phandle_args *args)
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{
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struct miphy365x_dev *state = dev_get_drvdata(dev);
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u8 port, type;
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struct miphy365x_dev *miphy_dev = dev_get_drvdata(dev);
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struct miphy365x_phy *miphy_phy = NULL;
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struct device_node *phynode = args->np;
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int ret, index;
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if (args->count != 2) {
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if (!of_device_is_available(phynode)) {
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dev_warn(dev, "Requested PHY is disabled\n");
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return ERR_PTR(-ENODEV);
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}
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if (args->args_count != 1) {
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dev_err(dev, "Invalid number of cells in 'phy' property\n");
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return ERR_PTR(-EINVAL);
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}
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if (args->args[0] & 0xFFFFFF00 || args->args[1] & 0xFFFFFF00) {
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dev_err(dev, "Unsupported flags set in 'phy' property\n");
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for (index = 0; index < of_get_child_count(dev->of_node); index++)
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if (phynode == miphy_dev->phys[index]->phy->dev.of_node) {
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miphy_phy = miphy_dev->phys[index];
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break;
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}
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if (!miphy_phy) {
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dev_err(dev, "Failed to find appropriate phy\n");
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return ERR_PTR(-EINVAL);
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}
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port = args->args[0];
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type = args->args[1];
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miphy_phy->type = args->args[0];
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if (WARN_ON(port >= ARRAY_SIZE(ports)))
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return ERR_PTR(-EINVAL);
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if (type == MIPHY_TYPE_SATA)
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state->phys[port].base = state->phys[port].sata;
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else if (type == MIPHY_TYPE_PCIE)
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state->phys[port].base = state->phys[port].pcie;
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else {
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WARN(1, "Invalid type specified in DT");
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if (!(miphy_phy->type == MIPHY_TYPE_SATA ||
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miphy_phy->type == MIPHY_TYPE_PCIE)) {
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dev_err(dev, "Unsupported device type: %d\n", miphy_phy->type);
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return ERR_PTR(-EINVAL);
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}
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state->phys[port].type = type;
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/* Each port handles SATA and PCIE - third entry is always sysconf. */
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for (index = 0; index < 3; index++) {
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ret = miphy365x_get_addr(dev, miphy_phy, index);
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if (ret < 0)
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return ERR_PTR(ret);
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}
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return state->phys[port].phy;
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return miphy_phy->phy;
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}
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static struct phy_ops miphy365x_ops = {
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@ -500,95 +535,80 @@ static struct phy_ops miphy365x_ops = {
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.owner = THIS_MODULE,
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};
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static int miphy365x_get_base_addr(struct platform_device *pdev,
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struct miphy365x_phy *phy, u8 port)
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static int miphy365x_of_probe(struct device_node *phynode,
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struct miphy365x_phy *miphy_phy)
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{
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struct resource *res;
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char type[6];
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of_property_read_u32(phynode, "st,sata-gen", &miphy_phy->sata_gen);
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if (!miphy_phy->sata_gen)
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miphy_phy->sata_gen = SATA_GEN1;
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sprintf(type, "sata%d", port);
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miphy_phy->pcie_tx_pol_inv =
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of_property_read_bool(phynode, "st,pcie-tx-pol-inv");
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, type);
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phy->sata = devm_ioremap_resource(&pdev->dev, res));
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if (!phy->sata)
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return -ENOMEM;
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sprintf(type, "pcie%d", port);
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, type);
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phy->pcie = devm_ioremap_resource(&pdev->dev, res));
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if (!phy->pcie)
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return -ENOMEM;
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return 0;
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}
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static int miphy365x_of_probe(struct device_node *np,
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struct miphy365x_dev *phy_dev)
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{
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phy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
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if (IS_ERR(phy_dev->regmap)) {
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dev_err(phy_dev->dev, "No syscfg phandle specified\n");
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return PTR_ERR(phy_dev->regmap);
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}
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of_property_read_u32(np, "st,sata-gen", &phy_dev->sata_gen);
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if (!phy_dev->sata_gen)
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phy_dev->sata_gen = SATA_GEN1;
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phy_dev->pcie_tx_pol_inv =
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of_property_read_bool(np, "st,pcie-tx-pol-inv");
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phy_dev->sata_tx_pol_inv =
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of_property_read_bool(np, "st,sata-tx-pol-inv");
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miphy_phy->sata_tx_pol_inv =
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of_property_read_bool(phynode, "st,sata-tx-pol-inv");
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return 0;
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}
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static int miphy365x_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct miphy365x_dev *phy_dev;
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struct device *dev = &pdev->dev;
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struct device_node *child, *np = pdev->dev.of_node;
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struct miphy365x_dev *miphy_dev;
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struct phy_provider *provider;
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u8 port;
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struct phy *phy;
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int chancount, port = 0;
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int ret;
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phy_dev = devm_kzalloc(dev, sizeof(*phy_dev), GFP_KERNEL);
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if (!phy_dev)
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miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL);
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if (!miphy_dev)
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return -ENOMEM;
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ret = miphy365x_of_probe(np, phy_dev);
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if (ret)
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return ret;
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chancount = of_get_child_count(np);
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miphy_dev->phys = devm_kzalloc(&pdev->dev, sizeof(phy) * chancount,
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GFP_KERNEL);
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if (!miphy_dev->phys)
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return -ENOMEM;
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phy_dev->dev = dev;
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miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
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if (IS_ERR(miphy_dev->regmap)) {
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dev_err(miphy_dev->dev, "No syscfg phandle specified\n");
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return PTR_ERR(miphy_dev->regmap);
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}
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dev_set_drvdata(dev, phy_dev);
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miphy_dev->dev = &pdev->dev;
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mutex_init(&phy_dev->miphy_mutex);
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dev_set_drvdata(&pdev->dev, miphy_dev);
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for (port = 0; port < ARRAY_SIZE(ports); port++) {
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struct phy *phy;
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mutex_init(&miphy_dev->miphy_mutex);
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phy = devm_phy_create(dev, &miphy365x_ops, NULL);
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for_each_child_of_node(np, child) {
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struct miphy365x_phy *miphy_phy;
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miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
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GFP_KERNEL);
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if (!miphy_phy)
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return -ENOMEM;
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miphy_dev->phys[port] = miphy_phy;
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phy = devm_phy_create(&pdev->dev, child, &miphy365x_ops, NULL);
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if (IS_ERR(phy)) {
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dev_err(dev, "failed to create PHY on port %d\n", port);
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dev_err(&pdev->dev, "failed to create PHY\n");
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return PTR_ERR(phy);
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}
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phy_dev->phys[port].phy = phy;
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phy_dev->phys[port].port = port;
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miphy_dev->phys[port]->phy = phy;
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ret = miphy365x_get_base_addr(pdev,
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&phy_dev->phys[port], port);
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ret = miphy365x_of_probe(child, miphy_phy);
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if (ret)
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return ret;
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phy_set_drvdata(phy, &phy_dev->phys[port]);
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phy_set_drvdata(phy, miphy_dev->phys[port]);
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port++;
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}
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provider = devm_of_phy_provider_register(dev, miphy365x_xlate);
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provider = devm_of_phy_provider_register(&pdev->dev, miphy365x_xlate);
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if (IS_ERR(provider))
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return PTR_ERR(provider);
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