igb: offer a PTP Hardware Clock instead of the timecompare method
This commit removes the legacy timecompare code from the igb driver and offers a tunable PHC instead. Signed-off-by: Richard Cochran <richardcochran@gmail.com> Tested-by: Aaron Brown <aaron.f.brown@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
This commit is contained in:
parent
d339b13316
commit
7ebae8177e
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@ -120,6 +120,17 @@ config IGB_DCA
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driver. DCA is a method for warming the CPU cache before data
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is used, with the intent of lessening the impact of cache misses.
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config IGB_PTP
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bool "PTP Hardware Clock (PHC)"
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default y
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depends on IGB && PTP_1588_CLOCK
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---help---
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Say Y here if you want to use PTP Hardware Clock (PHC) in the
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driver. Only the basic clock operations have been implemented.
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Every timestamp and clock read operations must consult the
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overflow counter to form a correct time value.
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config IGBVF
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tristate "Intel(R) 82576 Virtual Function Ethernet support"
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depends on PCI
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@ -35,3 +35,4 @@ obj-$(CONFIG_IGB) += igb.o
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igb-objs := igb_main.o igb_ethtool.o e1000_82575.o \
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e1000_mac.o e1000_nvm.o e1000_phy.o e1000_mbx.o
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igb-$(CONFIG_IGB_PTP) += igb_ptp.o
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@ -35,7 +35,6 @@
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#include "e1000_82575.h"
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#include <linux/clocksource.h>
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#include <linux/timecompare.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/bitops.h>
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@ -329,9 +328,6 @@ struct igb_adapter {
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/* OS defined structs */
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struct pci_dev *pdev;
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struct cyclecounter cycles;
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struct timecounter clock;
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struct timecompare compare;
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struct hwtstamp_config hwtstamp_config;
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spinlock_t stats64_lock;
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@ -386,7 +382,6 @@ struct igb_adapter {
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#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
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#define IGB_82576_TSYNC_SHIFT 19
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#define IGB_82580_TSYNC_SHIFT 24
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#define IGB_TS_HDR_LEN 16
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enum e1000_state_t {
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__IGB_TESTING,
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@ -422,7 +417,15 @@ extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
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extern bool igb_has_link(struct igb_adapter *adapter);
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extern void igb_set_ethtool_ops(struct net_device *);
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extern void igb_power_up_link(struct igb_adapter *);
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#ifdef CONFIG_IGB_PTP
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extern void igb_ptp_init(struct igb_adapter *adapter);
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extern void igb_ptp_remove(struct igb_adapter *adapter);
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extern void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
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struct skb_shared_hwtstamps *hwtstamps,
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u64 systim);
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#endif
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static inline s32 igb_reset_phy(struct e1000_hw *hw)
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{
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if (hw->phy.ops.reset)
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@ -114,7 +114,6 @@ static void igb_free_all_rx_resources(struct igb_adapter *);
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static void igb_setup_mrqc(struct igb_adapter *);
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static int igb_probe(struct pci_dev *, const struct pci_device_id *);
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static void __devexit igb_remove(struct pci_dev *pdev);
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static void igb_init_hw_timer(struct igb_adapter *adapter);
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static int igb_sw_init(struct igb_adapter *);
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static int igb_open(struct net_device *);
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static int igb_close(struct net_device *);
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@ -565,33 +564,6 @@ exit:
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return;
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}
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/**
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* igb_read_clock - read raw cycle counter (to be used by time counter)
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*/
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static cycle_t igb_read_clock(const struct cyclecounter *tc)
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{
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struct igb_adapter *adapter =
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container_of(tc, struct igb_adapter, cycles);
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struct e1000_hw *hw = &adapter->hw;
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u64 stamp = 0;
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int shift = 0;
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/*
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* The timestamp latches on lowest register read. For the 82580
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* the lowest register is SYSTIMR instead of SYSTIML. However we never
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* adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
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*/
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if (hw->mac.type >= e1000_82580) {
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stamp = rd32(E1000_SYSTIMR) >> 8;
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shift = IGB_82580_TSYNC_SHIFT;
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}
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stamp |= (u64)rd32(E1000_SYSTIML) << shift;
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stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
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return stamp;
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}
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/**
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* igb_get_hw_dev - return device
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* used by hardware layer to print debugging information
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@ -2110,9 +2082,11 @@ static int __devinit igb_probe(struct pci_dev *pdev,
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}
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#endif
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#ifdef CONFIG_IGB_PTP
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/* do hw tstamp init after resetting */
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igb_init_hw_timer(adapter);
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igb_ptp_init(adapter);
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#endif
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dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
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/* print bus type/speed/width info */
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dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
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@ -2184,7 +2158,10 @@ static void __devexit igb_remove(struct pci_dev *pdev)
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struct e1000_hw *hw = &adapter->hw;
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pm_runtime_get_noresume(&pdev->dev);
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#ifdef CONFIG_IGB_PTP
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igb_ptp_remove(adapter);
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#endif
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/*
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* The watchdog timer may be rescheduled, so explicitly
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* disable watchdog from being rescheduled.
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@ -2303,112 +2280,6 @@ out:
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#endif /* CONFIG_PCI_IOV */
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}
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/**
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* igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
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* @adapter: board private structure to initialize
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*
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* igb_init_hw_timer initializes the function pointer and values for the hw
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* timer found in hardware.
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**/
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static void igb_init_hw_timer(struct igb_adapter *adapter)
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{
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struct e1000_hw *hw = &adapter->hw;
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switch (hw->mac.type) {
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case e1000_i350:
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case e1000_82580:
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memset(&adapter->cycles, 0, sizeof(adapter->cycles));
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adapter->cycles.read = igb_read_clock;
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adapter->cycles.mask = CLOCKSOURCE_MASK(64);
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adapter->cycles.mult = 1;
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/*
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* The 82580 timesync updates the system timer every 8ns by 8ns
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* and the value cannot be shifted. Instead we need to shift
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* the registers to generate a 64bit timer value. As a result
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* SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
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* 24 in order to generate a larger value for synchronization.
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*/
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adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
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/* disable system timer temporarily by setting bit 31 */
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wr32(E1000_TSAUXC, 0x80000000);
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wrfl();
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/* Set registers so that rollover occurs soon to test this. */
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wr32(E1000_SYSTIMR, 0x00000000);
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wr32(E1000_SYSTIML, 0x80000000);
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wr32(E1000_SYSTIMH, 0x000000FF);
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wrfl();
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/* enable system timer by clearing bit 31 */
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wr32(E1000_TSAUXC, 0x0);
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wrfl();
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timecounter_init(&adapter->clock,
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&adapter->cycles,
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ktime_to_ns(ktime_get_real()));
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/*
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* Synchronize our NIC clock against system wall clock. NIC
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* time stamp reading requires ~3us per sample, each sample
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* was pretty stable even under load => only require 10
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* samples for each offset comparison.
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*/
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memset(&adapter->compare, 0, sizeof(adapter->compare));
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adapter->compare.source = &adapter->clock;
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adapter->compare.target = ktime_get_real;
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adapter->compare.num_samples = 10;
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timecompare_update(&adapter->compare, 0);
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break;
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case e1000_82576:
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/*
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* Initialize hardware timer: we keep it running just in case
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* that some program needs it later on.
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*/
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memset(&adapter->cycles, 0, sizeof(adapter->cycles));
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adapter->cycles.read = igb_read_clock;
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adapter->cycles.mask = CLOCKSOURCE_MASK(64);
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adapter->cycles.mult = 1;
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/**
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* Scale the NIC clock cycle by a large factor so that
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* relatively small clock corrections can be added or
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* subtracted at each clock tick. The drawbacks of a large
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* factor are a) that the clock register overflows more quickly
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* (not such a big deal) and b) that the increment per tick has
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* to fit into 24 bits. As a result we need to use a shift of
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* 19 so we can fit a value of 16 into the TIMINCA register.
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*/
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adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
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wr32(E1000_TIMINCA,
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(1 << E1000_TIMINCA_16NS_SHIFT) |
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(16 << IGB_82576_TSYNC_SHIFT));
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/* Set registers so that rollover occurs soon to test this. */
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wr32(E1000_SYSTIML, 0x00000000);
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wr32(E1000_SYSTIMH, 0xFF800000);
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wrfl();
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timecounter_init(&adapter->clock,
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&adapter->cycles,
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ktime_to_ns(ktime_get_real()));
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/*
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* Synchronize our NIC clock against system wall clock. NIC
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* time stamp reading requires ~3us per sample, each sample
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* was pretty stable even under load => only require 10
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* samples for each offset comparison.
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*/
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memset(&adapter->compare, 0, sizeof(adapter->compare));
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adapter->compare.source = &adapter->clock;
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adapter->compare.target = ktime_get_real;
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adapter->compare.num_samples = 10;
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timecompare_update(&adapter->compare, 0);
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break;
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case e1000_82575:
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/* 82575 does not support timesync */
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default:
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break;
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}
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}
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/**
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* igb_sw_init - Initialize general software structures (struct igb_adapter)
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* @adapter: board private structure to initialize
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@ -5718,35 +5589,7 @@ static int igb_poll(struct napi_struct *napi, int budget)
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return 0;
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}
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/**
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* igb_systim_to_hwtstamp - convert system time value to hw timestamp
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* @adapter: board private structure
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* @shhwtstamps: timestamp structure to update
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* @regval: unsigned 64bit system time value.
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*
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* We need to convert the system time value stored in the RX/TXSTMP registers
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* into a hwtstamp which can be used by the upper level timestamping functions
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*/
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static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
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struct skb_shared_hwtstamps *shhwtstamps,
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u64 regval)
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{
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u64 ns;
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/*
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* The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
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* 24 to match clock shift we setup earlier.
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*/
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if (adapter->hw.mac.type >= e1000_82580)
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regval <<= IGB_82580_TSYNC_SHIFT;
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ns = timecounter_cyc2time(&adapter->clock, regval);
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timecompare_update(&adapter->compare, ns);
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memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
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shhwtstamps->hwtstamp = ns_to_ktime(ns);
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shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
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}
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#ifdef CONFIG_IGB_PTP
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/**
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* igb_tx_hwtstamp - utility function which checks for TX time stamp
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* @q_vector: pointer to q_vector containing needed info
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@ -5776,6 +5619,7 @@ static void igb_tx_hwtstamp(struct igb_q_vector *q_vector,
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skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
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}
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#endif
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/**
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* igb_clean_tx_irq - Reclaim resources after transmit completes
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* @q_vector: pointer to q_vector containing needed info
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@ -5819,9 +5663,11 @@ static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
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total_bytes += tx_buffer->bytecount;
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total_packets += tx_buffer->gso_segs;
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#ifdef CONFIG_IGB_PTP
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/* retrieve hardware timestamp */
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igb_tx_hwtstamp(q_vector, tx_buffer);
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#endif
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/* free the skb */
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dev_kfree_skb_any(tx_buffer->skb);
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tx_buffer->skb = NULL;
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skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
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}
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#ifdef CONFIG_IGB_PTP
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static void igb_rx_hwtstamp(struct igb_q_vector *q_vector,
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union e1000_adv_rx_desc *rx_desc,
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struct sk_buff *skb)
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igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
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}
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#endif
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static void igb_rx_vlan(struct igb_ring *ring,
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union e1000_adv_rx_desc *rx_desc,
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struct sk_buff *skb)
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goto next_desc;
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}
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#ifdef CONFIG_IGB_PTP
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igb_rx_hwtstamp(q_vector, rx_desc, skb);
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#endif
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igb_rx_hash(rx_ring, rx_desc, skb);
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igb_rx_checksum(rx_ring, rx_desc, skb);
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igb_rx_vlan(rx_ring, rx_desc, skb);
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@ -27,6 +27,9 @@
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#define ISGN 0x80000000
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/*
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* The 82580 timesync updates the system timer every 8ns by 8ns,
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* and this update value cannot be reprogrammed.
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*
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* Neither the 82576 nor the 82580 offer registers wide enough to hold
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* nanoseconds time values for very long. For the 82580, SYSTIM always
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* counts nanoseconds, but the upper 24 bits are not availible. The
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* field are needed to provide the nominal 16 nanosecond period,
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* leaving 19 bits for fractional nanoseconds.
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*
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* We scale the NIC clock cycle by a large factor so that relatively
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* small clock corrections can be added or subtracted at each clock
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* tick. The drawbacks of a large factor are a) that the clock
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* register overflows more quickly (not such a big deal) and b) that
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* the increment per tick has to fit into 24 bits. As a result we
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* need to use a shift of 19 so we can fit a value of 16 into the
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* TIMINCA register.
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*
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*
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* SYSTIMH SYSTIML
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* +--------------+ +---+---+------+
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struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
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struct e1000_hw *hw = &igb->hw;
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/*
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* The timestamp latches on lowest register read. For the 82580
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* the lowest register is SYSTIMR instead of SYSTIML. However we only
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* need to provide nanosecond resolution, so we just ignore it.
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*/
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jk = rd32(E1000_SYSTIMR);
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lo = rd32(E1000_SYSTIML);
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hi = rd32(E1000_SYSTIMH);
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@ -320,3 +336,46 @@ void igb_ptp_remove(struct igb_adapter *adapter)
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adapter->netdev->name);
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}
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}
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/**
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* igb_systim_to_hwtstamp - convert system time value to hw timestamp
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* @adapter: board private structure
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* @hwtstamps: timestamp structure to update
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* @systim: unsigned 64bit system time value.
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*
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* We need to convert the system time value stored in the RX/TXSTMP registers
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* into a hwtstamp which can be used by the upper level timestamping functions.
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*
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* The 'tmreg_lock' spinlock is used to protect the consistency of the
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* system time value. This is needed because reading the 64 bit time
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* value involves reading two (or three) 32 bit registers. The first
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* read latches the value. Ditto for writing.
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*
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* In addition, here have extended the system time with an overflow
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* counter in software.
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**/
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void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
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struct skb_shared_hwtstamps *hwtstamps,
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u64 systim)
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{
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u64 ns;
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unsigned long flags;
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switch (adapter->hw.mac.type) {
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case e1000_i350:
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case e1000_82580:
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case e1000_82576:
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break;
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default:
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return;
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}
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spin_lock_irqsave(&adapter->tmreg_lock, flags);
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ns = timecounter_cyc2time(&adapter->tc, systim);
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spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
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memset(hwtstamps, 0, sizeof(*hwtstamps));
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hwtstamps->hwtstamp = ns_to_ktime(ns);
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}
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