[ALSA] sun-cs4231: use cs4231-regs.h
This patch replaces cs4231 registers definitions with common include. Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl> Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Jaroslav Kysela <perex@suse.cz>
This commit is contained in:
Krzysztof Helt
Jaroslav Kysela
parent
e31b6656a8
commit
7e52f3dac7
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@ -135,129 +135,10 @@ static struct snd_cs4231 *cs4231_list;
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*/
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/* IO ports */
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#define CS4231P(chip, x) ((chip)->port + c_d_c_CS4231##x)
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#include <sound/cs4231-regs.h>
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/* XXX offsets are different than PC ISA chips... */
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#define c_d_c_CS4231REGSEL 0x0
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#define c_d_c_CS4231REG 0x4
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#define c_d_c_CS4231STATUS 0x8
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#define c_d_c_CS4231PIO 0xc
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/* codec registers */
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#define CS4231_LEFT_INPUT 0x00 /* left input control */
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#define CS4231_RIGHT_INPUT 0x01 /* right input control */
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#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */
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#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */
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#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */
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#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */
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#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */
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#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */
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#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */
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#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */
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#define CS4231_PIN_CTRL 0x0a /* pin control */
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#define CS4231_TEST_INIT 0x0b /* test and initialization */
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#define CS4231_MISC_INFO 0x0c /* miscellaneaous information */
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#define CS4231_LOOPBACK 0x0d /* loopback control */
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#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */
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#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */
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#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */
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#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */
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#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */
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#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */
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#define CS4231_TIMER_LOW 0x14 /* timer low byte */
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#define CS4231_TIMER_HIGH 0x15 /* timer high byte */
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#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */
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#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */
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#define CS4236_EXT_REG 0x17 /* extended register access */
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#define CS4231_IRQ_STATUS 0x18 /* irq status register */
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#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */
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#define CS4231_VERSION 0x19 /* CS4231(A) - version values */
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#define CS4231_MONO_CTRL 0x1a /* mono input/output control */
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#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */
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#define CS4235_LEFT_MASTER 0x1b /* left master output control */
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#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */
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#define CS4231_PLY_VAR_FREQ 0x1d /* playback variable frequency */
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#define CS4235_RIGHT_MASTER 0x1d /* right master output control */
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#define CS4231_REC_UPR_CNT 0x1e /* record upper count */
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#define CS4231_REC_LWR_CNT 0x1f /* record lower count */
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/* definitions for codec register select port - CODECP( REGSEL ) */
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#define CS4231_INIT 0x80 /* CODEC is initializing */
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#define CS4231_MCE 0x40 /* mode change enable */
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#define CS4231_TRD 0x20 /* transfer request disable */
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/* definitions for codec status register - CODECP( STATUS ) */
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#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */
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/* definitions for codec irq status - CS4231_IRQ_STATUS */
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#define CS4231_PLAYBACK_IRQ 0x10
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#define CS4231_RECORD_IRQ 0x20
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#define CS4231_TIMER_IRQ 0x40
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#define CS4231_ALL_IRQS 0x70
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#define CS4231_REC_UNDERRUN 0x08
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#define CS4231_REC_OVERRUN 0x04
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#define CS4231_PLY_OVERRUN 0x02
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#define CS4231_PLY_UNDERRUN 0x01
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/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */
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#define CS4231_ENABLE_MIC_GAIN 0x20
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#define CS4231_MIXS_LINE 0x00
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#define CS4231_MIXS_AUX1 0x40
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#define CS4231_MIXS_MIC 0x80
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#define CS4231_MIXS_ALL 0xc0
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/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */
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#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */
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#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */
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#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */
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#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */
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#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */
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#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */
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#define CS4231_STEREO 0x10 /* stereo mode */
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/* bits 3-1 define frequency divisor */
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#define CS4231_XTAL1 0x00 /* 24.576 crystal */
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#define CS4231_XTAL2 0x01 /* 16.9344 crystal */
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/* definitions for interface control register - CS4231_IFACE_CTRL */
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#define CS4231_RECORD_PIO 0x80 /* record PIO enable */
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#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */
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#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */
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#define CS4231_AUTOCALIB 0x08 /* auto calibrate */
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#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */
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#define CS4231_RECORD_ENABLE 0x02 /* record enable */
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#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */
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/* definitions for pin control register - CS4231_PIN_CTRL */
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#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */
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#define CS4231_XCTL1 0x40 /* external control #1 */
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#define CS4231_XCTL0 0x80 /* external control #0 */
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/* definitions for test and init register - CS4231_TEST_INIT */
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#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */
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#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */
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/* definitions for misc control register - CS4231_MISC_INFO */
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#define CS4231_MODE2 0x40 /* MODE 2 */
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#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */
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#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */
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/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */
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#define CS4231_DACZ 0x01 /* zero DAC when underrun */
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#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */
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#define CS4231_OLB 0x80 /* output level bit */
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#define CS4231U(chip, x) ((chip)->port + ((c_d_c_CS4231##x) << 2))
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/* SBUS DMA register defines. */
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@ -418,10 +299,12 @@ static void snd_cs4231_ready(struct snd_cs4231 *chip)
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{
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int timeout;
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for (timeout = 250;
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timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
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timeout--)
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udelay(100);
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for (timeout = 250; timeout > 0; timeout--) {
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int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
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if ((val & CS4231_INIT) == 0)
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break;
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udelay(100);
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}
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}
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static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
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@ -429,14 +312,14 @@ static void snd_cs4231_dout(struct snd_cs4231 *chip, unsigned char reg,
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{
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snd_cs4231_ready(chip);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
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snd_printdd("out: auto calibration time out - reg = 0x%x, "
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"value = 0x%x\n",
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reg, value);
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#endif
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__cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
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__cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
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wmb();
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__cs4231_writeb(chip, value, CS4231P(chip, REG));
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__cs4231_writeb(chip, value, CS4231U(chip, REG));
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mb();
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}
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@ -462,13 +345,13 @@ static unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg)
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{
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snd_cs4231_ready(chip);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
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snd_printdd("in: auto calibration time out - reg = 0x%x\n",
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reg);
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#endif
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__cs4231_writeb(chip, chip->mce_bit | reg, CS4231P(chip, REGSEL));
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__cs4231_writeb(chip, chip->mce_bit | reg, CS4231U(chip, REGSEL));
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mb();
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return __cs4231_readb(chip, CS4231P(chip, REG));
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return __cs4231_readb(chip, CS4231U(chip, REG));
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}
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/*
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@ -481,13 +364,15 @@ static void snd_cs4231_busy_wait(struct snd_cs4231 *chip)
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/* looks like this sequence is proper for CS4231A chip (GUS MAX) */
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for (timeout = 5; timeout > 0; timeout--)
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__cs4231_readb(chip, CS4231P(chip, REGSEL));
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__cs4231_readb(chip, CS4231U(chip, REGSEL));
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/* end of cleanup sequence */
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for (timeout = 500;
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timeout > 0 && (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT);
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timeout--)
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for (timeout = 500; timeout > 0; timeout--) {
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int val = __cs4231_readb(chip, CS4231U(chip, REGSEL));
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if ((val & CS4231_INIT) == 0)
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break;
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msleep(1);
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}
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}
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static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
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@ -498,17 +383,18 @@ static void snd_cs4231_mce_up(struct snd_cs4231 *chip)
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spin_lock_irqsave(&chip->lock, flags);
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snd_cs4231_ready(chip);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
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snd_printdd("mce_up - auto calibration time out (0)\n");
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#endif
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chip->mce_bit |= CS4231_MCE;
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timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
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timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
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if (timeout == 0x80)
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snd_printdd("mce_up [%p]: serious init problem - "
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"codec still busy\n",
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chip->port);
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if (!(timeout & CS4231_MCE))
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__cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
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__cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
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CS4231U(chip, REGSEL));
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spin_unlock_irqrestore(&chip->lock, flags);
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}
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@ -520,12 +406,14 @@ static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
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spin_lock_irqsave(&chip->lock, flags);
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snd_cs4231_busy_wait(chip);
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#ifdef CONFIG_SND_DEBUG
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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snd_printdd("mce_down [%p] - auto calibration time out (0)\n", CS4231P(chip, REGSEL));
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if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
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snd_printdd("mce_down [%p] - auto calibration time out (0)\n",
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CS4231U(chip, REGSEL));
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#endif
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chip->mce_bit &= ~CS4231_MCE;
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timeout = __cs4231_readb(chip, CS4231P(chip, REGSEL));
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__cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f), CS4231P(chip, REGSEL));
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timeout = __cs4231_readb(chip, CS4231U(chip, REGSEL));
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__cs4231_writeb(chip, chip->mce_bit | (timeout & 0x1f),
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CS4231U(chip, REGSEL));
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if (timeout == 0x80)
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snd_printdd("mce_down [%p]: serious init problem - "
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"codec still busy\n",
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@ -564,7 +452,7 @@ static void snd_cs4231_mce_down(struct snd_cs4231 *chip)
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/* in 10ms increments, check condition, up to 100ms */
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timeout = 10;
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while (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT) {
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while (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT) {
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spin_unlock_irqrestore(&chip->lock, flags);
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if (--timeout < 0) {
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snd_printk("mce_down - "
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@ -944,8 +832,8 @@ static int snd_cs4231_open(struct snd_cs4231 *chip, unsigned int mode)
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CS4231_RECORD_IRQ |
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CS4231_TIMER_IRQ);
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snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
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__cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
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snd_cs4231_out(chip, CS4231_IRQ_STATUS, CS4231_PLAYBACK_IRQ |
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CS4231_RECORD_IRQ |
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@ -974,8 +862,8 @@ static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
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/* disable IRQ */
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spin_lock_irqsave(&chip->lock, flags);
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snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
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__cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
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/* now disable record & playback */
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@ -997,8 +885,8 @@ static void snd_cs4231_close(struct snd_cs4231 *chip, unsigned int mode)
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/* clear IRQ again */
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snd_cs4231_out(chip, CS4231_IRQ_STATUS, 0);
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__cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231P(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
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__cs4231_writeb(chip, 0, CS4231U(chip, STATUS)); /* clear IRQ */
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spin_unlock_irqrestore(&chip->lock, flags);
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snd_cs4231_calibrate_mute(chip, 0);
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@ -1187,7 +1075,7 @@ static int __init snd_cs4231_probe(struct snd_cs4231 *chip)
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for (i = 0; i < 50; i++) {
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mb();
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if (__cs4231_readb(chip, CS4231P(chip, REGSEL)) & CS4231_INIT)
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if (__cs4231_readb(chip, CS4231U(chip, REGSEL)) & CS4231_INIT)
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msleep(2);
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else {
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spin_lock_irqsave(&chip->lock, flags);
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@ -1205,8 +1093,9 @@ static int __init snd_cs4231_probe(struct snd_cs4231 *chip)
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spin_lock_irqsave(&chip->lock, flags);
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__cs4231_readb(chip, CS4231P(chip, STATUS)); /* clear any pendings IRQ */
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__cs4231_writeb(chip, 0, CS4231P(chip, STATUS));
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/* clear any pendings IRQ */
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__cs4231_readb(chip, CS4231U(chip, STATUS));
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__cs4231_writeb(chip, 0, CS4231U(chip, STATUS));
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mb();
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spin_unlock_irqrestore(&chip->lock, flags);
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@ -1784,7 +1673,7 @@ static irqreturn_t snd_cs4231_sbus_interrupt(int irq, void *dev_id)
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struct snd_cs4231 *chip = dev_id;
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/*This is IRQ is not raised by the cs4231*/
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if (!(__cs4231_readb(chip, CS4231P(chip, STATUS)) & CS4231_GLOBALIRQ))
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if (!(__cs4231_readb(chip, CS4231U(chip, STATUS)) & CS4231_GLOBALIRQ))
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return IRQ_NONE;
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/* ACK the APC interrupt. */
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