irqchip/mxs: Add Alphascale ASM9260 support
Freescale iMX23/iMX28 and Alphascale ASM9260 have similar interrupt collectors. We already prepared the mxs driver to handle a different register layout. Add the actual ASM9260 support. Differences between these devices: - Different register offsets - Different count of interupt lines per register - ASM9260 does not provide reset bit - ASM9260 does not support FIQ. Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Tested-by: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: marc.zyngier@arm.com Cc: jason@lakedaemon.net Link: http://lkml.kernel.org/r/1444677334-12242-6-git-send-email-linux@rempel-privat.de Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This commit is contained in:
Oleksij Rempel
Thomas Gleixner
parent
25e34b4431
commit
7e4ac676ee
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@ -188,3 +188,8 @@ config IMX_GPCV2
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select IRQ_DOMAIN
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help
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Enables the wakeup IRQs for IMX platforms with GPCv2 block
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config IRQ_MXS
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def_bool y if MACH_ASM9260 || ARCH_MXS
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select IRQ_DOMAIN
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select STMP_DEVICE
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@ -6,7 +6,7 @@ obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
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obj-$(CONFIG_ARCH_HIP04) += irq-hip04.o
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obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
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obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
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obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
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obj-$(CONFIG_IRQ_MXS) += irq-mxs.o
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obj-$(CONFIG_ARCH_TEGRA) += irq-tegra.o
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obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
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obj-$(CONFIG_DW_APB_ICTL) += irq-dw-apb-ictl.o
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@ -0,0 +1,109 @@
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/*
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* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _ALPHASCALE_ASM9260_ICOLL_H
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#define _ALPHASCALE_ASM9260_ICOLL_H
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#define ASM9260_NUM_IRQS 64
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/*
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* this device provide 4 offsets for each register:
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* 0x0 - plain read write mode
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* 0x4 - set mode, OR logic.
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* 0x8 - clr mode, XOR logic.
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* 0xc - togle mode.
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*/
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#define ASM9260_HW_ICOLL_VECTOR 0x0000
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/*
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* bits 31:2
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* This register presents the vector address for the interrupt currently
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* active on the CPU IRQ input. Writing to this register notifies the
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* interrupt collector that the interrupt service routine for the current
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* interrupt has been entered.
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* The exception trap should have a LDPC instruction from this address:
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* LDPC ASM9260_HW_ICOLL_VECTOR_ADDR; IRQ exception at 0xffff0018
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*/
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/*
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* The Interrupt Collector Level Acknowledge Register is used by software to
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* indicate the completion of an interrupt on a specific level.
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* This register is written at the very end of an interrupt service routine. If
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* nesting is used then the CPU irq must be turned on before writing to this
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* register to avoid a race condition in the CPU interrupt hardware.
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*/
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#define ASM9260_HW_ICOLL_LEVELACK 0x0010
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#define ASM9260_BM_LEVELn(nr) BIT(nr)
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#define ASM9260_HW_ICOLL_CTRL 0x0020
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/*
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* ASM9260_BM_CTRL_SFTRST and ASM9260_BM_CTRL_CLKGATE are not available on
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* asm9260.
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*/
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#define ASM9260_BM_CTRL_SFTRST BIT(31)
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#define ASM9260_BM_CTRL_CLKGATE BIT(30)
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/* disable interrupt level nesting */
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#define ASM9260_BM_CTRL_NO_NESTING BIT(19)
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/*
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* Set this bit to one enable the RISC32-style read side effect associated with
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* the vector address register. In this mode, interrupt in-service is signaled
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* by the read of the ASM9260_HW_ICOLL_VECTOR register to acquire the interrupt
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* vector address. Set this bit to zero for normal operation, in which the ISR
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* signals in-service explicitly by means of a write to the
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* ASM9260_HW_ICOLL_VECTOR register.
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* 0 - Must Write to Vector register to go in-service.
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* 1 - Go in-service as a read side effect
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*/
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#define ASM9260_BM_CTRL_ARM_RSE_MODE BIT(18)
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#define ASM9260_BM_CTRL_IRQ_ENABLE BIT(16)
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#define ASM9260_HW_ICOLL_STAT_OFFSET 0x0030
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/*
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* bits 5:0
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* Vector number of current interrupt. Multiply by 4 and add to vector base
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* address to obtain the value in ASM9260_HW_ICOLL_VECTOR.
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*/
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/*
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* RAW0 and RAW1 provides a read-only view of the raw interrupt request lines
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* coming from various parts of the chip. Its purpose is to improve diagnostic
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* observability.
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*/
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#define ASM9260_HW_ICOLL_RAW0 0x0040
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#define ASM9260_HW_ICOLL_RAW1 0x0050
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#define ASM9260_HW_ICOLL_INTERRUPT0 0x0060
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#define ASM9260_HW_ICOLL_INTERRUPTn(n) (0x0060 + ((n) >> 2) * 0x10)
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/*
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* WARNING: Modifying the priority of an enabled interrupt may result in
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* undefined behavior.
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*/
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#define ASM9260_BM_INT_PRIORITY_MASK 0x3
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#define ASM9260_BM_INT_ENABLE BIT(2)
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#define ASM9260_BM_INT_SOFTIRQ BIT(3)
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#define ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n) (((n) & 0x3) << 3)
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#define ASM9260_BM_ICOLL_INTERRUPTn_ENABLE(n) (1 << (2 + \
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ASM9260_BM_ICOLL_INTERRUPTn_SHIFT(n)))
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#define ASM9260_HW_ICOLL_VBASE 0x0160
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/*
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* bits 31:2
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* This bitfield holds the upper 30 bits of the base address of the vector
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* table.
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*/
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#define ASM9260_HW_ICOLL_CLEAR0 0x01d0
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#define ASM9260_HW_ICOLL_CLEAR1 0x01e0
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#define ASM9260_HW_ICOLL_CLEARn(n) (((n >> 5) * 0x10) \
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+ SET_REG)
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#define ASM9260_BM_CLEAR_BIT(n) BIT(n & 0x1f)
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/* Scratchpad */
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#define ASM9260_HW_ICOLL_UNDEF_VECTOR 0x01f0
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#endif
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@ -1,5 +1,7 @@
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/*
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* Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de>
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* Add Alphascale ASM9260 support.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -28,6 +30,8 @@
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#include <linux/stmp_device.h>
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#include <asm/exception.h>
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#include "alphascale_asm9260-icoll.h"
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/*
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* this device provide 4 offsets for each register:
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* 0x0 - plain read write mode
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@ -49,17 +53,41 @@
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#define ICOLL_NUM_IRQS 128
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enum icoll_type {
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ICOLL,
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ASM9260_ICOLL,
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};
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struct icoll_priv {
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void __iomem *vector;
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void __iomem *levelack;
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void __iomem *ctrl;
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void __iomem *stat;
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void __iomem *intr;
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void __iomem *clear;
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enum icoll_type type;
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};
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static struct icoll_priv icoll_priv;
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static struct irq_domain *icoll_domain;
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/* calculate bit offset depending on number of intterupt per register */
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static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit)
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{
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/*
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* mask lower part of hwirq to convert it
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* in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3)
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*/
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return bit << ((d->hwirq & 3) << 3);
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}
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/* calculate mem offset depending on number of intterupt per register */
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static void __iomem *icoll_intr_reg(struct irq_data *d)
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{
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/* offset = hwirq / intr_per_reg * 0x10 */
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return icoll_priv.intr + ((d->hwirq >> 2) * 0x10);
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}
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static void icoll_ack_irq(struct irq_data *d)
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{
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/*
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@ -83,12 +111,34 @@ static void icoll_unmask_irq(struct irq_data *d)
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icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq));
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}
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static void asm9260_mask_irq(struct irq_data *d)
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{
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__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
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icoll_intr_reg(d) + CLR_REG);
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}
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static void asm9260_unmask_irq(struct irq_data *d)
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{
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__raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq),
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icoll_priv.clear +
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ASM9260_HW_ICOLL_CLEARn(d->hwirq));
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__raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE),
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icoll_intr_reg(d) + SET_REG);
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}
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static struct irq_chip mxs_icoll_chip = {
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.irq_ack = icoll_ack_irq,
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.irq_mask = icoll_mask_irq,
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.irq_unmask = icoll_unmask_irq,
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};
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static struct irq_chip asm9260_icoll_chip = {
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.irq_ack = icoll_ack_irq,
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.irq_mask = asm9260_mask_irq,
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.irq_unmask = asm9260_unmask_irq,
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};
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asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
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{
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u32 irqnr;
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@ -101,7 +151,14 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
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static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_chip_and_handler(virq, &mxs_icoll_chip, handle_level_irq);
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struct irq_chip *chip;
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if (icoll_priv.type == ICOLL)
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chip = &mxs_icoll_chip;
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else
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chip = &asm9260_icoll_chip;
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irq_set_chip_and_handler(virq, chip, handle_level_irq);
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return 0;
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}
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@ -136,12 +193,15 @@ static int __init icoll_of_init(struct device_node *np,
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{
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void __iomem *icoll_base;
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icoll_priv.type = ICOLL;
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icoll_base = icoll_init_iobase(np);
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icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR;
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icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK;
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icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL;
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icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET;
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icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0;
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icoll_priv.clear = NULL;
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/*
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* Interrupt Collector reset, which initializes the priority
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@ -154,3 +214,34 @@ static int __init icoll_of_init(struct device_node *np,
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return 0;
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}
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IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
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static int __init asm9260_of_init(struct device_node *np,
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struct device_node *interrupt_parent)
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{
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void __iomem *icoll_base;
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int i;
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icoll_priv.type = ASM9260_ICOLL;
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icoll_base = icoll_init_iobase(np);
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icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR;
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icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK;
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icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL;
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icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET;
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icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0;
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icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0;
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writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE,
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icoll_priv.ctrl);
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/*
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* ASM9260 don't provide reset bit. So, we need to set level 0
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* manually.
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*/
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for (i = 0; i < 16 * 0x10; i += 0x10)
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writel(0, icoll_priv.intr + i);
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icoll_add_domain(np, ASM9260_NUM_IRQS);
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return 0;
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}
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IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init);
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