drm-misc-fixes for v5.15-rc7:
- Rebased, to remove vc4 patches. - Fix mxsfb crash on unload. - Use correct sync parameters for Feixin K101-IM2BYL02. - Assorted kmb modeset/atomic fixes. -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEuXvWqAysSYEJGuVH/lWMcqZwE8MFAmFxM6YACgkQ/lWMcqZw E8MDpRAAki0KQpdlg00AglHfomXg40A6fzCMha5eFWxG1inPav11+Rquxu/E1q1q z3dt6MsHMxoj+rV9vedpRJKcj1HP0GYIgzXJGLKbA0he5Ie4XCAKMj8KixpcKnIJ GG3giX+ownnHcKOKcV6AvF/wiXoIGaIYCSwllEBZ01bW92rVBIPVkvadbcpCCtR+ rqm4tz6vcRV23M5XqBhzDjaB9IZ+5Xjvyw8CNF2yuoFbPprSML0WVF6NZuF/me8W L3d8P6CVXUzvIJzRN8LogpyYUtcWjx1jgLAt6urU9xCh/kVl08NB0w8Aw2ZIJS3l xI+G2P549TTAg6JK5WGIEUiaNNMjtsO17BEk+PjXwQrtaIemkiPKwLZn0zaZuEsR 5HCV0vRkzMeoYKOD5epZKLRw15nUDMu1I8a/O9Lkxe6u0FNRu8sQ3bO4TwfYSDLv 742YL7UcYVFQq805NBPIeV2WI5W5ROSk8MVQAAyOHQRKTUpJd+cbXJsUFCvAeZ0o EFk3R4CoV6ZoJMDLuq08S4nvDut1TyIF6QJpUWKt5X/kcguz4y0ymoJT2FhDeODf fgIulBc5e8Qa12afbKY2u1OCoFFnQZIwL3tv3PfVXLzGNIO1MeY2la0Is3saMPuy +kAlLDtk0YpVMsLTcmv+5nlehdB554ob72/4y9s0ppOMso1CbYg= =dKM5 -----END PGP SIGNATURE----- Merge tag 'drm-misc-fixes-2021-10-21-1' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes drm-misc-fixes for v5.15-rc7: - Rebased, to remove vc4 patches. - Fix mxsfb crash on unload. - Use correct sync parameters for Feixin K101-IM2BYL02. - Assorted kmb modeset/atomic fixes. Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/e66eaf89-b9b9-41f5-d0d2-dad7e59fabb5@linux.intel.com
This commit is contained in:
Dave Airlie
commit
7e1c5440f4
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@ -66,7 +66,8 @@ static const struct drm_crtc_funcs kmb_crtc_funcs = {
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.disable_vblank = kmb_crtc_disable_vblank,
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};
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static void kmb_crtc_set_mode(struct drm_crtc *crtc)
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static void kmb_crtc_set_mode(struct drm_crtc *crtc,
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struct drm_atomic_state *old_state)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_display_mode *m = &crtc->state->adjusted_mode;
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@ -75,7 +76,7 @@ static void kmb_crtc_set_mode(struct drm_crtc *crtc)
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unsigned int val = 0;
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/* Initialize mipi */
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kmb_dsi_mode_set(kmb->kmb_dsi, m, kmb->sys_clk_mhz);
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kmb_dsi_mode_set(kmb->kmb_dsi, m, kmb->sys_clk_mhz, old_state);
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drm_info(dev,
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"vfp= %d vbp= %d vsync_len=%d hfp=%d hbp=%d hsync_len=%d\n",
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m->crtc_vsync_start - m->crtc_vdisplay,
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@ -138,7 +139,7 @@ static void kmb_crtc_atomic_enable(struct drm_crtc *crtc,
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struct kmb_drm_private *kmb = crtc_to_kmb_priv(crtc);
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clk_prepare_enable(kmb->kmb_clk.clk_lcd);
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kmb_crtc_set_mode(crtc);
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kmb_crtc_set_mode(crtc, state);
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drm_crtc_vblank_on(crtc);
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}
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@ -185,11 +186,45 @@ static void kmb_crtc_atomic_flush(struct drm_crtc *crtc,
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spin_unlock_irq(&crtc->dev->event_lock);
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}
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static enum drm_mode_status
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kmb_crtc_mode_valid(struct drm_crtc *crtc,
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const struct drm_display_mode *mode)
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{
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int refresh;
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struct drm_device *dev = crtc->dev;
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int vfp = mode->vsync_start - mode->vdisplay;
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if (mode->vdisplay < KMB_CRTC_MAX_HEIGHT) {
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drm_dbg(dev, "height = %d less than %d",
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mode->vdisplay, KMB_CRTC_MAX_HEIGHT);
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return MODE_BAD_VVALUE;
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}
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if (mode->hdisplay < KMB_CRTC_MAX_WIDTH) {
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drm_dbg(dev, "width = %d less than %d",
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mode->hdisplay, KMB_CRTC_MAX_WIDTH);
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return MODE_BAD_HVALUE;
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}
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refresh = drm_mode_vrefresh(mode);
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if (refresh < KMB_MIN_VREFRESH || refresh > KMB_MAX_VREFRESH) {
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drm_dbg(dev, "refresh = %d less than %d or greater than %d",
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refresh, KMB_MIN_VREFRESH, KMB_MAX_VREFRESH);
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return MODE_BAD;
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}
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if (vfp < KMB_CRTC_MIN_VFP) {
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drm_dbg(dev, "vfp = %d less than %d", vfp, KMB_CRTC_MIN_VFP);
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return MODE_BAD;
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}
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return MODE_OK;
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}
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static const struct drm_crtc_helper_funcs kmb_crtc_helper_funcs = {
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.atomic_begin = kmb_crtc_atomic_begin,
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.atomic_enable = kmb_crtc_atomic_enable,
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.atomic_disable = kmb_crtc_atomic_disable,
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.atomic_flush = kmb_crtc_atomic_flush,
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.mode_valid = kmb_crtc_mode_valid,
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};
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int kmb_setup_crtc(struct drm_device *drm)
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@ -380,7 +380,7 @@ static irqreturn_t handle_lcd_irq(struct drm_device *dev)
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if (val & LAYER3_DMA_FIFO_UNDERFLOW)
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drm_dbg(&kmb->drm,
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"LAYER3:GL1 DMA UNDERFLOW val = 0x%lx", val);
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if (val & LAYER3_DMA_FIFO_UNDERFLOW)
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if (val & LAYER3_DMA_FIFO_OVERFLOW)
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drm_dbg(&kmb->drm,
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"LAYER3:GL1 DMA OVERFLOW val = 0x%lx", val);
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}
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@ -20,11 +20,18 @@
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#define DRIVER_MAJOR 1
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#define DRIVER_MINOR 1
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/* Platform definitions */
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#define KMB_CRTC_MIN_VFP 4
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#define KMB_CRTC_MAX_WIDTH 1920 /* max width in pixels */
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#define KMB_CRTC_MAX_HEIGHT 1080 /* max height in pixels */
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#define KMB_CRTC_MIN_WIDTH 1920
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#define KMB_CRTC_MIN_HEIGHT 1080
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#define KMB_FB_MAX_WIDTH 1920
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#define KMB_FB_MAX_HEIGHT 1080
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#define KMB_FB_MIN_WIDTH 1
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#define KMB_FB_MIN_HEIGHT 1
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#define KMB_MIN_VREFRESH 59 /*vertical refresh in Hz */
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#define KMB_MAX_VREFRESH 60 /*vertical refresh in Hz */
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#define KMB_LCD_DEFAULT_CLK 200000000
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#define KMB_SYS_CLK_MHZ 500
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@ -50,6 +57,7 @@ struct kmb_drm_private {
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spinlock_t irq_lock;
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int irq_lcd;
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int sys_clk_mhz;
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struct disp_cfg init_disp_cfg[KMB_MAX_PLANES];
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struct layer_status plane_status[KMB_MAX_PLANES];
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int kmb_under_flow;
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int kmb_flush_done;
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@ -482,6 +482,10 @@ static u32 mipi_tx_fg_section_cfg(struct kmb_dsi *kmb_dsi,
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return 0;
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}
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#define CLK_DIFF_LOW 50
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#define CLK_DIFF_HI 60
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#define SYSCLK_500 500
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static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen,
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struct mipi_tx_frame_timing_cfg *fg_cfg)
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{
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@ -492,7 +496,12 @@ static void mipi_tx_fg_cfg_regs(struct kmb_dsi *kmb_dsi, u8 frame_gen,
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/* 500 Mhz system clock minus 50 to account for the difference in
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* MIPI clock speed in RTL tests
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*/
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sysclk = kmb_dsi->sys_clk_mhz - 50;
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if (kmb_dsi->sys_clk_mhz == SYSCLK_500) {
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sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_LOW;
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} else {
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/* 700 Mhz clk*/
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sysclk = kmb_dsi->sys_clk_mhz - CLK_DIFF_HI;
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}
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/* PPL-Pixel Packing Layer, LLP-Low Level Protocol
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* Frame genartor timing parameters are clocked on the system clock,
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@ -1322,7 +1331,8 @@ static u32 mipi_tx_init_dphy(struct kmb_dsi *kmb_dsi,
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return 0;
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}
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static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi)
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static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi,
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struct drm_atomic_state *old_state)
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{
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struct regmap *msscam;
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@ -1331,7 +1341,7 @@ static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi)
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dev_dbg(kmb_dsi->dev, "failed to get msscam syscon");
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return;
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}
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drm_atomic_bridge_chain_enable(adv_bridge, old_state);
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/* DISABLE MIPI->CIF CONNECTION */
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regmap_write(msscam, MSS_MIPI_CIF_CFG, 0);
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@ -1342,7 +1352,7 @@ static void connect_lcd_to_mipi(struct kmb_dsi *kmb_dsi)
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}
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int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
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int sys_clk_mhz)
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int sys_clk_mhz, struct drm_atomic_state *old_state)
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{
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u64 data_rate;
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@ -1384,18 +1394,13 @@ int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
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mipi_tx_init_cfg.lane_rate_mbps = data_rate;
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}
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kmb_write_mipi(kmb_dsi, DPHY_ENABLE, 0);
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kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL0, 0);
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kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL1, 0);
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kmb_write_mipi(kmb_dsi, DPHY_INIT_CTRL2, 0);
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/* Initialize mipi controller */
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mipi_tx_init_cntrl(kmb_dsi, &mipi_tx_init_cfg);
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/* Dphy initialization */
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mipi_tx_init_dphy(kmb_dsi, &mipi_tx_init_cfg);
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connect_lcd_to_mipi(kmb_dsi);
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connect_lcd_to_mipi(kmb_dsi, old_state);
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dev_info(kmb_dsi->dev, "mipi hw initialized");
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return 0;
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@ -380,7 +380,7 @@ int kmb_dsi_host_bridge_init(struct device *dev);
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struct kmb_dsi *kmb_dsi_init(struct platform_device *pdev);
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void kmb_dsi_host_unregister(struct kmb_dsi *kmb_dsi);
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int kmb_dsi_mode_set(struct kmb_dsi *kmb_dsi, struct drm_display_mode *mode,
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int sys_clk_mhz);
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int sys_clk_mhz, struct drm_atomic_state *old_state);
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int kmb_dsi_map_mmio(struct kmb_dsi *kmb_dsi);
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int kmb_dsi_clk_init(struct kmb_dsi *kmb_dsi);
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int kmb_dsi_encoder_init(struct drm_device *dev, struct kmb_dsi *kmb_dsi);
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@ -67,8 +67,21 @@ static const u32 kmb_formats_v[] = {
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static unsigned int check_pixel_format(struct drm_plane *plane, u32 format)
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{
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struct kmb_drm_private *kmb;
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struct kmb_plane *kmb_plane = to_kmb_plane(plane);
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int i;
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int plane_id = kmb_plane->id;
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struct disp_cfg init_disp_cfg;
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kmb = to_kmb(plane->dev);
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init_disp_cfg = kmb->init_disp_cfg[plane_id];
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/* Due to HW limitations, changing pixel format after initial
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* plane configuration is not supported.
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*/
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if (init_disp_cfg.format && init_disp_cfg.format != format) {
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drm_dbg(&kmb->drm, "Cannot change format after initial plane configuration");
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return -EINVAL;
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}
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for (i = 0; i < plane->format_count; i++) {
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if (plane->format_types[i] == format)
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return 0;
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@ -81,11 +94,17 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
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{
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struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
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plane);
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struct kmb_drm_private *kmb;
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struct kmb_plane *kmb_plane = to_kmb_plane(plane);
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int plane_id = kmb_plane->id;
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struct disp_cfg init_disp_cfg;
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struct drm_framebuffer *fb;
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int ret;
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struct drm_crtc_state *crtc_state;
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bool can_position;
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kmb = to_kmb(plane->dev);
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init_disp_cfg = kmb->init_disp_cfg[plane_id];
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fb = new_plane_state->fb;
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if (!fb || !new_plane_state->crtc)
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return 0;
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@ -99,6 +118,16 @@ static int kmb_plane_atomic_check(struct drm_plane *plane,
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new_plane_state->crtc_w < KMB_FB_MIN_WIDTH ||
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new_plane_state->crtc_h < KMB_FB_MIN_HEIGHT)
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return -EINVAL;
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/* Due to HW limitations, changing plane height or width after
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* initial plane configuration is not supported.
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*/
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if ((init_disp_cfg.width && init_disp_cfg.height) &&
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(init_disp_cfg.width != fb->width ||
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init_disp_cfg.height != fb->height)) {
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drm_dbg(&kmb->drm, "Cannot change plane height or width after initial configuration");
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return -EINVAL;
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}
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can_position = (plane->type == DRM_PLANE_TYPE_OVERLAY);
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crtc_state =
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drm_atomic_get_existing_crtc_state(state,
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@ -335,6 +364,7 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
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unsigned char plane_id;
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int num_planes;
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static dma_addr_t addr[MAX_SUB_PLANES];
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struct disp_cfg *init_disp_cfg;
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if (!plane || !new_plane_state || !old_plane_state)
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return;
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@ -357,7 +387,8 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
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}
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spin_unlock_irq(&kmb->irq_lock);
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src_w = (new_plane_state->src_w >> 16);
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init_disp_cfg = &kmb->init_disp_cfg[plane_id];
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src_w = new_plane_state->src_w >> 16;
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src_h = new_plane_state->src_h >> 16;
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crtc_x = new_plane_state->crtc_x;
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crtc_y = new_plane_state->crtc_y;
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@ -500,6 +531,16 @@ static void kmb_plane_atomic_update(struct drm_plane *plane,
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/* Enable DMA */
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kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
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/* Save initial display config */
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if (!init_disp_cfg->width ||
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!init_disp_cfg->height ||
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!init_disp_cfg->format) {
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init_disp_cfg->width = width;
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init_disp_cfg->height = height;
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init_disp_cfg->format = fb->format->format;
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}
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drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg,
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kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id)));
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@ -63,6 +63,12 @@ struct layer_status {
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u32 ctrl;
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};
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struct disp_cfg {
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unsigned int width;
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unsigned int height;
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unsigned int format;
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};
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struct kmb_plane *kmb_plane_init(struct drm_device *drm);
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void kmb_plane_destroy(struct drm_plane *plane);
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#endif /* __KMB_PLANE_H__ */
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@ -173,7 +173,11 @@ static void mxsfb_irq_disable(struct drm_device *drm)
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struct mxsfb_drm_private *mxsfb = drm->dev_private;
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mxsfb_enable_axi_clk(mxsfb);
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mxsfb->crtc.funcs->disable_vblank(&mxsfb->crtc);
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/* Disable and clear VBLANK IRQ */
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writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
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writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
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mxsfb_disable_axi_clk(mxsfb);
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}
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|
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@ -590,14 +590,14 @@ static const struct drm_display_mode k101_im2byl02_default_mode = {
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.clock = 69700,
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.hdisplay = 800,
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.hsync_start = 800 + 6,
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.hsync_end = 800 + 6 + 15,
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.htotal = 800 + 6 + 15 + 16,
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.hsync_start = 800 + 52,
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.hsync_end = 800 + 52 + 8,
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.htotal = 800 + 52 + 8 + 48,
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.vdisplay = 1280,
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.vsync_start = 1280 + 8,
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.vsync_end = 1280 + 8 + 48,
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.vtotal = 1280 + 8 + 48 + 52,
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.vsync_start = 1280 + 16,
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.vsync_end = 1280 + 16 + 6,
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.vtotal = 1280 + 16 + 6 + 15,
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.width_mm = 135,
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.height_mm = 217,
|
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|
|
|
|||
Loading…
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